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SCL:1; SRVR:BYAPR18MB2520; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: J5Esbs7A0jUrLwcuuV49/AVooE0fLVOF86gV0qjRPM3TVaXb688O2l3rcd7jOt19F7K7XpDSLV3iw6X12FN3AQoo8Glk1QBrTeBQyaLMXnT6HC0lZRYCQDIMTDvgvxbLs4ZuDCkfeU0dJ/HPCOq7L9Hv8lT47Ii3AddiX+K87sQMPGeKstfpETxoNejELF0CWHcOAX2K5DgNZcIYBnnw04VUdQWMBME9LzpFP1LOYt/s5+6xDN4gAOedIrjn2jILzxTZhGkigGtGEDIn0tYXrzR1kz9D/uyuteof1fagvK4qR1g5QibzIe3KfZlhVJ81pCMaEk89d8rS3T9J30+MzodsS/lQCJuric7Y3p0NC83wALITv1TTco/B0Xya+ZuQrewx6r5ljaP3xK8yDDMGxu36HA/KB8Xm9d3K63I74pE= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 8654bad1-eb66-46e3-c54b-08d705f6cd86 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jul 2019 11:56:26.2800 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2520 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-07-11_02:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH] common/octeontx2: add CNF95xx SoC support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Nithin Dabilpuram > Sent: Wednesday, July 10, 2019 10:32 PM > To: Jerin Jacob Kollanukkaran ; Nithin Kumar > Dabilpuram ; Vamsi Krishna Attunuru > ; John McNamara ; > Marko Kovacevic ; Pavan Nikhilesh > Bhagavatula ; Kiran Kumar Kokkilagadda > > Cc: dev@dpdk.org > Subject: [PATCH] common/octeontx2: add CNF95xx SoC support >=20 > Update platform support of CNF95xx in documentation and also, update the > HW cap based on PCI subsystem id and revision id. > This patch also changes HW capability handling to be based on PCI Revisio= n > ID. PCI Revision ID contains a unique identifier to identify chip, major = and > minor revisions. >=20 > Signed-off-by: Nithin Dabilpuram > pci_dev =3D container_of(event_dev->dev, struct rte_pci_device, > device); > + rc =3D rte_pci_read_config(pci_dev, &rev_id, 1, > RVU_PCI_REVISION_ID); > + if (rc !=3D 1) { > + otx2_err("Failed to read pci revision id, rc=3D%d", rc); > + goto error; > + } Please remove this code duplication in all the drivers. Other that it looks good to me.