From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id B64B28E6A for ; Thu, 14 Jan 2016 08:50:09 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP; 13 Jan 2016 23:50:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,293,1449561600"; d="scan'208";a="726733040" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 13 Jan 2016 23:50:03 -0800 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 13 Jan 2016 23:50:03 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 13 Jan 2016 23:50:02 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.215]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.117]) with mapi id 14.03.0248.002; Thu, 14 Jan 2016 15:50:01 +0800 From: "Xie, Huawei" To: Yuanhan Liu , "dev@dpdk.org" Thread-Topic: [PATCH v2 7/7] virtio: add 1.0 support Thread-Index: AdFOoCuaIMp9mFhvQbG10T5nROu3pg== Date: Thu, 14 Jan 2016 07:50:00 +0000 Message-ID: References: <1449719650-3482-1-git-send-email-yuanhan.liu@linux.intel.com> <1452581944-24838-1-git-send-email-yuanhan.liu@linux.intel.com> <1452581944-24838-8-git-send-email-yuanhan.liu@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.4.80] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "Michael S. Tsirkin" Subject: Re: [dpdk-dev] [PATCH v2 7/7] virtio: add 1.0 support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2016 07:50:10 -0000 On 1/12/2016 2:58 PM, Yuanhan Liu wrote:=0A= > Modern (v1.0) virtio pci device defines several pci capabilities.=0A= > Each cap has a configure structure corresponding to it, and the=0A= > cap.bar and cap.offset fields tell us where to find it.=0A= >=0A= > Firstly, we map the pci resources by rte_eal_pci_map_device().=0A= > We then could easily locate to a cfg structure by:=0A= =0A= s/Locate/Locate to/=0A= =0A= >=0A= > cfg_addr =3D dev->mem_resources[cap.bar].addr + cap.offset;=0A= >=0A= > Therefore, the entrance of enabling modern (v1.0) pci device support=0A= > is to iterate the pci capability lists, and to locate some configs=0A= > we care; and they are:=0A= >=0A= > - common cfg=0A= >=0A= > For generic virtio and virtuqueu configuration, such as setting/getting= =0A= =0A= typo for virtqueue=0A= =0A= > features, enabling a specific queue, and so on.=0A= >=0A= > - nofity cfg=0A= >=0A= > Combining with `queue_notify_off' from common cfg, we could use it to= =0A= > notify a specific virt queue.=0A= >=0A= > - device cfg=0A= >=0A= > Where virtio_net_config structure locates.=0A= is located=0A= > If any of above cap is not found, we fallback to the legacy virtio=0A= >=0A= [SNIP]=0A= > =0A= > =0A= > =0A= > +#define MODERN_READ_DEF(nr_bits, type) \=0A= > +static inline type \=0A= > +modern_read##nr_bits(type *addr) \=0A= > +{ \=0A= > + return *(volatile type *)addr; \=0A= > +}=0A= > +=0A= > +#define MODERN_WRITE_DEF(nr_bits, type) \=0A= > +static inline void \=0A= > +modern_write##nr_bits(type val, type *addr) \=0A= > +{ \=0A= > + *(volatile type *)addr =3D val; \=0A= > +}=0A= > +=0A= > +MODERN_READ_DEF (8, uint8_t)=0A= > +MODERN_WRITE_DEF(8, uint8_t)=0A= > +=0A= > +MODERN_READ_DEF (16, uint16_t)=0A= > +MODERN_WRITE_DEF(16, uint16_t)=0A= > +=0A= > +MODERN_READ_DEF (32, uint32_t)=0A= > +MODERN_WRITE_DEF(32, uint32_t)=0A= > +=0A= > +static inline void=0A= > +modern_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)=0A= > +{=0A= > + modern_write32((uint32_t)val, lo);=0A= > + modern_write32(val >> 32, hi);=0A= > +}=0A= > +=0A= =0A= This is normal mmio read/write operation. ioread8/16/32/64 or just=0A= readxx is more meaningful name here.=0A= > +static void=0A= [SNIP]=0A= > +=0A= > +static void=0A= > +modern_write_dev_config(struct virtio_hw *hw, uint64_t offset,=0A= > + void *src, int length)=0A= =0A= define src as const=0A= =0A= [snip]=0A= > =0A= > +static inline void *=0A= > +get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)=0A= =0A= No explicit inline for non performance critical functions.=0A= =0A= > +{=0A= > + uint8_t bar =3D cap->bar;=0A= > + uint32_t length =3D cap->length;=0A= > + uint32_t offset =3D cap->offset;=0A= > + uint8_t *base;=0A= > +=0A= > + if (unlikely(bar > 5)) {=0A= Don't use constant value number whenever possible=0A= =0A= No likely/unlikely for non performance critical functions=0A= =0A= > + PMD_INIT_LOG(ERR, "invalid bar: %u", bar);=0A= > + return NULL;=0A= > + }=0A= > +=0A= > + if (unlikely(offset + length > dev->mem_resource[bar].len)) {=0A= > + PMD_INIT_LOG(ERR,=0A= > + "invalid cap: overflows bar space: %u > %"PRIu64,=0A= > + offset + length, dev->mem_resource[bar].len);=0A= > + return NULL;=0A= > + }=0A= > +=0A= > + base =3D dev->mem_resource[bar].addr;=0A= > + if (unlikely(base =3D=3D NULL)) {=0A= > + PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);=0A= > + return NULL;=0A= > + }=0A= > +=0A= > + return base + offset;=0A= > +}=0A= > +=0A= > +static int=0A= > +virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)=0A= > +{=0A= > + uint8_t pos;=0A= > + struct virtio_pci_cap cap;=0A= > + int ret;=0A= > +=0A= > + if (rte_eal_pci_map_device(dev) < 0) {=0A= > + PMD_INIT_LOG(DEBUG, "failed to map pci device!");=0A= =0A= s /DEBUG/ERR/=0A= > + return -1;=0A= > + }=0A= > +=0A= > + ret =3D rte_eal_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);=0A= > + =0A= [snip]=0A= =0A=