From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 0545C8D96 for ; Mon, 18 Jan 2016 17:38:50 +0100 (CET) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP; 18 Jan 2016 08:38:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,313,1449561600"; d="scan'208";a="31622397" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga004.fm.intel.com with ESMTP; 18 Jan 2016 08:38:50 -0800 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 18 Jan 2016 08:38:49 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 18 Jan 2016 08:38:49 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.215]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.209]) with mapi id 14.03.0248.002; Tue, 19 Jan 2016 00:38:47 +0800 From: "Xie, Huawei" To: Yuanhan Liu , "dev@dpdk.org" Thread-Topic: [PATCH v4 7/8] virtio: add 1.0 support Thread-Index: AdFSDrOY024IClH9QuSR9YlAzWxVyw== Date: Mon, 18 Jan 2016 16:38:46 +0000 Message-ID: References: <1452581944-24838-1-git-send-email-yuanhan.liu@linux.intel.com> <1452832571-6156-1-git-send-email-yuanhan.liu@linux.intel.com> <1452832571-6156-8-git-send-email-yuanhan.liu@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.4.160] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 7/8] virtio: add 1.0 support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2016 16:38:51 -0000 On 1/15/2016 12:34 PM, Yuanhan Liu wrote:=0A= > Modern (v1.0) virtio pci device defines several pci capabilities.=0A= > Each cap has a configure structure corresponding to it, and the=0A= > cap.bar and cap.offset fields tell us where to find it.=0A= >=0A= =0A= [snip]=0A= =0A= > =0A= > +static void *=0A= > +get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)=0A= > +{=0A= > + uint8_t bar =3D cap->bar;=0A= > + uint32_t length =3D cap->length;=0A= > + uint32_t offset =3D cap->offset;=0A= > + uint8_t *base;=0A= > +=0A= > + if (bar > 5) {=0A= > + PMD_INIT_LOG(ERR, "invalid bar: %u", bar);=0A= > + return NULL;=0A= > + }=0A= > +=0A= > + if (offset + length > dev->mem_resource[bar].len) {=0A= =0A= offset + length could overflow 32bit limit=0A= =0A= > + PMD_INIT_LOG(ERR,=0A= > + "invalid cap: overflows bar space: %u > %"PRIu64,=0A= > + offset + length, dev->mem_resource[bar].len);=0A= > + return NULL;=0A= > + }=0A= > +=0A= > + =0A= =0A= [snip]=0A=