From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f171.google.com (mail-pf0-f171.google.com [209.85.192.171]) by dpdk.org (Postfix) with ESMTP id 51F2A5A86 for ; Wed, 16 Dec 2015 15:01:58 +0100 (CET) Received: by mail-pf0-f171.google.com with SMTP id v86so12608553pfa.2 for ; Wed, 16 Dec 2015 06:01:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mvista-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=9SgwKgVcvuOMfKrxgT4YJ5MsUDxH2TTcMrlsAo50IyU=; b=BftZfQEMvv6VxCalTWcr3UQSL1k9XDczaSLDZPOg7Wyi250/EOCliWVEy0UyjBTa9W FZhPCXnHEb+s0IuftRpmD9yUgaNXj/FkNpyGejmcVsddofyfG0LE+eHJOkgDQCTc2iNH /5phJyltOq07cDVmh+bERIecgLGfDrOr3YiTsGoB9yNKkASvvSYsRMDCtiYwlT5fThSQ xXM3uoh/36XSvWTTFBoFtWGKBktpEIrwxQEZMPFMAMpzBQuEIH9YFyxtIM/JXrjYxlnG YUvImSH/sZPEc0YsSiHfOFyEmg+b/kN6K8x57h3+cdbXTLUgM4DKPz/uRwFb31VWtp4h ALmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=9SgwKgVcvuOMfKrxgT4YJ5MsUDxH2TTcMrlsAo50IyU=; b=QjmesREsWcsH6hpZdLTtAL8BANpkyH3npyDwhBRt2XPsAOYHN+blogyLjogk3iGLWb rhVCVzFJu9m1VMJIuBVQrqn5e9VlNB0Z2f2DspOOWdkvTyQQfQK65QqQWTX6lBLT2GyH k41G4X7N90+mrMI3EZVAUtrGW1rJEV5mtt7hkjgNfHitlG6eaklIPu36Y7Zx1ft2GUeY 885Sd+SAmL4P533SKwaYACUf40RXwZSehka4bIkVTtHjUkdKG+Gbk9ESD2xeJuwkQ0ih mYujXrgzMq3jHiXXqArgV+sqqrJ72rlIbNkBMeSU4PNOCFyz+KoBZPxum2hABbFgzOBL 6OHw== X-Gm-Message-State: ALoCoQk+6d8+jJcXGVIxlT+MhMfKYJ46WsKne3M26S0i9NRFlmATAh2U2cbAXYhWN17JUZIyMr4JaVP3a7pAwzUd0FZ+Wf9ckiORbUsOEO/hvnK+rsQAJEk= MIME-Version: 1.0 X-Received: by 10.98.19.9 with SMTP id b9mr5478541pfj.28.1450274517669; Wed, 16 Dec 2015 06:01:57 -0800 (PST) Received: by 10.66.13.233 with HTTP; Wed, 16 Dec 2015 06:01:57 -0800 (PST) In-Reply-To: <20151216134850.GU29571@yliu-dev.sh.intel.com> References: <1450098032-21198-1-git-send-email-sshukla@mvista.com> <1450098032-21198-6-git-send-email-sshukla@mvista.com> <20151216134850.GU29571@yliu-dev.sh.intel.com> Date: Wed, 16 Dec 2015 19:31:57 +0530 Message-ID: From: Santosh Shukla To: Yuanhan Liu Content-Type: text/plain; charset=UTF-8 Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [ [PATCH v2] 05/13] virtio: change io_base datatype from uint32_t to uint64_type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Dec 2015 14:01:58 -0000 On Wed, Dec 16, 2015 at 7:18 PM, Yuanhan Liu wrote: > On Mon, Dec 14, 2015 at 06:30:24PM +0530, Santosh Shukla wrote: >> In x86 case io_base to store ioport address not more than 65535 ioports. i.e..0 >> to ffff but in non-x86 case in particular arm64 it need to store more than 32 >> bit address so changing io_base datatype from 32 to 64. >> >> Signed-off-by: Santosh Shukla >> --- >> drivers/net/virtio/virtio_ethdev.c | 2 +- >> drivers/net/virtio/virtio_pci.h | 4 ++-- >> 2 files changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c >> index d928339..620e0d4 100644 >> --- a/drivers/net/virtio/virtio_ethdev.c >> +++ b/drivers/net/virtio/virtio_ethdev.c >> @@ -1291,7 +1291,7 @@ eth_virtio_dev_init(struct rte_eth_dev *eth_dev) >> return -1; >> >> hw->use_msix = virtio_has_msix(&pci_dev->addr); >> - hw->io_base = (uint32_t)(uintptr_t)pci_dev->mem_resource[0].addr; >> + hw->io_base = (uint64_t)(uintptr_t)pci_dev->mem_resource[0].addr; > > I'd suggest to move the io_base assignment (and cast) into virtio_ioport_init() > so that we could do the correct cast there, say cast it to uint32_t for > X86, and uint64_t for others. > Ok. This was deliberately done considering your 1.0 virtio spec patch do care for uint64_t types and in arm64 case, If I plan to use those future patches, IMO it make more sense to me keep it in uint64_t way; Also in x86 case max address could of type 0x1000-101f and so forth; changing data-type to uint64_t default wont effect such address, right? And hw->io_base by looking at virtio_pci.h function like inb/outb etc.. takes io_base address as unsigned long types which is arch dependent; i.e.. 4 byte for 32 bit and 8 for 64 bit so the lower level rd/wr apis are taking care of data-types accordingly. > --yliu > >> >> /* Reset the device although not necessary at startup */ >> vtpci_reset(hw); >> diff --git a/drivers/net/virtio/virtio_pci.h b/drivers/net/virtio/virtio_pci.h >> index 3f4ff80..f3e4178 100644 >> --- a/drivers/net/virtio/virtio_pci.h >> +++ b/drivers/net/virtio/virtio_pci.h >> @@ -169,7 +169,7 @@ struct virtqueue; >> >> struct virtio_hw { >> struct virtqueue *cvq; >> - uint32_t io_base; >> + uint64_t io_base; >> uint32_t guest_features; >> uint32_t max_tx_queues; >> uint32_t max_rx_queues; >> @@ -231,7 +231,7 @@ outl_p(unsigned int data, unsigned int port) >> #endif >> >> #define VIRTIO_PCI_REG_ADDR(hw, reg) \ >> - (unsigned short)((hw)->io_base + (reg)) >> + (unsigned long)((hw)->io_base + (reg)) >> >> #define VIRTIO_READ_REG_1(hw, reg) \ >> inb((VIRTIO_PCI_REG_ADDR((hw), (reg)))) >> -- >> 1.7.9.5