From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1E99742D60; Tue, 4 Jul 2023 20:19:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 998DC40A4B; Tue, 4 Jul 2023 20:19:17 +0200 (CEST) Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) by mails.dpdk.org (Postfix) with ESMTP id C452F40042 for ; Tue, 4 Jul 2023 20:19:16 +0200 (CEST) Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-51d80c5c834so10570959a12.1 for ; Tue, 04 Jul 2023 11:19:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=netgate.com; s=google; t=1688494756; x=1691086756; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=WueSOTLeab2hjJ+o+whLMw/Ra4eIVw7UipMe0g5jc6A=; b=gJkcx/Ai6ci2WdBc0Xdo/POFa93/7u9EmgGwelyut+30zqMmQFc267zsHsbEkjqoV3 IYsnpbDYSi+81+LFuHfbGf+rDeiF0SJlHQwAfDI0563yrggu1emKDRComePgJoyyFB+i 6cX9BGKsOCmCqeg3lnbJz7xavyy8H2BGzZn1U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688494756; x=1691086756; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=WueSOTLeab2hjJ+o+whLMw/Ra4eIVw7UipMe0g5jc6A=; b=Vgm5VuZQo5zsXJzpzpDCt3oSEgtSgTmyJtGkbV76hYokEwVCFdYH0JJI7fwf/PWkoq 0NfFD9v+6QB+CYSWdKjZ+huAtenFVQ0cUnqn203twGqfSgrCVmBtJ63FOV5zA3i6S/zc nilA3ZnwiteUOaOCAyIwNpHDCdRY/5Sm7xZu10NaiCUW/68O8v70n/E9I3nQKP+474oN we+VnLtrf2fGvhxl4KaHFW4jSy6pOGW1UBPP9v5HRpxYU56L5vkexW2fIujt/fMe/9hr IyMvabND4C/lUsLaTtW7PSiAJToGh+EKvA8tOrvNs19zbWma1o7CTCGmtmJniVYPVvmW ZdNw== X-Gm-Message-State: ABy/qLbxaYfR2D8kMsOD1nWC31sgoMlBuBod+uEGUYr/dxTLmbmlb7MB nHTvYFQY82frkl5oilmqH/31MmEOIIcsf9C5lEsfUA== X-Google-Smtp-Source: APBJJlFLhi80+8QcYLmIRDenxh+lXWRFxWfpI/L1geSr9ymuZjKe7qdrg3QpUR6aELTlfX8vDZVmJxcZrmID2Lmgtpk= X-Received: by 2002:a05:6402:3589:b0:51b:fd09:9ec1 with SMTP id y9-20020a056402358900b0051bfd099ec1mr111945edc.0.1688494755799; Tue, 04 Jul 2023 11:19:15 -0700 (PDT) MIME-Version: 1.0 References: <20230614134018.2344-1-vratnikov@netgate.com> <20230614094638.2649366f@hermes.local> <8278146.NyiUUSuA9g@thomas> <20230704085530.1cf47bc7@hermes.local> In-Reply-To: <20230704085530.1cf47bc7@hermes.local> From: Vladimir Ratnikov Date: Tue, 4 Jul 2023 20:19:05 +0200 Message-ID: Subject: Re: [PATCH] eal/interrupts: Allow UIO interrupts when using igb_uio To: Stephen Hemminger Cc: hkalra@marvell.com, dev@dpdk.org, Junfeng Guo , Simei Su , qi.z.zhang@intel.com, Thomas Monjalon Content-Type: multipart/alternative; boundary="0000000000002172bc05ffad5214" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --0000000000002172bc05ffad5214 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On systems with I225 interfaces it works in interrupt mode(rx), so not only LSE interrupts are supported. I could try add rte_intr_cap_single functionality and recheck it twice(if several interfaces works in rx_mode=3Dinterrupt) But actually it worked with changes above(CPU utilization close to the zero, data passes through the interface etc) On Tue, Jul 4, 2023 at 5:55=E2=80=AFPM Stephen Hemminger wrote: > On Tue, 4 Jul 2023 12:45:54 +0200 > Vladimir Ratnikov wrote: > > > Sorry for a long reply, sure. > > > > Stephen, > > am I right that the most concern is about a place where interrupt > > capabilities check appears for non MSI-X support? > > What if having dedicated rte_intr_cap_single analog when there's no > support > > for MSI-X and just do the same(check capability, allocate interrupt > vector > > etc) ? > > > > > > Regards, > > -Vladimir > > With single interrupt, only link state interrupt is possible. > Does that work with igb_uio? It should, if not then yes > rte_intr_cap_single > or something like that is needed. > --0000000000002172bc05ffad5214 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On systems with I225 interfaces it works in interrupt mode= (rx), so not only LSE interrupts are supported.
I could try add=C2=A0 rte_intr_cap_single functionality and recheck it twice(if several interface= s works in rx_mode=3Dinterrupt)
But actually it worked with changes abov= e(CPU utilization close to the zero, data passes through the interface etc)=

= On Tue, Jul 4, 2023 at 5:55=E2=80=AFPM Stephen Hemminger <stephen@networkplumber.org> wrote:
On Tue, 4 Jul 202= 3 12:45:54 +0200
Vladimir Ratnikov <vratnikov@netgate.com> wrote:

> Sorry for a long reply, sure.
>
> Stephen,
> am I right that the most concern is about a place where interrupt
> capabilities check appears for non MSI-X support?
> What if having dedicated rte_intr_cap_single analog when there's n= o support
> for MSI-X and just do the same(check capability, allocate interrupt ve= ctor
> etc) ?
>
>
> Regards,
> -Vladimir

With single interrupt, only link state interrupt is possible.
Does that work with igb_uio?=C2=A0 It should, if not then yes rte_intr_cap_= single
or something like that is needed.
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