From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F0187430D3; Tue, 22 Aug 2023 21:23:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F1D1B40689; Tue, 22 Aug 2023 21:23:27 +0200 (CEST) Received: from mail-yw1-f170.google.com (mail-yw1-f170.google.com [209.85.128.170]) by mails.dpdk.org (Postfix) with ESMTP id 1D47B4021D for ; Tue, 22 Aug 2023 21:23:27 +0200 (CEST) Received: by mail-yw1-f170.google.com with SMTP id 00721157ae682-5922b96c5fcso22365387b3.0 for ; Tue, 22 Aug 2023 12:23:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; t=1692732206; x=1693337006; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=iZco31JYLkK68iMylCpvokK8P06DjF/Tm0LGeefC6Js=; b=S50TpjP3ANyMoDH7NLDHCs73d9F0QyTSHW2X26Ko73F+bMdodF7zb7imFCI3zPqPd6 oTW94BKeJ01JPwx96o/0aUP8Iej4EewtVf35DLu793UuWPYej4NEDK185DWDDMBVp/CP ++sHyIZBm5uxwRLHyGIX7cNyyG44ldwcjVfBo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692732206; x=1693337006; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=iZco31JYLkK68iMylCpvokK8P06DjF/Tm0LGeefC6Js=; b=UzkzEAe1pqJ9iJ3M3CM4qxqFgeuy8p8lplMJTBPTocza2s4zzHzzUkPCQ+qiLgNIzl 6ag8IRgYLiPDmaNxBYYRTiU8FjKXSmSoyJw8kMjvFVRUGC1Q38E7yjLpyMtJMCLx+62A NMJxn53pAT2hHKCFOFZjBYF+CxGTeVaKh13/0jl/qlz/GbGV9ocEStx57LUgLN6OF7nT t/09HD4ju6WkXjIQPpXfJvCDIBTruXyoHSSAIdHB/V30Sx+I+OcM3Tm6OhBm6XPueO0j 8IKBp87CHQKJ+aiyM6Ve35MCDLUsioLNQY6y6jUpPbPO4ztD3bYIRXl4cd+ygbUTc/1U 9X/A== X-Gm-Message-State: AOJu0YyemwaM+od9CSm90UXNtfuKW9mWXdDqlV3GM6T7Wio5bL5Y8PJ9 CRaJ6qGSwrQJjUKkw+NlWThWdMg3wxdDGwQCSqvVdRCjO4QjNy/1unE= X-Google-Smtp-Source: AGHT+IH6KdTFwsPc0dgZaQHBgmYY0rSVkaKsumFyoCU13E4gA1sgV3myDR+l1SMoZIe1sL9/WdcYtQQjwLXry10SI0s= X-Received: by 2002:a81:8402:0:b0:586:a684:e7b6 with SMTP id u2-20020a818402000000b00586a684e7b6mr11048578ywf.9.1692732206403; Tue, 22 Aug 2023 12:23:26 -0700 (PDT) MIME-Version: 1.0 References: <20230803075038.307012-1-david.marchand@redhat.com> <20230803075038.307012-7-david.marchand@redhat.com> In-Reply-To: <20230803075038.307012-7-david.marchand@redhat.com> From: Adam Hassick Date: Tue, 22 Aug 2023 15:23:54 -0400 Message-ID: Subject: Re: [PATCH 06/14] pci: define some command constants To: David Marchand Cc: dev@dpdk.org Content-Type: multipart/alternative; boundary="000000000000dce973060387ed11" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --000000000000dce973060387ed11 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Recheck-request: iol-sample-apps-testing, This email is a test of the community lab's retesting system, please ignore. Testing superseded reply on a patch. On Thu, Aug 3, 2023 at 3:51=E2=80=AFAM David Marchand wrote: > Define some PCI command constants and use them in existing drivers. > > Signed-off-by: David Marchand > --- > drivers/bus/pci/linux/pci_vfio.c | 8 ++++---- > drivers/event/dlb2/pf/dlb2_main.c | 8 +++----- > lib/pci/rte_pci.h | 4 +++- > 3 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/bus/pci/linux/pci_vfio.c > b/drivers/bus/pci/linux/pci_vfio.c > index 6d13cafdcf..f96b3ce7fb 100644 > --- a/drivers/bus/pci/linux/pci_vfio.c > +++ b/drivers/bus/pci/linux/pci_vfio.c > @@ -156,18 +156,18 @@ pci_vfio_enable_bus_memory(struct rte_pci_device > *dev, int dev_fd) > return -1; > } > > - ret =3D pread64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND); > + ret =3D pread64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMA= ND); > > if (ret !=3D sizeof(cmd)) { > RTE_LOG(ERR, EAL, "Cannot read command from PCI config > space!\n"); > return -1; > } > > - if (cmd & PCI_COMMAND_MEMORY) > + if (cmd & RTE_PCI_COMMAND_MEMORY) > return 0; > > - cmd |=3D PCI_COMMAND_MEMORY; > - ret =3D pwrite64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND)= ; > + cmd |=3D RTE_PCI_COMMAND_MEMORY; > + ret =3D pwrite64(dev_fd, &cmd, sizeof(cmd), offset + > RTE_PCI_COMMAND); > > if (ret !=3D sizeof(cmd)) { > RTE_LOG(ERR, EAL, "Cannot write command to PCI config > space!\n"); > diff --git a/drivers/event/dlb2/pf/dlb2_main.c > b/drivers/event/dlb2/pf/dlb2_main.c > index c6606a9bee..6dbaa2ff97 100644 > --- a/drivers/event/dlb2/pf/dlb2_main.c > +++ b/drivers/event/dlb2/pf/dlb2_main.c > @@ -33,7 +33,6 @@ > #define DLB2_PCI_EXP_DEVCTL2 40 > #define DLB2_PCI_LNKCTL2 48 > #define DLB2_PCI_SLTCTL2 56 > -#define DLB2_PCI_CMD 4 > #define DLB2_PCI_EXP_DEVSTA 10 > #define DLB2_PCI_EXP_DEVSTA_TRPND 0x20 > #define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000 > @@ -47,7 +46,6 @@ > #define DLB2_PCI_ERR_ROOT_STATUS 0x30 > #define DLB2_PCI_ERR_COR_STATUS 0x10 > #define DLB2_PCI_ERR_UNCOR_STATUS 0x4 > -#define DLB2_PCI_COMMAND_INTX_DISABLE 0x400 > #define DLB2_PCI_ACS_CAP 0x4 > #define DLB2_PCI_ACS_CTRL 0x6 > #define DLB2_PCI_ACS_SV 0x1 > @@ -286,7 +284,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) > > /* clear the PCI command register before issuing the FLR */ > > - off =3D DLB2_PCI_CMD; > + off =3D RTE_PCI_COMMAND; > cmd =3D 0; > if (rte_pci_write_config(pdev, &cmd, 2, off) !=3D 2) { > DLB2_LOG_ERR("[%s()] failed to write the pci command\n", > @@ -468,9 +466,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) > } > } > > - off =3D DLB2_PCI_CMD; > + off =3D RTE_PCI_COMMAND; > if (rte_pci_read_config(pdev, &cmd, 2, off) =3D=3D 2) { > - cmd &=3D ~DLB2_PCI_COMMAND_INTX_DISABLE; > + cmd &=3D ~RTE_PCI_COMMAND_INTX_DISABLE; > if (rte_pci_write_config(pdev, &cmd, 2, off) !=3D 2) { > DLB2_LOG_ERR("[%s()] failed to write the pci > command\n", > __func__); > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h > index a055a28592..bf2b2639f4 100644 > --- a/lib/pci/rte_pci.h > +++ b/lib/pci/rte_pci.h > @@ -32,10 +32,12 @@ extern "C" { > > #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */ > #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */ > -#define RTE_PCI_COMMAND 0x04 /* 16 bits */ > > /* PCI Command Register */ > +#define RTE_PCI_COMMAND 0x04 /* 16 bits */ > +#define RTE_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory spac= e > */ > #define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */ > +#define RTE_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ > > /* PCI Status Register */ > #define RTE_PCI_STATUS 0x06 /* 16 bits */ > -- > 2.41.0 > > --000000000000dce973060387ed11 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Recheck-request: iol-sample-apps-tes= ting,

This email is a test of the community lab's retestin= g system, please ignore. Testing superseded reply on a patch.

=
On Thu, Au= g 3, 2023 at 3:51=E2=80=AFAM David Marchand <david.marchand@redhat.com> wrote:
Define some PCI command constant= s and use them in existing drivers.

Signed-off-by: David Marchand <david.marchand@redhat.com>
---
=C2=A0drivers/bus/pci/linux/pci_vfio.c=C2=A0 | 8 ++++----
=C2=A0drivers/event/dlb2/pf/dlb2_main.c | 8 +++-----
=C2=A0lib/pci/rte_pci.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| 4 +++-
=C2=A03 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_v= fio.c
index 6d13cafdcf..f96b3ce7fb 100644
--- a/drivers/bus/pci/linux/pci_vfio.c
+++ b/drivers/bus/pci/linux/pci_vfio.c
@@ -156,18 +156,18 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev= , int dev_fd)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -1;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }

-=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D pread64(dev_fd, &cmd, sizeof(cmd), = offset + PCI_COMMAND);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D pread64(dev_fd, &cmd, sizeof(cmd), = offset + RTE_PCI_COMMAND);

=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret !=3D sizeof(cmd)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 RTE_LOG(ERR, EAL, &= quot;Cannot read command from PCI config space!\n");
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -1;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }

-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (cmd & PCI_COMMAND_MEMORY)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (cmd & RTE_PCI_COMMAND_MEMORY)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;

-=C2=A0 =C2=A0 =C2=A0 =C2=A0cmd |=3D PCI_COMMAND_MEMORY;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D pwrite64(dev_fd, &cmd, sizeof(cmd),= offset + PCI_COMMAND);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0cmd |=3D RTE_PCI_COMMAND_MEMORY;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D pwrite64(dev_fd, &cmd, sizeof(cmd),= offset + RTE_PCI_COMMAND);

=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret !=3D sizeof(cmd)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 RTE_LOG(ERR, EAL, &= quot;Cannot write command to PCI config space!\n");
diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2= _main.c
index c6606a9bee..6dbaa2ff97 100644
--- a/drivers/event/dlb2/pf/dlb2_main.c
+++ b/drivers/event/dlb2/pf/dlb2_main.c
@@ -33,7 +33,6 @@
=C2=A0#define DLB2_PCI_EXP_DEVCTL2 40
=C2=A0#define DLB2_PCI_LNKCTL2 48
=C2=A0#define DLB2_PCI_SLTCTL2 56
-#define DLB2_PCI_CMD 4
=C2=A0#define DLB2_PCI_EXP_DEVSTA 10
=C2=A0#define DLB2_PCI_EXP_DEVSTA_TRPND 0x20
=C2=A0#define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000
@@ -47,7 +46,6 @@
=C2=A0#define DLB2_PCI_ERR_ROOT_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x3= 0
=C2=A0#define DLB2_PCI_ERR_COR_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x1= 0
=C2=A0#define DLB2_PCI_ERR_UNCOR_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x4
-#define DLB2_PCI_COMMAND_INTX_DISABLE=C2=A0 =C2=A0 0x400
=C2=A0#define DLB2_PCI_ACS_CAP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A00x4
=C2=A0#define DLB2_PCI_ACS_CTRL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 0x6
=C2=A0#define DLB2_PCI_ACS_SV=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 0x1
@@ -286,7 +284,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)

=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* clear the PCI command register before issuin= g the FLR */

-=C2=A0 =C2=A0 =C2=A0 =C2=A0off =3D DLB2_PCI_CMD;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0off =3D RTE_PCI_COMMAND;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 cmd =3D 0;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rte_pci_write_config(pdev, &cmd, 2, off= ) !=3D 2) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 DLB2_LOG_ERR("= [%s()] failed to write the pci command\n",
@@ -468,9 +466,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }

-=C2=A0 =C2=A0 =C2=A0 =C2=A0off =3D DLB2_PCI_CMD;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0off =3D RTE_PCI_COMMAND;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rte_pci_read_config(pdev, &cmd, 2, off)= =3D=3D 2) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cmd &=3D ~DLB2_= PCI_COMMAND_INTX_DISABLE;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cmd &=3D ~RTE_P= CI_COMMAND_INTX_DISABLE;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rte_pci_write_c= onfig(pdev, &cmd, 2, off) !=3D 2) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 DLB2_LOG_ERR("[%s()] failed to write the pci command\n"= ;,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__func__);
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
index a055a28592..bf2b2639f4 100644
--- a/lib/pci/rte_pci.h
+++ b/lib/pci/rte_pci.h
@@ -32,10 +32,12 @@ extern "C" {

=C2=A0#define RTE_PCI_VENDOR_ID=C2=A0 =C2=A0 =C2=A0 0x00=C2=A0 =C2=A0 /* 16= bits */
=C2=A0#define RTE_PCI_DEVICE_ID=C2=A0 =C2=A0 =C2=A0 0x02=C2=A0 =C2=A0 /* 16= bits */
-#define RTE_PCI_COMMAND=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 0x04=C2=A0 =C2=A0 /* 16 bits */

=C2=A0/* PCI Command Register */
+#define RTE_PCI_COMMAND=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 0x04=C2=A0 =C2=A0 /* 16 bits */
+#define RTE_PCI_COMMAND_MEMORY 0x2=C2=A0 =C2=A0 =C2=A0/* Enable response i= n Memory space */
=C2=A0#define RTE_PCI_COMMAND_MASTER 0x4=C2=A0 =C2=A0 =C2=A0/* Bus Master E= nable */
+#define RTE_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
=C2=A0/* PCI Status Register */
=C2=A0#define RTE_PCI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x06=C2=A0 = =C2=A0 /* 16 bits */
--
2.41.0

--000000000000dce973060387ed11--