From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 97521A0C43; Thu, 10 Jun 2021 22:52:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1AD484067C; Thu, 10 Jun 2021 22:52:15 +0200 (CEST) Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) by mails.dpdk.org (Postfix) with ESMTP id B8B954003C for ; Thu, 10 Jun 2021 22:52:13 +0200 (CEST) Received: by mail-oi1-f176.google.com with SMTP id z3so3551982oib.5 for ; Thu, 10 Jun 2021 13:52:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; h=mime-version:from:date:message-id:subject:to:cc; bh=tq6WwRaU1RH5xXs3VZM6Q+P5GWVEUpDUXyG0i3zqw2U=; b=byLdA4/glbPD9x7oCsQc15U9QC9vVkVHMpLj5FyPgYuhnm9yBVIUZw2NWlLj4lkWTZ F4G9GCFYSbUMGBbDEZFzwcbt4tkr6Bz90eqBzDPZUxLccSm7paJ+p1XO44A2PYEHM+Qr vrob7AyOBE8Yt3EVeUlUY0rZdsA1omL1lHhlg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=tq6WwRaU1RH5xXs3VZM6Q+P5GWVEUpDUXyG0i3zqw2U=; b=t5ANsiaV2g65m1j6w4xpXPxxEy6klMFpeZxinEiE2y4WBcuvVE05Xl6LMThvq/ovPH b9QZSdo8ixeQlOAmAfmkrfSM06j+5yf/33oe9ayx43zzduSHoZcbY/S5qoa3cjfUS0q8 Kc7KrHaQER+kyDkEDqNM21SgKSWh1z4drS93fc8tAWTPYjTmkIiKMwQMMaqP1KX1uwd5 lhp0FPvSpVguWFzIWU2XSEcHe7coW4Nwk7P8iB6xejzycaiHo/Q1mqF7OEm25PueDfVE f6am6TLYT7WZDWygceszcccHROX6tPYLJ7eHJl3Da1KhF6I1TyXthkuf0lnU5VqkbXAb o96g== X-Gm-Message-State: AOAM533G2hiSctfIOztj8BefApt3vDFbQLsZthIrovaHq8JF81EZiMGt Q1OGDWjXNyVP/63Y7g3kUDdlMQcpnEmZ/HIQJF0QFw== X-Google-Smtp-Source: ABdhPJx6fzArifROOZKOvFNn811wpDbln5/0CtMM974cbKg5NE5MR6tVybUhMH4VJWA5fT5ourgR9TW/U/mfZoKGMVU= X-Received: by 2002:aca:53ca:: with SMTP id h193mr11140952oib.69.1623358332977; Thu, 10 Jun 2021 13:52:12 -0700 (PDT) MIME-Version: 1.0 From: Owen Hilyard Date: Thu, 10 Jun 2021 16:51:37 -0400 Message-ID: To: Aaron Conole , David Marchand Cc: dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-dev] Define statement with UB prevents compilation using UBSAN X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hello, While starting work on adding UBSAN to the community lab CI, I found that DPDK does not compile in its default configuration with UBSAN enabled, failing with the error message: ../drivers/net/bnx2x/bnx2x.c: In function =E2=80=98bnx2x_check_blocks_with_= parity3=E2=80=99: ../drivers/net/bnx2x/bnx2x.c:3363:4: error: case label does not reduce to an integer constant 3363 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | ^~~~ Working backward to the define statement, AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY is defined as #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1 << 31) While this does set the most significant bit of the integer, it also seems to make UBSAN unable to properly track its type. Replacing this with #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (-2147483648) or #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0b10000000000000000000000000000000) Allows compilation to finish on x86_64, but substantially breaks the style of the rest of the file. There are a few other places where this undefined behavior happens: ./drivers/baseband/acc100/rte_acc100_pmd.c:4490: value =3D (1 << 31) + (23 = << 8) + (1 << 6) + 7; ./drivers/net/bnxt/tf_core/tf_shadow_tcam.c:60:#define TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(hndl) (((hndl) & (1 << 31)) !=3D 0) ./drivers/net/bnxt/tf_core/tf_shadow_tcam.c:61:#define TF_SHADOW_TCAM_HB_HANDLE_CREATE(idx, be) ((1 << 31) | \ ./drivers/net/bnxt/tf_core/tf_shadow_tbl.c:60:#define TF_SHADOW_HB_HANDLE_IS_VALID(hndl) (((hndl) & (1 << 31)) !=3D 0) ./drivers/net/bnxt/tf_core/tf_shadow_tbl.c:61:#define TF_SHADOW_HB_HANDLE_CREATE(idx, be) ((1 << 31) | \ ./drivers/net/e1000/base/e1000_regs.h:197:#define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ ./drivers/net/e1000/base/e1000_regs.h:607:#define E1000_ETQF_QUEUE_ENABLE (1 << 31) ./drivers/net/igc/base/igc_regs.h:201:#define IGC_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ ./drivers/net/igc/base/igc_82575.h:248:#define IGC_ETQF_QUEUE_ENABLE (1 << 31) ./drivers/net/igc/base/igc_82575.h:271:#define IGC_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ ./drivers/net/bnx2x/ecore_hsi.h:2597: #define TRIGGER_MDUMP_ONCE (1 << 31) ./drivers/net/bnx2x/ecore_hsi.h:3904:#define IGU_REGULAR_BCLEANUP (0x1 << 31) ./drivers/net/bnx2x/ecore_reg.h:4366:#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1 << 31) ./drivers/net/bnx2x/ecore_reg.h:4391:#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1 << 31) ./drivers/net/ixgbe/base/ixgbe_type.h:4295:#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31) ./drivers/net/ixgbe/base/ixgbe_type.h:4325:#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31) ./drivers/crypto/qat/qat_sym_pmd.h:24:#define QAT_SYM_CAP_VALID (1 << 31) ./drivers/bus/fslmc/portal/dpaa2_hw_pvt.h:301:#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |=3D 1 << 31) ./drivers/raw/ioat/ioat_spec.h:329:#define CMDSTATUS_ACTIVE_MASK (1 << 31) ./drivers/common/mlx5/windows/mlx5_win_defs.h:114: IBV_RX_HASH_INNER =3D (1 << 31) Aside from normal CI, I don't have a good way to verify that a patch to fix this wouldn't have hard to detect effects. As far as I know, some of these drivers don't have DTS run on them in the course of CI, so I'm somewhat wary of trying to make a change to them. Until this is fixed, deploying UBSAN in any real capacity won't be useful since every patch will fail. What do the two of you think about steps moving forward on this problem? Owen Hilyard