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From: Shreyansh Jain <shreyansh.jain@nxp.com>
To: Rosen Xu <rosen.xu@intel.com>
Cc: dev@dpdk.org, declan.doherty@intel.com, tianfei.zhang@intel.com
Subject: Re: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus Second Scan, it should be scanned after PCI Bus
Date: Tue, 6 Mar 2018 11:50:23 +0530	[thread overview]
Message-ID: <CAJ5mUsXu4-VdVrS5m9D52U8GTHpWyP9viO55PCTyztFUMtgQUw@mail.gmail.com> (raw)
In-Reply-To: <1520300638-134954-4-git-send-email-rosen.xu@intel.com>

On Tue, Mar 6, 2018 at 7:13 AM, Rosen Xu <rosen.xu@intel.com> wrote:
> Signed-off-by: Rosen Xu <rosen.xu@intel.com>
> ---
>  lib/librte_eal/common/eal_common_bus.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/lib/librte_eal/common/eal_common_bus.c b/lib/librte_eal/common/eal_common_bus.c
> index 3e022d5..74bfa15 100644
> --- a/lib/librte_eal/common/eal_common_bus.c
> +++ b/lib/librte_eal/common/eal_common_bus.c
> @@ -70,15 +70,27 @@ struct rte_bus_list rte_bus_list =
>  rte_bus_scan(void)
>  {
>         int ret;
> -       struct rte_bus *bus = NULL;
> +       struct rte_bus *bus = NULL, *ifpga_bus = NULL;
>
>         TAILQ_FOREACH(bus, &rte_bus_list, next) {
> +               if (!strcmp(bus->name, "ifpga")) {
> +                       ifpga_bus = bus;
> +                       continue;
> +               }
> +
>                 ret = bus->scan();
>                 if (ret)
>                         RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\n",
>                                 bus->name);
>         }
>
> +       if (ifpga_bus) {
> +               ret = ifpga_bus->scan();
> +               if (ret)
> +                       RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\n",
> +                               ifpga_bus->name);
> +       }
> +

You are doing this just so that PCI scans are completed *before* ifpga scans?
Well, I understand that this certainly is an issue that we can't yet
define a priority ordering of bus scans.

But, I think what you are require is a simpler:

In the file ifpga_bus.c:

+RTE_REGISTER_BUS(IFPGA_BUS_NAME, rte_ifpga_bus.bus); <== this
...
...
#define RTE_REGISTER_BUS(nm, bus) \
RTE_INIT_PRIO(businitfn_ ##nm, 110); \

If you define your own version of RTE_REGISTER_BUS with the priority
number higher, it would be inserted later in the bus list.
rte_register_bus doesn't do any inherent ordering.
This would save the changes you are doing in the
lib/librte_eal/common/eal_common_bus.c file.

But I think there has to be a better provision of defining priority of
bus scans - I am sure when new devices come in, there would be
possibility of dependencies as in your case.

>         return 0;
>  }
>
> --
> 1.8.3.1
>

  reply	other threads:[~2018-03-06  6:21 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-06  1:43 [dpdk-dev] [RFC 0/4] Intel FPGA Bus Rosen Xu
2018-03-06  1:43 ` [dpdk-dev] [RFC 1/4] drivers/bus/ifpga:Intel FPGA Bus Lib Code Rosen Xu
2018-03-06  6:09   ` Shreyansh Jain
2018-03-06  9:24     ` Xu, Rosen
2018-03-06 10:05   ` Gaëtan Rivet
2018-03-09 15:34     ` Xu, Rosen
2018-03-06  1:43 ` [dpdk-dev] [RFC 2/4] lib/librte_eal/common:Add Intel FPGA Bus Running Command Parse Code Rosen Xu
2018-03-06  1:43 ` [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus Second Scan, it should be scanned after PCI Bus Rosen Xu
2018-03-06  6:20   ` Shreyansh Jain [this message]
2018-03-06 10:42     ` Xu, Rosen
2018-03-06 10:46       ` Gaëtan Rivet
2018-03-06 11:36         ` Bruce Richardson
2018-03-06 11:59           ` Gaëtan Rivet
2018-03-15  1:17             ` Xu, Rosen
2018-03-15  1:29           ` Xu, Rosen
2018-03-06  1:43 ` [dpdk-dev] [RFC 4/4] drivers/raw/ifpga_rawdev: Rawdev for Intel FPGA Device, it's a PCI Driver of FPGA Device Manager Rosen Xu
2018-03-06  6:48   ` Shreyansh Jain
2018-03-06  7:21     ` Shreyansh Jain
2018-03-07  4:10     ` Zhang, Tianfei

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