From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B1AD6A046B for ; Fri, 28 Jun 2019 19:11:46 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C67F849E0; Fri, 28 Jun 2019 19:11:44 +0200 (CEST) Received: from mail-vs1-f65.google.com (mail-vs1-f65.google.com [209.85.217.65]) by dpdk.org (Postfix) with ESMTP id BA6E337A2 for ; Fri, 28 Jun 2019 19:11:42 +0200 (CEST) Received: by mail-vs1-f65.google.com with SMTP id 190so4514717vsf.9 for ; Fri, 28 Jun 2019 10:11:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PdjLrahkVRkvZuUNxyvg4xl0tcEx2O4uqTcpUekNf2A=; b=Hc1vKOYU5YVKkxUMKhHxwK1uo+aomtQgL9EeP+YVg/3TwOg6Xk4xeDaePVlnRTNnA1 CqGVVLivlliIQWP2HyxPUa7h6fo1XTXGP/TU/UzdkFVaildtj3M7hQ8VO2ydWsKN9DvI uKOkp7DZ4J+p0icz+NMLvx53edaPJT7cpL4VVZns5uOPb6vXDi7n+m6HPRd2GWiuRawh m4h/8fTqeNRw0hcI5Wz8S2VlzrNNOVFyGo5dVlYvZptM5YA1JYXdxYQb9omVpAIpEhm4 VW+yAVPHmb7TzZ/L7SOIoKNeyd71EcF0uPvLRrRoNqiIhfk7UjVTsGdk2Qwur2dVg0+j BBlA== X-Gm-Message-State: APjAAAVQL/hG37udwCgLdMnam+ihccG2v40Q6NRfqbRNF3655UU+qrxb XPsB+rp5vLrHyP2oGDhwFhZHnQYh+R4xaSIndU6LMA== X-Google-Smtp-Source: APXvYqyNuK5/0tYcHXn11UV0JrTG6eZoEup7ViUJ48WSHTqbwfZ/3kyRMMkGtPB2qdIxNJW8Ax3L98viegb3ADClANk= X-Received: by 2002:a67:da99:: with SMTP id w25mr7294114vsj.141.1561741902111; Fri, 28 Jun 2019 10:11:42 -0700 (PDT) MIME-Version: 1.0 References: <20190628034406.5399-1-honnappa.nagarahalli@arm.com> <20190628163549.29160-1-honnappa.nagarahalli@arm.com> In-Reply-To: <20190628163549.29160-1-honnappa.nagarahalli@arm.com> From: David Marchand Date: Fri, 28 Jun 2019 19:11:31 +0200 Message-ID: To: Honnappa Nagarahalli Cc: dev , Thomas Monjalon , "Yigit, Ferruh" , "Ruifeng Wang (Arm Technology China)" , nd , dpdk stable Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH v2 1/2] test/rcu: increase the size of num cores variable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Jun 28, 2019 at 6:36 PM Honnappa Nagarahalli < honnappa.nagarahalli@arm.com> wrote: > num_cores is of type uint8_t. This results in the following > compilation error. > > test_rcu_qsbr_perf.c:649:16: error: comparison is always false > due to limited range of data type [-Werror=type-limits] > if (num_cores >= RTE_MAX_LCORE) { > ^~ > > RTE_MAX_LCORE is set to 256 for armv8 config. > > Fixes: e6a14121f4ae ("test/rcu: remove arbitrary limit on max core count") > Cc: stable@dpdk.org > > Signed-off-by: Honnappa Nagarahalli > Reviewed-by: Ruifeng Wang > --- > v2 > - Changed type of num_cores to 'unsigned int' and > related changes (David/Thomas) > > app/test/test_rcu_qsbr.c | 8 ++++---- > app/test/test_rcu_qsbr_perf.c | 16 ++++++++-------- > 2 files changed, 12 insertions(+), 12 deletions(-) > > diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c > index 943a1e370..ae359a987 100644 > --- a/app/test/test_rcu_qsbr.c > +++ b/app/test/test_rcu_qsbr.c > @@ -27,7 +27,7 @@ > #define TEST_RCU_QSBR_CNT_INIT 1 > > uint16_t enabled_core_ids[RTE_MAX_LCORE]; > -uint8_t num_cores; > +unsigned int num_cores; > > static uint32_t *keys; > #define TOTAL_ENTRY (1024 * 8) > @@ -389,7 +389,7 @@ test_rcu_qsbr_synchronize_reader(void *arg) > static int > test_rcu_qsbr_synchronize(void) > { > - int i; > + unsigned int i; > > printf("\nTest rte_rcu_qsbr_synchronize()\n"); > > @@ -890,8 +890,8 @@ test_rcu_qsbr_sw_sv_3qs(void) > static int > test_rcu_qsbr_mw_mv_mqs(void) > { > - int i, j; > - uint8_t test_cores; > + unsigned int i, j; > + unsigned int test_cores; > > writer_done = 0; > test_cores = num_cores / 4; > diff --git a/app/test/test_rcu_qsbr_perf.c b/app/test/test_rcu_qsbr_perf.c > index 363365f46..a085db852 100644 > --- a/app/test/test_rcu_qsbr_perf.c > +++ b/app/test/test_rcu_qsbr_perf.c > @@ -17,7 +17,7 @@ > > /* Check condition and return an error if true. */ > static uint16_t enabled_core_ids[RTE_MAX_LCORE]; > -static uint8_t num_cores; > +static unsigned int num_cores; > > static uint32_t *keys; > #define TOTAL_ENTRY (1024 * 8) > @@ -125,8 +125,8 @@ test_rcu_qsbr_writer_perf(void *arg) > static int > test_rcu_qsbr_perf(void) > { > - int i, sz; > - int tmp_num_cores; > + unsigned int i, sz; > sz is supposed to be a size_t. + unsigned int tmp_num_cores; > > writer_done = 0; > > @@ -188,8 +188,8 @@ test_rcu_qsbr_perf(void) > static int > test_rcu_qsbr_rperf(void) > { > - int i, sz; > - int tmp_num_cores; > + unsigned int i, sz; > Idem. + unsigned int tmp_num_cores; > > rte_atomic64_clear(&updates); > rte_atomic64_clear(&update_cycles); > @@ -234,7 +234,7 @@ test_rcu_qsbr_rperf(void) > static int > test_rcu_qsbr_wperf(void) > { > - int i, sz; > + unsigned int i, sz; > > rte_atomic64_clear(&checks); > rte_atomic64_clear(&check_cycles); > @@ -378,7 +378,7 @@ static int > test_rcu_qsbr_sw_sv_1qs(void) > { > uint64_t token, begin, cycles; > - int i, j, tmp_num_cores, sz; > + unsigned int i, j, tmp_num_cores, sz; > int32_t pos; > > writer_done = 0; > @@ -496,7 +496,7 @@ static int > test_rcu_qsbr_sw_sv_1qs_non_blocking(void) > { > uint64_t token, begin, cycles; > - int i, j, ret, tmp_num_cores, sz; > + unsigned int i, j, ret, tmp_num_cores, sz; > Idem. ret is an int. int32_t pos; > > writer_done = 0; > -- > 2.17.1 > > Let's focus on just the issue we want to fix and drop the changes on sz and ret. If you send a follow up patch on the issues for sz and ret, please also consider changing enabled_core_ids as an unsigned int array. Thanks. -- David Marchand