* [PATCH] dma/idxd: set defaults for GRPCFG traffic class
@ 2024-06-26 5:45 Shaiq Wani
2024-10-04 16:49 ` Bruce Richardson
0 siblings, 1 reply; 3+ messages in thread
From: Shaiq Wani @ 2024-06-26 5:45 UTC (permalink / raw)
To: dev, bruce.richardson
Set GRPCFG traffic class to value of 1 for best performance on current
generation of accelerators. Applicable to gen1 and gen2 devices.
Signed-off-by: Shaiq Wani <shaiq.wani@intel.com>
---
drivers/dma/idxd/idxd_pci.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/dma/idxd/idxd_pci.c b/drivers/dma/idxd/idxd_pci.c
index 81637d9420..e551b2232d 100644
--- a/drivers/dma/idxd/idxd_pci.c
+++ b/drivers/dma/idxd/idxd_pci.c
@@ -12,6 +12,14 @@
#define IDXD_VENDOR_ID 0x8086
#define IDXD_DEVICE_ID_SPR 0x0B25
+#define DEVICE_VERSION_1 0x100
+#define DEVICE_VERSION_2 0x200
+/*
+ * Set bits for Traffic Class A & B
+ * TC-A (Bits 2:0) and TC-B (Bits 5:3)
+ */
+#define IDXD_SET_TC_A_B 0x9
+
#define IDXD_PMD_DMADEV_NAME_PCI dmadev_idxd_pci
const struct rte_pci_id pci_id_idxd_map[] = {
@@ -177,6 +185,7 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
uint16_t grp_offset, wq_offset; /* how far into bar0 the regs are */
uint16_t wq_size, total_wq_size;
uint8_t lg2_max_batch, lg2_max_copy_size;
+ uint32_t version;
unsigned int i, err_code;
pci = rte_malloc(NULL, sizeof(*pci), 0);
@@ -190,6 +199,7 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
/* assign the bar registers, and then configure device */
pci->regs = dev->mem_resource[0].addr;
+ version = pci->regs->version;
grp_offset = (uint16_t)pci->regs->offsets[0];
pci->grp_regs = RTE_PTR_ADD(pci->regs, grp_offset * 0x100);
wq_offset = (uint16_t)(pci->regs->offsets[0] >> 16);
@@ -234,6 +244,8 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
for (i = 0; i < nb_groups; i++) {
pci->grp_regs[i].grpengcfg = 0;
pci->grp_regs[i].grpwqcfg[0] = 0;
+ if (version <= DEVICE_VERSION_2)
+ pci->grp_regs[i].grpflags |= IDXD_SET_TC_A_B;
}
for (i = 0; i < nb_wqs; i++)
idxd_get_wq_cfg(pci, i)[0] = 0;
@@ -278,6 +290,7 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
(lg2_max_batch << WQ_BATCH_SZ_SHIFT);
}
+ IDXD_PMD_DEBUG(" Device Version: %"PRIx32, version);
/* dump the group configuration to output */
for (i = 0; i < nb_groups; i++) {
IDXD_PMD_DEBUG("## Group %d", i);
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] dma/idxd: set defaults for GRPCFG traffic class
2024-06-26 5:45 [PATCH] dma/idxd: set defaults for GRPCFG traffic class Shaiq Wani
@ 2024-10-04 16:49 ` Bruce Richardson
2024-10-18 16:46 ` David Marchand
0 siblings, 1 reply; 3+ messages in thread
From: Bruce Richardson @ 2024-10-04 16:49 UTC (permalink / raw)
To: Shaiq Wani; +Cc: dev
On Wed, Jun 26, 2024 at 05:45:23AM +0000, Shaiq Wani wrote:
> Set GRPCFG traffic class to value of 1 for best performance on current
> generation of accelerators. Applicable to gen1 and gen2 devices.
>
> Signed-off-by: Shaiq Wani <shaiq.wani@intel.com>
> ---
> drivers/dma/idxd/idxd_pci.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] dma/idxd: set defaults for GRPCFG traffic class
2024-10-04 16:49 ` Bruce Richardson
@ 2024-10-18 16:46 ` David Marchand
0 siblings, 0 replies; 3+ messages in thread
From: David Marchand @ 2024-10-18 16:46 UTC (permalink / raw)
To: Shaiq Wani; +Cc: Bruce Richardson, dev
On Fri, Oct 4, 2024 at 6:49 PM Bruce Richardson
<bruce.richardson@intel.com> wrote:
>
> On Wed, Jun 26, 2024 at 05:45:23AM +0000, Shaiq Wani wrote:
> > Set GRPCFG traffic class to value of 1 for best performance on current
> > generation of accelerators. Applicable to gen1 and gen2 devices.
> >
> > Signed-off-by: Shaiq Wani <shaiq.wani@intel.com>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Applied, thanks.
--
David Marchand
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-10-18 16:46 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-06-26 5:45 [PATCH] dma/idxd: set defaults for GRPCFG traffic class Shaiq Wani
2024-10-04 16:49 ` Bruce Richardson
2024-10-18 16:46 ` David Marchand
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).