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References: <20231106170521.3064038-1-abdullah.sevincer@intel.com>
<20231106170521.3064038-2-abdullah.sevincer@intel.com>
In-Reply-To: <20231106170521.3064038-2-abdullah.sevincer@intel.com>
From: David Marchand <david.marchand@redhat.com>
Date: Mon, 6 Nov 2023 19:30:19 +0100
Message-ID: <CAJFAV8w_RjgMr1tyAGxQJeeDzairkaa5C_vBH7X=dMtM-bBKVA@mail.gmail.com>
Subject: Re: [PATCH v7 1/2] bus/pci: support PASID control
To: Abdullah Sevincer <abdullah.sevincer@intel.com>, thomas@monjalon.net
Cc: dev@dpdk.org, jerinj@marvell.com, mike.ximing.chen@intel.com,
bruce.richardson@intel.com
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On Mon, Nov 6, 2023 at 6:05=E2=80=AFPM Abdullah Sevincer
<abdullah.sevincer@intel.com> wrote:
>
> Add an internal API to control PASID for a given PCIe device.
>
> For kernels when PASID enabled by default it breaks DLB functionality,
> hence disabling PASID is required for DLB to function properly.
>
> PASID capability is not exposed to users hence offset can not be
> retrieved by rte_pci_find_ext_capability() api. Therefore, api
> implemented in this commit accepts an offset for PASID with an enable
> flag which is used to enable/disable PASID.
>
> Signed-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>
> ---
> drivers/bus/pci/pci_common.c | 7 +++++++
> drivers/bus/pci/rte_bus_pci.h | 13 +++++++++++++
> drivers/bus/pci/version.map | 1 +
> lib/pci/rte_pci.h | 4 ++++
> 4 files changed, 25 insertions(+)
>
> diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
> index 921d957bf6..ecf080c5d7 100644
> --- a/drivers/bus/pci/pci_common.c
> +++ b/drivers/bus/pci/pci_common.c
> @@ -938,6 +938,13 @@ rte_pci_set_bus_master(const struct rte_pci_device *=
dev, bool enable)
> return 0;
> }
>
> +int
> +rte_pci_pasid_set_state(const struct rte_pci_device *dev, off_t offset, =
bool enable)
> +{
> + uint16_t pasid =3D enable;
> + return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) <=
0 ? -1 : 0;
> +}
I don't see much point in providing a wrapper that does nothing more
than call rte_pci_write_config() and let the driver pass the right
offsets.
If anything, can't this wrapper find out about the pasid offset itself?
There is a extended capability for this, so I would expect it can be used.
Something like (only compile tested):
diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
index ba5e280d33..2ca28bd4d4 100644
--- a/drivers/bus/pci/pci_common.c
+++ b/drivers/bus/pci/pci_common.c
@@ -939,13 +939,18 @@ rte_pci_set_bus_master(const struct
rte_pci_device *dev, bool enable)
}
int
-rte_pci_pasid_set_state(const struct rte_pci_device *dev,
- off_t offset, bool enable)
+rte_pci_pasid_set_state(const struct rte_pci_device *dev, bool enable)
{
- uint16_t pasid =3D enable;
- return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0
- ? -1
- : 0;
+ uint16_t state =3D enable;
+ off_t pasid_offset;
+ int ret =3D -1;
+
+ pasid_offset =3D rte_pci_find_ext_capability(dev,
RTE_PCI_EXT_CAP_ID_PASID);
+ if (pasid_offset >=3D 0 && rte_pci_write_config(dev, &state,
sizeof(state),
+ pasid_offset + RTE_PCI_PASID_CTRL) =3D=3D sizeof(st=
ate))
+ ret =3D 0;
+
+ return ret;
}
struct rte_pci_bus rte_pci_bus =3D {
diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
index f07bf9b588..6d5dbc1d50 100644
--- a/drivers/bus/pci/rte_bus_pci.h
+++ b/drivers/bus/pci/rte_bus_pci.h
@@ -160,14 +160,14 @@ int rte_pci_set_bus_master(const struct
rte_pci_device *dev, bool enable);
*
* @param dev
* A pointer to a rte_pci_device structure.
- * @param offset
- * Offset of the PASID external capability.
* @param enable
* Flag to enable or disable PASID.
+ *
+ * @return
+ * 0 on success, -1 on error in PCI config space read/write.
*/
__rte_internal
-int rte_pci_pasid_set_state(const struct rte_pci_device *dev,
- off_t offset, bool enable);
+int rte_pci_pasid_set_state(const struct rte_pci_device *dev, bool enable)=
;
/**
* Read PCI config space.
diff --git a/drivers/event/dlb2/pf/dlb2_main.c
b/drivers/event/dlb2/pf/dlb2_main.c
index 61a7b39eef..bd1ee4af27 100644
--- a/drivers/event/dlb2/pf/dlb2_main.c
+++ b/drivers/event/dlb2/pf/dlb2_main.c
@@ -26,7 +26,6 @@
#define PF_ID_ZERO 0 /* PF ONLY! */
#define NO_OWNER_VF 0 /* PF ONLY! */
#define NOT_VF_REQ false /* PF ONLY! */
-#define DLB2_PCI_PASID_CAP_OFFSET 0x148 /* PASID capability offse=
t */
static int
dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev)
@@ -518,8 +517,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
/* Disable PASID if it is enabled by default, which
* breaks the DLB if enabled.
*/
- off =3D DLB2_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL;
- if (rte_pci_pasid_set_state(pdev, off, false)) {
+ if (rte_pci_pasid_set_state(pdev, false)) {
DLB2_LOG_ERR("[%s()] failed to write the pcie config
space at offset %d\n",
__func__, (int)off);
return -1;
--=20
David Marchand