From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 88BFA432F0; Fri, 10 Nov 2023 09:03:28 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5471A40A89; Fri, 10 Nov 2023 09:03:28 +0100 (CET) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id 561D34026D for ; Fri, 10 Nov 2023 09:03:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1699603405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xq/KpysfuTKbb51LAtKm62JJvpnkXbOvqT68LZZr2PQ=; b=VBAJoghJg/DbAiyHxjwPPg0WLBPymTVryXD8+I9+1FiHM0OysmaLWhl4nzaZ6jiJ2nYJ93 cVEWk8Afl0sASCIT2l7o4iTcvWn3dVtGdhRuWzGAnmSq+aTSD/EmlXr4HXAm7AUGlZu0Vw ZlUEbJ3/HSFBzm7m33q39NRICndFlnY= Received: from mail-lj1-f198.google.com (mail-lj1-f198.google.com [209.85.208.198]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-644-Eweqyzm0MWy5wNbvooKE5A-1; Fri, 10 Nov 2023 03:03:24 -0500 X-MC-Unique: Eweqyzm0MWy5wNbvooKE5A-1 Received: by mail-lj1-f198.google.com with SMTP id 38308e7fff4ca-2c562dab105so16694811fa.1 for ; Fri, 10 Nov 2023 00:03:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699603403; x=1700208203; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xq/KpysfuTKbb51LAtKm62JJvpnkXbOvqT68LZZr2PQ=; b=GiletLlYEDI4ZPEopoVFw011Xbui3n9+JdIWK1V4ZQSsKkvTScFZgFLAl+vEXQyQqD dNf4tJ+3ziTG9cnnfznIfCh5Xe1F5mYXCoDSSTR3IdUpSSmwc021qA9OCLYSkEOs+oR8 s4Vwv1GN08egZ1jq6sFGJ9ZfoUXGCaqSHsnIAhtT2S6CToy459kEj3hqGU4qPzZMj37q kpGJSPHPWQB5qDHx7vRl/nVYVhnHOB3Qu8T65wJHIDcRj9v9vmb/L5onEfYivmBER76s o97A/euUX+dsV62BYaLyk2mdViH3LwBj3cW1eqP0ifxC97cRMzNKIHV6mG3b8wbBALt8 wfqg== X-Gm-Message-State: AOJu0YykB/z11T2VmK+Q8rC6tKPmByp9VaWAGqgo5/1eMG7IJo3IKONF VBhmuEZceKH/zzB+fh9hk3O5HDGzQyEKF/Y3SYDVGdqPzkzeGtcNI8txpUIjFF9HDjwwpzaMr6R vL7BjPpPgF4E9B5Krsd0= X-Received: by 2002:a05:651c:10aa:b0:2c6:edf1:b05e with SMTP id k10-20020a05651c10aa00b002c6edf1b05emr654858ljn.15.1699603403016; Fri, 10 Nov 2023 00:03:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IFsClO3CDDEbtjE95yQBt4CVyPcGorkOii6hzy753tWkqMPHNrd+PWY1XSzKzypXKqaXAECfP1K5NM6Okqnz1Y= X-Received: by 2002:a05:651c:10aa:b0:2c6:edf1:b05e with SMTP id k10-20020a05651c10aa00b002c6edf1b05emr654851ljn.15.1699603402675; Fri, 10 Nov 2023 00:03:22 -0800 (PST) MIME-Version: 1.0 References: <20231106170521.3064038-1-abdullah.sevincer@intel.com> <20231106170521.3064038-2-abdullah.sevincer@intel.com> In-Reply-To: From: David Marchand Date: Fri, 10 Nov 2023 09:03:11 +0100 Message-ID: Subject: Re: [PATCH v7 1/2] bus/pci: support PASID control To: "Sevincer, Abdullah" Cc: "thomas@monjalon.net" , "dev@dpdk.org" , "jerinj@marvell.com" , "Chen, Mike Ximing" , "Richardson, Bruce" , Chenbo Xia , Nipun Gupta X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hello, On Mon, Nov 6, 2023 at 7:50=E2=80=AFPM Sevincer, Abdullah wrote: > Hi David, > >++ pasid_offset =3D rte_pci_find_ext_capability(dev, > >+RTE_PCI_EXT_CAP_ID_PASID); > > That rte_pci_find_ext_capability() api does not work for PASID since PAS= ID is not exposed to user from kernel. > So, we can not retrieve offset. Instead we came up with a solution that p= asses an offset to an internal function to disable PASID and make the funct= ion internal so we can change it later. > When the linux limitation is lifted we can re-write the functions and use= rte_pci_find_ext_capability api to retrieve offset and your > solution above can be done. Adding PCI bus maintainers, Chenbo and Nipun. Ok, that is indeed an issue. I found some patches exposing this capability with vfio-pci but I am not sure what is the latest work on the topic. Do you have pointers to the latest kernel patches? In any case, even if, in the future, the kernel exposes this capability, we need to live with the current behavior (and probably for a long time). As the discovery of pasid offset is not possible, the common API merit is low, but at least it shows what is being done by the driver. Can we make a change so that this new API takes only the offset to the pasid *structure* and not to the exact register controlling the feature? It should be something like: $ git diff diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index ba5e280d33..c66cefcd63 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -943,9 +943,9 @@ rte_pci_pasid_set_state(const struct rte_pci_device *de= v, off_t offset, bool enable) { uint16_t pasid =3D enable; - return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0 - ? -1 - : 0; + + return rte_pci_write_config(dev, &pasid, sizeof(pasid), + offset + RTE_PCI_PASID_CTRL) < 0 ? -1 : 0; } struct rte_pci_bus rte_pci_bus =3D { diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index f07bf9b588..b1d17996cb 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -161,9 +161,12 @@ int rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable); * @param dev * A pointer to a rte_pci_device structure. * @param offset - * Offset of the PASID external capability. + * Offset of the PASID external capability structure. * @param enable * Flag to enable or disable PASID. + * + * @return + * 0 on success, -1 on error in PCI config space read/write. */ __rte_internal int rte_pci_pasid_set_state(const struct rte_pci_device *dev, diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 61a7b39eef..a95d3227a4 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -518,8 +518,8 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) /* Disable PASID if it is enabled by default, which * breaks the DLB if enabled. */ - off =3D DLB2_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL; - if (rte_pci_pasid_set_state(pdev, off, false)) { + off =3D DLB2_PCI_PASID_CAP_OFFSET; + if (rte_pci_pasid_set_state(pdev, off, false) < 0) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", __func__, (int)off); return -1; diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 0d2d8d8fed..94219792de 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -101,7 +101,7 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services = */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface *= / -#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID= */ +#define RTE_PCI_EXT_CAP_ID_PASID 0x1b /* Process Address Space ID= */ /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Stat= us */ --=20 David Marchand