From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7A5AA0540; Mon, 13 Jul 2020 13:33:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 44FB51D635; Mon, 13 Jul 2020 13:33:56 +0200 (CEST) Received: from us-smtp-delivery-1.mimecast.com (us-smtp-1.mimecast.com [205.139.110.61]) by dpdk.org (Postfix) with ESMTP id EAB791D633 for ; Mon, 13 Jul 2020 13:33:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1594640034; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=12Cir0MDLyrLYUenBWWKp8aRScrtRuJb2SSN8HqIkGE=; b=GR2SB1KChXhDWexI/8VqnLILVEQ1LBG7jK1OrzjRfP5SOP96pF9jFBfsgan28I6lMe5DYT P6cHmZGghnZYus+I7OLLntcrR9cXrbmefkUFAM49AwDrKhM+vSSbBDeMfmS4gf2GDbSzyL sJ9BQaPT8pyCKcYPvIrmgh6z+vIBUrc= Received: from mail-ua1-f71.google.com (mail-ua1-f71.google.com [209.85.222.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-272-3bWJ6tlbMCiL9d3H7vsE7w-1; Mon, 13 Jul 2020 07:33:52 -0400 X-MC-Unique: 3bWJ6tlbMCiL9d3H7vsE7w-1 Received: by mail-ua1-f71.google.com with SMTP id 64so6408971uaz.3 for ; Mon, 13 Jul 2020 04:33:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=12Cir0MDLyrLYUenBWWKp8aRScrtRuJb2SSN8HqIkGE=; b=BJbyt5pGFoo0GgX+tUlOlGo/ctcs6p7iU2zA2WYQLTnnJMO9GhDxynYcnu4tw9VauR hgoSh0vTMTXwqztNYU+1GnZBcyJqgqBsmFWXRWZRE8Gb60mrkQbDDt6xBCYvntgLxIaR VBN4VuqE2tbK5aGlviVSXknDkWVFMQckVfkpaO0ZFf6QDRYlrA5Ed4vY4/3Sj6xf1Shs nSOEmBrMQ/EQLDOeKTvIjCrmAG/gZhGezPSgACJdLdDDh5Pf39Gnz0NeUwQ/h5W5u582 JZimYe3S/EcXS0tVj3oDBm9rSOyGnkXuAfhIrsglsV6PW7RnCjFa049YPtFGz+b7DFiu fgbA== X-Gm-Message-State: AOAM533dfXgF2hyXibU5bPxF6V8NgSwWlIzDAKw0VrWJCkmVL41GeCQH sQSJ1LePRbnMtsH0knO39yzEcAYIIWA2Vqj/ecA+pG9lNGktptQwqsLgYM98BFQZwb9XTRgc2Ti UVOhTYBxrb2u5ry6+3sI= X-Received: by 2002:a1f:255:: with SMTP id 82mr60287015vkc.39.1594640032094; Mon, 13 Jul 2020 04:33:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJys/9Ht7cM3KC0ps1BKnA4sFZa73nSVzeR7gNAnTfNUvCCPT3tZaMf6Puhb0/X5YTdMxeNHbe3MGOr5MxiMIzg= X-Received: by 2002:a1f:255:: with SMTP id 82mr60286997vkc.39.1594640031867; Mon, 13 Jul 2020 04:33:51 -0700 (PDT) MIME-Version: 1.0 References: <869034e585604e3cc2f1131219478e634a1d3f64.1594638050.git.vladimir.medvedkin@intel.com> In-Reply-To: <869034e585604e3cc2f1131219478e634a1d3f64.1594638050.git.vladimir.medvedkin@intel.com> From: David Marchand Date: Mon, 13 Jul 2020 13:33:40 +0200 Message-ID: To: Vladimir Medvedkin Cc: dev , Jerin Jacob Kollanukkaran , Ray Kinsella , Thomas Monjalon , "Ananyev, Konstantin" , Bruce Richardson X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v6 1/8] eal/x86: introduce AVX 512-bit type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Jul 13, 2020 at 1:11 PM Vladimir Medvedkin wrote: > > New data type to manipulate 512 bit AVX values. > > Signed-off-by: Vladimir Medvedkin > Acked-by: Konstantin Ananyev > --- > lib/librte_eal/x86/include/rte_vect.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h > index df5a60762..30dcfd5e7 100644 > --- a/lib/librte_eal/x86/include/rte_vect.h > +++ b/lib/librte_eal/x86/include/rte_vect.h > @@ -13,6 +13,7 @@ > > #include > #include > +#include > #include "generic/rte_vect.h" > > #if (defined(__ICC) || \ > @@ -90,6 +91,24 @@ __extension__ ({ \ > }) > #endif /* (defined(__ICC) && __ICC < 1210) */ > > +#ifdef __AVX512F__ > + > +#define RTE_X86_ZMM_SIZE (sizeof(__m512i)) > +#define RTE_X86_ZMM_MASK (ZMM_SIZE - 1) Please fix: #define RTE_X86_ZMM_MASK (RTE_X86_ZMM_SIZE - 1) > + > +typedef union __rte_x86_zmm { > + __m512i z; > + ymm_t y[RTE_X86_ZMM_SIZE / sizeof(ymm_t)]; > + xmm_t x[RTE_X86_ZMM_SIZE / sizeof(xmm_t)]; > + uint8_t u8[RTE_X86_ZMM_SIZE / sizeof(uint8_t)]; > + uint16_t u16[RTE_X86_ZMM_SIZE / sizeof(uint16_t)]; > + uint32_t u32[RTE_X86_ZMM_SIZE / sizeof(uint32_t)]; > + uint64_t u64[RTE_X86_ZMM_SIZE / sizeof(uint64_t)]; > + double pd[RTE_X86_ZMM_SIZE / sizeof(double)]; > +} __rte_aligned(RTE_X86_ZMM_SIZE) __rte_x86_zmm_t; > + > +#endif /* __AVX512F__ */ > + > #ifdef __cplusplus > } > #endif > -- > 2.17.1 >