From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D62EA04BC; Thu, 8 Oct 2020 18:46:01 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2B9951B679; Thu, 8 Oct 2020 18:45:59 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by dpdk.org (Postfix) with ESMTP id 27EF029AC for ; Thu, 8 Oct 2020 18:45:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1602175554; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=9+iHZBxeMLuApcXalmzARC4n15/QXn05OJbUhylcLLw=; b=Yx9Kk6mD7Nkvu3Ebicy6NJaWt5rWPU+/b9+S9rsD3qFDlzVLsFXHS1f8etAuvXoOsEgi8D e2zr9arJnYAYySXQKJ/jn6jrG8O4v4KzRbMutELXR6ni/irIuFQyyxFGmjmu7Nsru/vU/E jtZHMT5aNMNUJzE8GyO0KMxkG24iVkw= Received: from mail-vs1-f71.google.com (mail-vs1-f71.google.com [209.85.217.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-66-PL-AS1tpPeuiyOrG1KOZ9g-1; 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Thu, 08 Oct 2020 09:45:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzp9B156BwM08bq/UH2MjT04ttmzygT7G6I9Vokr7HXStHLCfVYcnMzO/HbBvv2ywN1rWo7HFlO7nzO2ZhohgE= X-Received: by 2002:ab0:5926:: with SMTP id n35mr5108274uad.126.1602175550020; Thu, 08 Oct 2020 09:45:50 -0700 (PDT) MIME-Version: 1.0 References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-3-ciara.power@intel.com> In-Reply-To: <20200930130415.11211-3-ciara.power@intel.com> From: David Marchand Date: Thu, 8 Oct 2020 18:45:39 +0200 Message-ID: To: Ciara Power Cc: dev , Ruifeng Wang , Jerin Jacob , Honnappa Nagarahalli , David Christensen , Jan Viktorin , Bruce Richardson , Konstantin Ananyev Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dmarchan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v3 02/18] eal: add default SIMD bitwidth values X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Sep 30, 2020 at 3:09 PM Ciara Power wrote: > > Each arch has a define for the default SIMD bitwidth value, this is used > on EAL init to set the config max SIMD bitwidth. > > Cc: Ruifeng Wang > Cc: Jerin Jacob > Cc: Honnappa Nagarahalli > Cc: David Christensen > > Signed-off-by: Ciara Power > > --- > v3: > - Removed unnecessary define in generic rte_vect.h > - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE. > v2: Changed default bitwidth for Arm to 128. > --- > lib/librte_eal/arm/include/rte_vect.h | 2 ++ > lib/librte_eal/common/eal_common_options.c | 3 +++ > lib/librte_eal/ppc/include/rte_vect.h | 2 ++ > lib/librte_eal/x86/include/rte_vect.h | 2 ++ > 4 files changed, 9 insertions(+) > > diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h > index 01c51712a1..a3508e69d5 100644 > --- a/lib/librte_eal/arm/include/rte_vect.h > +++ b/lib/librte_eal/arm/include/rte_vect.h > @@ -14,6 +14,8 @@ > extern "C" { > #endif > > +#define RTE_DEFAULT_SIMD_BITWIDTH UINT16_MAX > + > typedef int32x4_t xmm_t; > > #define XMM_SIZE (sizeof(xmm_t)) > diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c > index e9117a96af..d412cae89b 100644 > --- a/lib/librte_eal/common/eal_common_options.c > +++ b/lib/librte_eal/common/eal_common_options.c > @@ -35,6 +35,7 @@ > #ifndef RTE_EXEC_ENV_WINDOWS > #include > #endif > +#include > > #include "eal_internal_cfg.h" > #include "eal_options.h" > @@ -344,6 +345,8 @@ eal_reset_internal_config(struct internal_config *internal_cfg) > internal_cfg->user_mbuf_pool_ops_name = NULL; > CPU_ZERO(&internal_cfg->ctrl_cpuset); > internal_cfg->init_complete = 0; > + internal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH; > + internal_cfg->max_simd_bitwidth.locked = 0; Does the previous patch work without this one? In any case, it seems a whole to me and reading one of Olivier's questions on the default value, I would squash them together. > } > > static int > diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h > index b0545c878c..70fbd0c423 100644 > --- a/lib/librte_eal/ppc/include/rte_vect.h > +++ b/lib/librte_eal/ppc/include/rte_vect.h > @@ -15,6 +15,8 @@ > extern "C" { > #endif > > +#define RTE_DEFAULT_SIMD_BITWIDTH 256 > + > typedef vector signed int xmm_t; > > #define XMM_SIZE (sizeof(xmm_t)) > diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h > index df5a607623..b1df75aca7 100644 > --- a/lib/librte_eal/x86/include/rte_vect.h > +++ b/lib/librte_eal/x86/include/rte_vect.h > @@ -35,6 +35,8 @@ > extern "C" { > #endif > > +#define RTE_DEFAULT_SIMD_BITWIDTH 256 > + > typedef __m128i xmm_t; > > #define XMM_SIZE (sizeof(xmm_t)) > -- > 2.17.1 > -- David Marchand