From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5FDF1A327F for ; Mon, 21 Oct 2019 21:19:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2034D1BEB1; Mon, 21 Oct 2019 21:19:25 +0200 (CEST) Received: from us-smtp-1.mimecast.com (us-smtp-delivery-1.mimecast.com [205.139.110.120]) by dpdk.org (Postfix) with ESMTP id A9A601BEA7 for ; Mon, 21 Oct 2019 21:19:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571685563; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/JeSAEVL52xrSEhyMGWby/XmjLTklLMUTTT8TiVpIKE=; b=Zz45EKmxx5EAMvChA7QEo9Elkms4YL6GINYMG008at0OhVq+/wVv0Z8FS33phy98DSd7fj SjQ57ucbxC9SxGHbgyg019JyDXTQPwj0gV/TOiCfmaTicSxETANQ8i1Cvjx4/pAWgelspl 1ZCRkPOiDr7K0Hfjxr/SuR52yTrJAtE= Received: from mail-vs1-f71.google.com (mail-vs1-f71.google.com [209.85.217.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-254-Aw8yUBe0O2Gj1b-VZmoZGg-1; Mon, 21 Oct 2019 15:19:21 -0400 Received: by mail-vs1-f71.google.com with SMTP id p10so3230714vsn.1 for ; Mon, 21 Oct 2019 12:19:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=SlsOXDMC/BWo26GrRdk/3cE99Hiauk2Lk0ziysnD4mM=; b=VVPbqe7V7a7ydF4XUpOymT+DlFBFPdUtSs+ngQffpOPMPlDlRnFvth+ci39fZa1suX PE4hi0sa+Q6l6Uvdc+3+T8K1N1HMc5hDyFeBLM5W8l+Ud6PmoTPSbValYGB7bG24TfPQ U1oUZ2KdwOPVRzZnbgn7hglu7gKzxcAszQZfzBTr6iJReOit1xWQqZkZ2lXA1PY+cJ9E pMyXMlok592lFwJQM0BGah6Q4fsqmhF+LS4Zds/9Srx+tNo91MP6qbZr8S7NIcOO7n1P Dw+6Jj65TLwp2j190VEJKWJ9gv5dFpByu5rK+7Q9Ip3Vm7JuBDZ88vxLBDAbyHObrrPS /Itg== X-Gm-Message-State: APjAAAW2FgxXavJMBE1U4ZvXwQdKLMsaO88x5Aj/Q8ic9Afj8ws1R2tf sbQoT9GsmnHZwT+oMcQuFaaym3TcW0N2CN2KCVLc+yV8IpCNgDEh7PgjunAvP63iW7QEdNCDnOi D6HRpRlWDqQuW9sBL8OY= X-Received: by 2002:ab0:304e:: with SMTP id x14mr13966722ual.41.1571685561254; Mon, 21 Oct 2019 12:19:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqwdsR6P2HIKSC9DsS5X+JQXUdiIUcN0tXtJipAzVKmJuiDuu6O5aUXTIKcdDyi6TNJmSjsfi5pD8D7EAf4J0SE= X-Received: by 2002:ab0:304e:: with SMTP id x14mr13966694ual.41.1571685560831; Mon, 21 Oct 2019 12:19:20 -0700 (PDT) MIME-Version: 1.0 References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> <1571651279-51857-1-git-send-email-gavin.hu@arm.com> <1571651279-51857-3-git-send-email-gavin.hu@arm.com> In-Reply-To: <1571651279-51857-3-git-send-email-gavin.hu@arm.com> From: David Marchand Date: Mon, 21 Oct 2019 21:19:09 +0200 Message-ID: To: Gavin Hu Cc: dev , nd , "Ananyev, Konstantin" , Thomas Monjalon , Stephen Hemminger , Hemant Agrawal , Jerin Jacob Kollanukkaran , Pavan Nikhilesh , Honnappa Nagarahalli , "Ruifeng Wang (Arm Technology China)" , Phil Yang , Steve Capper X-MC-Unique: Aw8yUBe0O2Gj1b-VZmoZGg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v8 2/6] eal: add the APIs to wait until equal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Oct 21, 2019 at 11:48 AM Gavin Hu wrote: > > The rte_wait_until_equal_xx APIs abstract the functionality of > 'polling for a memory location to become equal to a given value'. > > Add the RTE_ARM_USE_WFE configuration entry for aarch64, disabled > by default. When it is enabled, the above APIs will call WFE instruction > to save CPU cycles and power. > > From a VM, when calling this API on aarch64, it may trap in and out to > release vCPUs whereas cause high exit latency. Since kernel 4.18.20 an > adaptive trapping mechanism is introduced to balance the latency and > workload. > > Signed-off-by: Gavin Hu > Reviewed-by: Ruifeng Wang > Reviewed-by: Steve Capper > Reviewed-by: Ola Liljedahl > Reviewed-by: Honnappa Nagarahalli > Reviewed-by: Phil Yang > Acked-by: Pavan Nikhilesh > Acked-by: Jerin Jacob > --- > config/arm/meson.build | 1 + > config/common_base | 5 ++ > .../common/include/arch/arm/rte_pause_64.h | 26 ++++++ > lib/librte_eal/common/include/generic/rte_pause.h | 93 ++++++++++++++++= ++++++ > 4 files changed, 125 insertions(+) > > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 979018e..b4b4cac 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -26,6 +26,7 @@ flags_common_default =3D [ > ['RTE_LIBRTE_AVP_PMD', false], > > ['RTE_SCHED_VECTOR', false], > + ['RTE_ARM_USE_WFE', false], > ] > > flags_generic =3D [ > diff --git a/config/common_base b/config/common_base > index e843a21..c812156 100644 > --- a/config/common_base > +++ b/config/common_base > @@ -111,6 +111,11 @@ CONFIG_RTE_MAX_VFIO_CONTAINERS=3D64 > CONFIG_RTE_MALLOC_DEBUG=3Dn > CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn > CONFIG_RTE_USE_LIBBSD=3Dn > +# Use WFE instructions to implement the rte_wait_for_equal_xxx APIs, > +# calling these APIs put the cores in low power state while waiting > +# for the memory address to become equal to the expected value. > +# This is supported only by aarch64. > +CONFIG_RTE_ARM_USE_WFE=3Dn > > # > # Recognize/ignore the AVX/AVX512 CPU flags for performance/power testin= g. > diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/= librte_eal/common/include/arch/arm/rte_pause_64.h > index 93895d3..eb8f73e 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > @@ -1,5 +1,6 @@ > /* SPDX-License-Identifier: BSD-3-Clause > * Copyright(c) 2017 Cavium, Inc > + * Copyright(c) 2019 Arm Limited > */ Before including generic/rte_pause.h, put a check like: #ifdef RTE_ARM_USE_WFE #define RTE_ARCH_HAS_WFE #endif #include "generic/rte_pause.h" > > #ifndef _RTE_PAUSE_ARM64_H_ > @@ -17,6 +18,31 @@ static inline void rte_pause(void) > asm volatile("yield" ::: "memory"); > } > > +#ifdef RTE_ARM_USE_WFE > +#define sev() { asm volatile("sev" : : : "memory") } > +#define wfe() { asm volatile("wfe" : : : "memory") } > + > +#define __WAIT_UNTIL_EQUAL(type, size, addr, expected, memorder) \ > +__rte_experimental \ The experimental tag is unnecessary here. We only need it in the function prototype (in the generic header). > +static __rte_always_inline void \ > +rte_wait_until_equal_##size(volatile type * addr, type expected,\ > +int memorder) \ > +{ \ > + if (__atomic_load_n(addr, memorder) !=3D expected) { \ > + sev(); \ > + do { \ > + wfe(); \ > + } while (__atomic_load_n(addr, memorder) !=3D expected); = \ > + } \ > +} > +__WAIT_UNTIL_EQUAL(uint16_t, 16, addr, expected, memorder) > +__WAIT_UNTIL_EQUAL(uint32_t, 32, addr, expected, memorder) > +__WAIT_UNTIL_EQUAL(uint64_t, 64, addr, expected, memorder) > + > +#undef __WAIT_UNTIL_EQUAL Missing #undef on sev and wfe macros. > + > +#endif /* RTE_ARM_USE_WFE */ > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/common/include/generic/rte_pause.h b/lib/libr= te_eal/common/include/generic/rte_pause.h > index 52bd4db..80597a9 100644 > --- a/lib/librte_eal/common/include/generic/rte_pause.h > +++ b/lib/librte_eal/common/include/generic/rte_pause.h > @@ -1,5 +1,6 @@ > /* SPDX-License-Identifier: BSD-3-Clause > * Copyright(c) 2017 Cavium, Inc > + * Copyright(c) 2019 Arm Limited > */ > > #ifndef _RTE_PAUSE_H_ > @@ -12,6 +13,11 @@ > * > */ > > +#include > +#include > +#include > +#include > + > /** > * Pause CPU execution for a short while > * > @@ -20,4 +26,91 @@ > */ > static inline void rte_pause(void); > > +/** > + * @warning > + * @b EXPERIMENTAL: this API may change, or be removed, without prior no= tice > + * > + * Wait for *addr to be updated with a 16-bit expected value, with a rel= axed > + * memory ordering model meaning the loads around this API can be reorde= red. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 16-bit expected value to be in the memory location. > + * @param memorder > + * Two different memory orders that can be specified: > + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to > + * C++11 memory orders with the same names, see the C++11 standard or > + * the GCC wiki on atomic synchronization for detailed definition. > + */ > +__rte_experimental > +static __rte_always_inline void > +rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, > +int memorder); > + > +/** > + * @warning > + * @b EXPERIMENTAL: this API may change, or be removed, without prior no= tice > + * > + * Wait for *addr to be updated with a 32-bit expected value, with a rel= axed > + * memory ordering model meaning the loads around this API can be reorde= red. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 32-bit expected value to be in the memory location. > + * @param memorder > + * Two different memory orders that can be specified: > + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to > + * C++11 memory orders with the same names, see the C++11 standard or > + * the GCC wiki on atomic synchronization for detailed definition. > + */ > +__rte_experimental > +static __rte_always_inline void > +rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, > +int memorder); > + > +/** > + * @warning > + * @b EXPERIMENTAL: this API may change, or be removed, without prior no= tice > + * > + * Wait for *addr to be updated with a 64-bit expected value, with a rel= axed > + * memory ordering model meaning the loads around this API can be reorde= red. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 64-bit expected value to be in the memory location. > + * @param memorder > + * Two different memory orders that can be specified: > + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to > + * C++11 memory orders with the same names, see the C++11 standard or > + * the GCC wiki on atomic synchronization for detailed definition. > + */ > +__rte_experimental > +static __rte_always_inline void > +rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, > +int memorder); > + Here, change this check to: #ifndef RTE_ARCH_HAS_WFE > +#ifndef RTE_ARM_USE_WFE > +#define __WAIT_UNTIL_EQUAL(type, size, addr, expected, memorder) \ > +__rte_experimental \ > +static __rte_always_inline void \ > +rte_wait_until_equal_##size(volatile type * addr, type expected,\ > +int memorder) \ > +{ \ > + if (__atomic_load_n(addr, memorder) !=3D expected) { \ > + do { \ > + rte_pause(); \ > + } while (__atomic_load_n(addr, memorder) !=3D expected); = \ > + } \ > +} > +__WAIT_UNTIL_EQUAL(uint16_t, 16, addr, expected, memorder) > +__WAIT_UNTIL_EQUAL(uint32_t, 32, addr, expected, memorder) > +__WAIT_UNTIL_EQUAL(uint64_t, 64, addr, expected, memorder) > + > +#undef __WAIT_UNTIL_EQUAL > + > +#endif /* RTE_ARM_USE_WFE */ > + > #endif /* _RTE_PAUSE_H_ */ > -- > 2.7.4 > Thanks. -- David Marchand