* [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
@ 2020-03-09 9:13 Linhaifeng
2020-03-09 9:19 ` David Marchand
2020-03-09 15:43 ` [dpdk-dev] " Jerin Jacob
0 siblings, 2 replies; 12+ messages in thread
From: Linhaifeng @ 2020-03-09 9:13 UTC (permalink / raw)
To: dev; +Cc: thomas, Lilijun (Jerry), chenchanghu, xudingke
We nead isb rather than dsb to sync system counter to cntvct_el0.
Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
---
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 859ae129d..705351394 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -21,6 +21,7 @@ extern "C" {
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+#define isb() asm volatile("isb" : : : "memory")
#define rte_mb() dsb(sy)
@@ -186,6 +187,8 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp,
return (old.int128 == expected.int128);
}
+#define rte_isb() isb()
+
#ifdef __cplusplus
}
#endif
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
index 68e7c7338..29f524901 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
@@ -18,6 +18,7 @@ extern "C" {
* The time base for this lcore.
*/
#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
+
/**
* This call is portable to any ARMv8 architecture, however, typically
* cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
@@ -27,6 +28,7 @@ rte_rdtsc(void)
{
uint64_t tsc;
+ rte_isb();
asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
return tsc;
}
--
2.24.1.windows.2
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
2020-03-09 9:13 [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 Linhaifeng
@ 2020-03-09 9:19 ` David Marchand
2020-03-10 2:51 ` [dpdk-dev] 答复: " Linhaifeng
2020-03-09 15:43 ` [dpdk-dev] " Jerin Jacob
1 sibling, 1 reply; 12+ messages in thread
From: David Marchand @ 2020-03-09 9:19 UTC (permalink / raw)
To: Linhaifeng; +Cc: dev, thomas, Lilijun (Jerry), chenchanghu, xudingke
On Mon, Mar 9, 2020 at 10:14 AM Linhaifeng <haifeng.lin@huawei.com> wrote:
>
> We nead isb rather than dsb to sync system counter to cntvct_el0.
I'll leave the arm maintainers look at this, but I have a comment on the form.
>
> Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
> ---
> lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
> lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index 859ae129d..705351394 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -21,6 +21,7 @@ extern "C" {
>
> #define dsb(opt) asm volatile("dsb " #opt : : : "memory")
> #define dmb(opt) asm volatile("dmb " #opt : : : "memory")
> +#define isb() asm volatile("isb" : : : "memory")
dsb and dmb should not be exported as public macros in the first place
(I forgot to send the patch that drops those, will send later).
Please don't add more public macro that make no sense except for
aarch64: neither isb, nor rte_isb.
>
> #define rte_mb() dsb(sy)
>
> @@ -186,6 +187,8 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp,
> return (old.int128 == expected.int128);
> }
>
> +#define rte_isb() isb()
> +
> #ifdef __cplusplus
> }
> #endif
--
David Marchand
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
2020-03-09 9:13 [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 Linhaifeng
2020-03-09 9:19 ` David Marchand
@ 2020-03-09 15:43 ` Jerin Jacob
2020-03-10 2:39 ` [dpdk-dev] 答复: " Linhaifeng
1 sibling, 1 reply; 12+ messages in thread
From: Jerin Jacob @ 2020-03-09 15:43 UTC (permalink / raw)
To: Linhaifeng; +Cc: dev, thomas, Lilijun (Jerry), chenchanghu, xudingke
On Mon, Mar 9, 2020 at 2:43 PM Linhaifeng <haifeng.lin@huawei.com> wrote:
>
> We nead isb rather than dsb to sync system counter to cntvct_el0.
# Currently rte_rdtsc() does not have dsb. Right? or any barriers.
# Why do you need it? If it regarding, getting accurate value then use
rte_rdtsc_precise().
>
> Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [dpdk-dev] 答复: [PATCH] cycles: add isb before read cntvct_el0
2020-03-09 15:43 ` [dpdk-dev] " Jerin Jacob
@ 2020-03-10 2:39 ` Linhaifeng
2020-03-10 7:53 ` [dpdk-dev] " Jerin Jacob
0 siblings, 1 reply; 12+ messages in thread
From: Linhaifeng @ 2020-03-10 2:39 UTC (permalink / raw)
To: Jerin Jacob; +Cc: dev, thomas, Lilijun (Jerry), chenchanghu, xudingke
-----邮件原件-----
发件人: Jerin Jacob [mailto:jerinjacobk@gmail.com]
发送时间: 2020年3月9日 23:43
收件人: Linhaifeng <haifeng.lin@huawei.com>
抄送: dev@dpdk.org; thomas@monjalon.net; Lilijun (Jerry) <jerry.lilijun@huawei.com>; chenchanghu <chenchanghu@huawei.com>; xudingke <xudingke@huawei.com>
主题: Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
On Mon, Mar 9, 2020 at 2:43 PM Linhaifeng <haifeng.lin@huawei.com> wrote:
>
> We nead isb rather than dsb to sync system counter to cntvct_el0.
# Currently rte_rdtsc() does not have dsb. Right? or any barriers.
# Why do you need it? If it regarding, getting accurate value then use rte_rdtsc_precise().
We use rte_get_tsc_cycles get start_value in pmd1 and end_value in pmd2 in our qos module, it works ok in x86 but not ok in arm64.
Then we use rte_mb() to sync instruction but it not work.Because rte_mb is dsb I think it only have affect on memory. cntvct_el0 and system counter is register so I think we should use isb.
It works well after we use isb in multi core scenes.
Use rte_rdtsc_precise is good idea. Maybe use isb replace of rte_mb(dsb) ?
>
> Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [dpdk-dev] 答复: [PATCH] cycles: add isb before read cntvct_el0
2020-03-09 9:19 ` David Marchand
@ 2020-03-10 2:51 ` Linhaifeng
0 siblings, 0 replies; 12+ messages in thread
From: Linhaifeng @ 2020-03-10 2:51 UTC (permalink / raw)
To: David Marchand; +Cc: dev, thomas, Lilijun (Jerry), chenchanghu, xudingke
-----邮件原件-----
发件人: David Marchand [mailto:david.marchand@redhat.com]
发送时间: 2020年3月9日 17:19
收件人: Linhaifeng <haifeng.lin@huawei.com>
抄送: dev@dpdk.org; thomas@monjalon.net; Lilijun (Jerry) <jerry.lilijun@huawei.com>; chenchanghu <chenchanghu@huawei.com>; xudingke <xudingke@huawei.com>
主题: Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
On Mon, Mar 9, 2020 at 10:14 AM Linhaifeng <haifeng.lin@huawei.com> wrote:
>
> We nead isb rather than dsb to sync system counter to cntvct_el0.
I'll leave the arm maintainers look at this, but I have a comment on the form.
Thank you
>
> Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
> ---
> lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
> lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index 859ae129d..705351394 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -21,6 +21,7 @@ extern "C" {
>
> #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define
> dmb(opt) asm volatile("dmb " #opt : : : "memory")
> +#define isb() asm volatile("isb" : : : "memory")
dsb and dmb should not be exported as public macros in the first place (I forgot to send the patch that drops those, will send later).
Please don't add more public macro that make no sense except for
aarch64: neither isb, nor rte_isb.
Ok.I will send a new patch after yours.
>
> #define rte_mb() dsb(sy)
>
> @@ -186,6 +187,8 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp,
> return (old.int128 == expected.int128); }
>
> +#define rte_isb() isb()
> +
> #ifdef __cplusplus
> }
> #endif
--
David Marchand
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
2020-03-10 2:39 ` [dpdk-dev] 答复: " Linhaifeng
@ 2020-03-10 7:53 ` Jerin Jacob
0 siblings, 0 replies; 12+ messages in thread
From: Jerin Jacob @ 2020-03-10 7:53 UTC (permalink / raw)
To: Linhaifeng; +Cc: dev, thomas, Lilijun (Jerry), chenchanghu, xudingke
On Tue, Mar 10, 2020 at 8:09 AM Linhaifeng <haifeng.lin@huawei.com> wrote:
>
>
>
> -----邮件原件-----
> 发件人: Jerin Jacob [mailto:jerinjacobk@gmail.com]
> 发送时间: 2020年3月9日 23:43
> 收件人: Linhaifeng <haifeng.lin@huawei.com>
> 抄送: dev@dpdk.org; thomas@monjalon.net; Lilijun (Jerry) <jerry.lilijun@huawei.com>; chenchanghu <chenchanghu@huawei.com>; xudingke <xudingke@huawei.com>
> 主题: Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
>
> On Mon, Mar 9, 2020 at 2:43 PM Linhaifeng <haifeng.lin@huawei.com> wrote:
> >
> > We nead isb rather than dsb to sync system counter to cntvct_el0.
>
> # Currently rte_rdtsc() does not have dsb. Right? or any barriers.
> # Why do you need it? If it regarding, getting accurate value then use rte_rdtsc_precise().
>
> We use rte_get_tsc_cycles get start_value in pmd1 and end_value in pmd2 in our qos module, it works ok in x86 but not ok in arm64.
>
> Then we use rte_mb() to sync instruction but it not work.Because rte_mb is dsb I think it only have affect on memory. cntvct_el0 and system counter is register so I think we should use isb.
>
> It works well after we use isb in multi core scenes.
>
> Use rte_rdtsc_precise is good idea. Maybe use isb replace of rte_mb(dsb) ?
Yes. Please.
>
> >
> > Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
2020-03-10 7:22 ` Linhaifeng
@ 2020-03-10 7:50 ` Jerin Jacob
0 siblings, 0 replies; 12+ messages in thread
From: Jerin Jacob @ 2020-03-10 7:50 UTC (permalink / raw)
To: Linhaifeng
Cc: Gavin Hu, dev, thomas, chenchanghu, xudingke, Lilijun (Jerry),
Honnappa Nagarahalli, Steve Capper, nd
On Tue, Mar 10, 2020 at 12:52 PM Linhaifeng <haifeng.lin@huawei.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Gavin Hu [mailto:Gavin.Hu@arm.com]
> > Sent: Tuesday, March 10, 2020 3:11 PM
> > To: Linhaifeng <haifeng.lin@huawei.com>; dev@dpdk.org;
> > thomas@monjalon.net
> > Cc: chenchanghu <chenchanghu@huawei.com>; xudingke
> > <xudingke@huawei.com>; Lilijun (Jerry) <jerry.lilijun@huawei.com>; Honnappa
> > Nagarahalli <Honnappa.Nagarahalli@arm.com>; Steve Capper
> > <Steve.Capper@arm.com>; nd <nd@arm.com>
> > Subject: RE: [PATCH] cycles: add isb before read cntvct_el0
> >
> > Hi Haifeng,
> >
> > > -----Original Message-----
> > > From: dev <dev-bounces@dpdk.org> On Behalf Of Linhaifeng
> > > Sent: Monday, March 9, 2020 5:23 PM
> > > To: dev@dpdk.org; thomas@monjalon.net
> > > Cc: chenchanghu <chenchanghu@huawei.com>; xudingke
> > > <xudingke@huawei.com>; Lilijun (Jerry) <jerry.lilijun@huawei.com>
> > > Subject: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
> > >
> > > We should use isb rather than dsb to sync system counter to cntvct_el0.
> > >
> > > Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
> > > ---
> > > lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
> > > lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
> > > 2 files changed, 5 insertions(+)
> > >
> > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > index 859ae129d..7e8049725 100644
> > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > @@ -21,6 +21,7 @@ extern "C" {
> > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define
> > > dmb(opt) asm volatile("dmb " #opt : : : "memory")
> > > +#define isb() asm volatile("isb" : : : "memory")
> > > #define rte_mb() dsb(sy)
> > > @@ -44,6 +45,8 @@ extern "C" {
> > > #define rte_cio_rmb() dmb(oshld)
> > > +#define rte_isb() isb()
> > > +
> > > /*------------------------ 128 bit atomic operations
> > > -------------------------*/ #if defined(__ARM_FEATURE_ATOMICS) ||
> > > defined(RTE_ARM_FEATURE_ATOMICS)
> > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> > > b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> > > index 68e7c7338..29f524901 100644
> > > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> > > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> > > @@ -18,6 +18,7 @@ extern "C" {
> > > * The time base for this lcore.
> > > */
> > > #ifndef RTE_ARM_EAL_RDTSC_USE_PMU
> > > +
> > > /**
> > > * This call is portable to any ARMv8 architecture, however, typically
> > > * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
> > > @@ -27,6 +28,7 @@ rte_rdtsc(void)
> > > {
> > > uint64_t tsc;
> > > + rte_isb();
> > Good catch, could you add a link to the commit log as a reference.
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/ar
> > m64/include/asm/arch_timer.h?h=v5.5#n220
> >
>
> Ok.
>
> > > asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
> > In kernel, there is a call to arch_counter_enforce_ordering(cnt), maybe it is
> > also necessary.
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/ar
> > m64/include/asm/arch_timer.h?h=v5.5#n168
>
> Should we add isb and arch_counter_enforce_ordering in rte_rdtsc or rte_rdtsc_precise?
Only for rte_rdtsc_precise() as some cases would not need a barrier.
rte_rdtsc_precise() created for this specific purpose.
>
> > > return tsc;
> > > }
> > > --
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
2020-03-10 7:11 ` Gavin Hu
@ 2020-03-10 7:22 ` Linhaifeng
2020-03-10 7:50 ` Jerin Jacob
0 siblings, 1 reply; 12+ messages in thread
From: Linhaifeng @ 2020-03-10 7:22 UTC (permalink / raw)
To: Gavin Hu, dev, thomas
Cc: chenchanghu, xudingke, Lilijun (Jerry),
Honnappa Nagarahalli, Steve Capper, nd
> -----Original Message-----
> From: Gavin Hu [mailto:Gavin.Hu@arm.com]
> Sent: Tuesday, March 10, 2020 3:11 PM
> To: Linhaifeng <haifeng.lin@huawei.com>; dev@dpdk.org;
> thomas@monjalon.net
> Cc: chenchanghu <chenchanghu@huawei.com>; xudingke
> <xudingke@huawei.com>; Lilijun (Jerry) <jerry.lilijun@huawei.com>; Honnappa
> Nagarahalli <Honnappa.Nagarahalli@arm.com>; Steve Capper
> <Steve.Capper@arm.com>; nd <nd@arm.com>
> Subject: RE: [PATCH] cycles: add isb before read cntvct_el0
>
> Hi Haifeng,
>
> > -----Original Message-----
> > From: dev <dev-bounces@dpdk.org> On Behalf Of Linhaifeng
> > Sent: Monday, March 9, 2020 5:23 PM
> > To: dev@dpdk.org; thomas@monjalon.net
> > Cc: chenchanghu <chenchanghu@huawei.com>; xudingke
> > <xudingke@huawei.com>; Lilijun (Jerry) <jerry.lilijun@huawei.com>
> > Subject: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
> >
> > We should use isb rather than dsb to sync system counter to cntvct_el0.
> >
> > Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
> > ---
> > lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
> > lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > index 859ae129d..7e8049725 100644
> > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > @@ -21,6 +21,7 @@ extern "C" {
> > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define
> > dmb(opt) asm volatile("dmb " #opt : : : "memory")
> > +#define isb() asm volatile("isb" : : : "memory")
> > #define rte_mb() dsb(sy)
> > @@ -44,6 +45,8 @@ extern "C" {
> > #define rte_cio_rmb() dmb(oshld)
> > +#define rte_isb() isb()
> > +
> > /*------------------------ 128 bit atomic operations
> > -------------------------*/ #if defined(__ARM_FEATURE_ATOMICS) ||
> > defined(RTE_ARM_FEATURE_ATOMICS)
> > diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> > b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> > index 68e7c7338..29f524901 100644
> > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> > @@ -18,6 +18,7 @@ extern "C" {
> > * The time base for this lcore.
> > */
> > #ifndef RTE_ARM_EAL_RDTSC_USE_PMU
> > +
> > /**
> > * This call is portable to any ARMv8 architecture, however, typically
> > * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
> > @@ -27,6 +28,7 @@ rte_rdtsc(void)
> > {
> > uint64_t tsc;
> > + rte_isb();
> Good catch, could you add a link to the commit log as a reference.
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/ar
> m64/include/asm/arch_timer.h?h=v5.5#n220
>
Ok.
> > asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
> In kernel, there is a call to arch_counter_enforce_ordering(cnt), maybe it is
> also necessary.
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/ar
> m64/include/asm/arch_timer.h?h=v5.5#n168
Should we add isb and arch_counter_enforce_ordering in rte_rdtsc or rte_rdtsc_precise?
> > return tsc;
> > }
> > --
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
2020-03-09 9:22 Linhaifeng
@ 2020-03-10 7:11 ` Gavin Hu
2020-03-10 7:22 ` Linhaifeng
0 siblings, 1 reply; 12+ messages in thread
From: Gavin Hu @ 2020-03-10 7:11 UTC (permalink / raw)
To: Linhaifeng, dev, thomas
Cc: chenchanghu, xudingke, Lilijun (Jerry),
Honnappa Nagarahalli, Steve Capper, nd
Hi Haifeng,
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Linhaifeng
> Sent: Monday, March 9, 2020 5:23 PM
> To: dev@dpdk.org; thomas@monjalon.net
> Cc: chenchanghu <chenchanghu@huawei.com>; xudingke
> <xudingke@huawei.com>; Lilijun (Jerry) <jerry.lilijun@huawei.com>
> Subject: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
>
> We should use isb rather than dsb to sync system counter to cntvct_el0.
>
> Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
> ---
> lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
> lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index 859ae129d..7e8049725 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -21,6 +21,7 @@ extern "C" {
> #define dsb(opt) asm volatile("dsb " #opt : : : "memory")
> #define dmb(opt) asm volatile("dmb " #opt : : : "memory")
> +#define isb() asm volatile("isb" : : : "memory")
> #define rte_mb() dsb(sy)
> @@ -44,6 +45,8 @@ extern "C" {
> #define rte_cio_rmb() dmb(oshld)
> +#define rte_isb() isb()
> +
> /*------------------------ 128 bit atomic operations -------------------------*/
> #if defined(__ARM_FEATURE_ATOMICS) ||
> defined(RTE_ARM_FEATURE_ATOMICS)
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> index 68e7c7338..29f524901 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> @@ -18,6 +18,7 @@ extern "C" {
> * The time base for this lcore.
> */
> #ifndef RTE_ARM_EAL_RDTSC_USE_PMU
> +
> /**
> * This call is portable to any ARMv8 architecture, however, typically
> * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
> @@ -27,6 +28,7 @@ rte_rdtsc(void)
> {
> uint64_t tsc;
> + rte_isb();
Good catch, could you add a link to the commit log as a reference.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/asm/arch_timer.h?h=v5.5#n220
> asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
In kernel, there is a call to arch_counter_enforce_ordering(cnt), maybe it is also necessary.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/asm/arch_timer.h?h=v5.5#n168
> return tsc;
> }
> --
^ permalink raw reply [flat|nested] 12+ messages in thread
* [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
@ 2020-03-09 11:05 Linhaifeng
0 siblings, 0 replies; 12+ messages in thread
From: Linhaifeng @ 2020-03-09 11:05 UTC (permalink / raw)
To: dev
We should use isb rather than dsb to sync system counter to cntvct_el0.
Signed-off-by: Linhaifeng <haifeng.lin@huawei.com>
---
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 859ae129d..2587f98a2 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -21,6 +21,7 @@ extern "C" {
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+#define isb() (asm volatile("isb" : : : "memory"))
#define rte_mb() dsb(sy)
@@ -44,6 +45,8 @@ extern "C" {
#define rte_cio_rmb() dmb(oshld)
+#define rte_isb() isb()
+
/*------------------------ 128 bit atomic operations -------------------------*/
#if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
index 68e7c7338..29f524901 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
@@ -18,6 +18,7 @@ extern "C" {
* The time base for this lcore.
*/
#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
+
/**
* This call is portable to any ARMv8 architecture, however, typically
* cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
@@ -27,6 +28,7 @@ rte_rdtsc(void)
{
uint64_t tsc;
+ rte_isb();
asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
return tsc;
}
--
2.24.1.windows.2
^ permalink raw reply [flat|nested] 12+ messages in thread
* [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
@ 2020-03-09 10:58 Linhaifeng
0 siblings, 0 replies; 12+ messages in thread
From: Linhaifeng @ 2020-03-09 10:58 UTC (permalink / raw)
To: dev
We should use isb rather than dsb to sync system counter to cntvct_el0.
Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
---
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 859ae129d..2587f98a2 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -21,6 +21,7 @@ extern "C" {
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+#define isb() (asm volatile("isb" : : : "memory"))
#define rte_mb() dsb(sy)
@@ -44,6 +45,8 @@ extern "C" {
#define rte_cio_rmb() dmb(oshld)
+#define rte_isb() isb()
+
/*------------------------ 128 bit atomic operations -------------------------*/
#if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
index 68e7c7338..29f524901 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
@@ -18,6 +18,7 @@ extern "C" {
* The time base for this lcore.
*/
#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
+
/**
* This call is portable to any ARMv8 architecture, however, typically
* cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
@@ -27,6 +28,7 @@ rte_rdtsc(void)
{
uint64_t tsc;
+ rte_isb();
asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
return tsc;
}
--
2.24.1.windows.2
^ permalink raw reply [flat|nested] 12+ messages in thread
* [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
@ 2020-03-09 9:22 Linhaifeng
2020-03-10 7:11 ` Gavin Hu
0 siblings, 1 reply; 12+ messages in thread
From: Linhaifeng @ 2020-03-09 9:22 UTC (permalink / raw)
To: dev, thomas; +Cc: chenchanghu, xudingke, Lilijun (Jerry)
We should use isb rather than dsb to sync system counter to cntvct_el0.
Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
---
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 859ae129d..7e8049725 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -21,6 +21,7 @@ extern "C" {
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+#define isb() asm volatile("isb" : : : "memory")
#define rte_mb() dsb(sy)
@@ -44,6 +45,8 @@ extern "C" {
#define rte_cio_rmb() dmb(oshld)
+#define rte_isb() isb()
+
/*------------------------ 128 bit atomic operations -------------------------*/
#if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
index 68e7c7338..29f524901 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
@@ -18,6 +18,7 @@ extern "C" {
* The time base for this lcore.
*/
#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
+
/**
* This call is portable to any ARMv8 architecture, however, typically
* cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
@@ -27,6 +28,7 @@ rte_rdtsc(void)
{
uint64_t tsc;
+ rte_isb();
asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
return tsc;
}
--
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-03-10 7:53 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-09 9:13 [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 Linhaifeng
2020-03-09 9:19 ` David Marchand
2020-03-10 2:51 ` [dpdk-dev] 答复: " Linhaifeng
2020-03-09 15:43 ` [dpdk-dev] " Jerin Jacob
2020-03-10 2:39 ` [dpdk-dev] 答复: " Linhaifeng
2020-03-10 7:53 ` [dpdk-dev] " Jerin Jacob
2020-03-09 9:22 Linhaifeng
2020-03-10 7:11 ` Gavin Hu
2020-03-10 7:22 ` Linhaifeng
2020-03-10 7:50 ` Jerin Jacob
2020-03-09 10:58 Linhaifeng
2020-03-09 11:05 Linhaifeng
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