From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A13AFA052E; Mon, 9 Mar 2020 10:19:22 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F05DD1C001; Mon, 9 Mar 2020 10:19:21 +0100 (CET) Received: from us-smtp-1.mimecast.com (us-smtp-delivery-1.mimecast.com [205.139.110.120]) by dpdk.org (Postfix) with ESMTP id 79C181BFFC for ; Mon, 9 Mar 2020 10:19:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1583745559; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7PWIzA4NaKGGitAVkooyVFildiNWYxOgB6YXhgYvC0s=; b=DFLP4wJzylsTYLILKuNOsI5S9uY10bEzAeB5jKIwfvSpnW1bKpDGvvipW4g+c/g1ei6mO3 z+lprsRwYqaVWNV1nNSPhAh4hIrcDCOtd+r6q9bFNu8pQ9ofbhsjxb2mhpPgSl3Eosg598 elfW92z830L9RXHb9P4X0bxewJUM7ls= Received: from mail-ua1-f71.google.com (mail-ua1-f71.google.com [209.85.222.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-22-_9gNDj4_O1yrRuD8W3AxtQ-1; Mon, 09 Mar 2020 05:19:18 -0400 X-MC-Unique: _9gNDj4_O1yrRuD8W3AxtQ-1 Received: by mail-ua1-f71.google.com with SMTP id 30so1329843uaz.4 for ; Mon, 09 Mar 2020 02:19:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=m9NMDgbyyNUSB22YheIMon+umVDH5l17z+yV2XS0jZw=; b=szWc6hH90mxaqncZZfYtKelPrW08Od9xsSzid3RXBh+YezLvvx/mtQgK+8sxI5336g X9hahcmIxg3xKBMyKxBatSz9ZTqmcfc0EHFPjHQYgt3IxYUffTpmBNgIeKIYRxE0S1RC z/P8KMN1qUGn4DiY5wkmFGtXLfShsJWknEu3njsEz/EjpcQ/T0WJGPrPtmIiV18aHBux 5MCJDhtJV+Q//VxnyqnZwOSIvpgWP9pmW7TNuMjQrImOjLEuBZTaBy+lTuIvCDk+8a/+ VcFqgT0N9CtoLVOpQAgyMz5VVLU+HDHHY8UP84xO6WLozgGV3veRgXJRM88U/rZrEccD DPQQ== X-Gm-Message-State: ANhLgQ2RK/JYipedSBZPxfw7O42lcrq9vlZgCySv8AYFoz5jeJ63ZgXC nsbe8rg+EFqap7HSs2N2NyMc3kjjIBGNbvK4JLCbDgW27RlQfUZhcS15TtNEhWIZ7piuXYpHdFo s4fWSHXJddNZEWtU9yvg= X-Received: by 2002:a67:643:: with SMTP id 64mr9523884vsg.180.1583745557659; Mon, 09 Mar 2020 02:19:17 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtHYZ8PPpD9v/bwRAhsFyQt3XxQbogaSgzIUff7avGvCSYO0Qo479nfFDIAk4i3uvl5QFgeWFbxh4oJGxUpgpA= X-Received: by 2002:a67:643:: with SMTP id 64mr9523874vsg.180.1583745557389; Mon, 09 Mar 2020 02:19:17 -0700 (PDT) MIME-Version: 1.0 References: <4099DE2E54AFAD489356C6C9161D53339729EB7E@DGGEML502-MBX.china.huawei.com> In-Reply-To: <4099DE2E54AFAD489356C6C9161D53339729EB7E@DGGEML502-MBX.china.huawei.com> From: David Marchand Date: Mon, 9 Mar 2020 10:19:06 +0100 Message-ID: To: Linhaifeng Cc: "dev@dpdk.org" , "thomas@monjalon.net" , "Lilijun (Jerry)" , chenchanghu , xudingke X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Mar 9, 2020 at 10:14 AM Linhaifeng wrote: > > We nead isb rather than dsb to sync system counter to cntvct_el0. I'll leave the arm maintainers look at this, but I have a comment on the fo= rm. > > Signed-off-by: Haifeng Lin > --- > lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++ > lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib= /librte_eal/common/include/arch/arm/rte_atomic_64.h > index 859ae129d..705351394 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > @@ -21,6 +21,7 @@ extern "C" { > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") > #define dmb(opt) asm volatile("dmb " #opt : : : "memory") > +#define isb() asm volatile("isb" : : : "memory") dsb and dmb should not be exported as public macros in the first place (I forgot to send the patch that drops those, will send later). Please don't add more public macro that make no sense except for aarch64: neither isb, nor rte_isb. > > #define rte_mb() dsb(sy) > > @@ -186,6 +187,8 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int= 128_t *exp, > return (old.int128 =3D=3D expected.int128); > } > > +#define rte_isb() isb() > + > #ifdef __cplusplus > } > #endif --=20 David Marchand