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Fri, 08 Apr 2022 02:16:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxBgU344+wB2Qav3JcWGYvrcMePEbmOsgEc5cLelrGs3WQ+ilKOU2/baQLj92nv1P2AaHS7uPifSvAA+6bB5bw= X-Received: by 2002:a05:6512:c05:b0:46b:8246:9a0f with SMTP id z5-20020a0565120c0500b0046b82469a0fmr2306039lfu.560.1649409409192; Fri, 08 Apr 2022 02:16:49 -0700 (PDT) MIME-Version: 1.0 References: <20211004055255.12947-1-pbhagavatula@marvell.com> <20211105101054.3422-1-pbhagavatula@marvell.com> <20211105101054.3422-2-pbhagavatula@marvell.com> In-Reply-To: From: David Marchand Date: Fri, 8 Apr 2022 11:16:38 +0200 Message-ID: Subject: Re: [dpdk-dev] [PATCH v5 2/2] hash: unify crc32 selection for x86 and Arm To: "pbhagavatula@marvell.com" Cc: "jerinj@marvell.com" , Yipeng Wang , Sameh Gobriel , Bruce Richardson , Vladimir Medvedkin , "dev@dpdk.org" , nd , Ruifeng Wang Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dmarchan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Tue, Jan 4, 2022 at 10:12 AM Ruifeng Wang wrote: > > From: pbhagavatula@marvell.com [snip] > > -/** > > - * Use single crc32 instruction to perform a hash on a 2 bytes value. > > - * Fall back to software crc32 implementation in case SSE4.2 is > > - * not supported > > - * > > - * @param data > > - * Data to perform hash on. > > - * @param init_val > > - * Value to initialise hash generator. > > - * @return > > - * 32bit calculated hash value. > > - */ > > -static inline uint32_t > > -rte_hash_crc_2byte(uint16_t data, uint32_t init_val) -{ -#if defined > > RTE_ARCH_X86 > > - if (likely(crc32_alg & CRC32_SSE42)) > > - return crc32c_sse42_u16(data, init_val); > > +#if defined RTE_ARCH_ARM64 > > + RTE_LOG(WARNING, HASH, > > + "Incorrect CRC32 algorithm requested setting best > > available algorithm on the architecture\n"); > > + rte_hash_crc_set_alg(CRC32_ARM64); > > +#endif > > + break; > > + case CRC32_ARM64: > > +#if defined RTE_ARCH_ARM64 > > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32)) > > + crc32_alg = CRC32_ARM64; > > #endif > > + #if defined RTE_ARCH_X86 > > + RTE_LOG(WARNING, HASH, > > + "Incorrect CRC32 algorithm requested setting best > > available algorithm on the architecture\n"); > > + rte_hash_crc_set_alg(CRC32_SSE42_x64); > > #endif > > + break; > > I edited this part for readability. > The 'break' need to be inside #if, so algorithm can fallback to CRC32_SW when CRC32 feature is not available on hardware. I marked this series in patchwork as changes requested. Thanks. -- David Marchand