From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 99337A2EFC for ; Mon, 14 Oct 2019 17:45:18 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 61CEC1C123; Mon, 14 Oct 2019 17:45:18 +0200 (CEST) Received: from us-smtp-1.mimecast.com (us-smtp-delivery-1.mimecast.com [205.139.110.120]) by dpdk.org (Postfix) with ESMTP id 23A521C123 for ; Mon, 14 Oct 2019 17:45:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571067916; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yPWLzzT1Q0hkl86TjB5o3d2upb2R61g3NoAONAasRyw=; b=IJMz4F62Rq6wUXfGlxXkbyGvEOurcCH5r3DujQJ/7S5emFooOviR7NwtCtiFzQnEPtUron YTpgovtitasuaSb+c/dnCQ5cIEGOn+LBXu98IL3WRW5hDoleefC+FHia+dxI+mp6Vaiarz hxLLmKXi7oeiX+1iaBDratJChAii6qM= Received: from mail-io1-f71.google.com (mail-io1-f71.google.com [209.85.166.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-284-vUDihkDwOoayILh7KwoTIg-1; Mon, 14 Oct 2019 11:45:15 -0400 Received: by mail-io1-f71.google.com with SMTP id w16so26908237ioc.15 for ; Mon, 14 Oct 2019 08:45:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OZWP496Qc7vcbbBLa9U5JPMoh2fhOoEXS8fyT5M9HNE=; b=aBFM8goRImE5A3N5eAbeQymk4GNqTT2lzyrSj68PtylPykmyE8binoU9+cGl4v1KSj RUFjEFpNR2k2V5LJFiMyq0ITcl9RSowJFtrZCHULl3m/bsXjSSjLTa9mbTvQSE487Fof jYB1oYmmAdB9U04gaWjqFCpldE3ofL3cih5FFXwRHlIMBkB8pwhaKQxvG1VYwnQ2jomS Nx8m21yYBuzxV/k5D/jyLQqaotuR3beBajt6OHCO6pQhJSsvPPnEFHl9nGDEHhmPeNTn lKjrFL+Hy4O8jjz53tTNuZhO2xrIA7v98YMCyQfzj6QGFW5hhRj/jRG7WSGc4dpObX4E p+Zw== X-Gm-Message-State: APjAAAVoSwpjd4x7/yTF4yAc3F5e/tLk7wjgCAcUZyzYbr97aZ4u5NMW 77OURzcIU+14Mnk6VihMcg7pAjq1ZZb5+jT5qk52TOSoTZvVij4YfNs0sqV/0hQ8M19Coe6qWAV VRyc8q8ecfeN36IaJlpA= X-Received: by 2002:a92:88cf:: with SMTP id m76mr1151306ilh.40.1571067914563; Mon, 14 Oct 2019 08:45:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqxdI7ejFmXmuvi9kATQP3yQfVLOqBeQdXe5ENd1lYTDuWBDveghMR040NFJej3HPIGon+9PbJhVVoM9taLpLDs= X-Received: by 2002:a92:88cf:: with SMTP id m76mr1151280ilh.40.1571067914236; Mon, 14 Oct 2019 08:45:14 -0700 (PDT) MIME-Version: 1.0 References: <20190723070536.30342-1-jerinj@marvell.com> <1565771263-27353-1-git-send-email-phil.yang@arm.com> <1565771263-27353-2-git-send-email-phil.yang@arm.com> In-Reply-To: <1565771263-27353-2-git-send-email-phil.yang@arm.com> From: David Marchand Date: Mon, 14 Oct 2019 17:45:03 +0200 Message-ID: To: Phil Yang Cc: Thomas Monjalon , Jerin Jacob Kollanukkaran , Gage Eads , dev , Hemant Agrawal , Honnappa Nagarahalli , Gavin Hu , nd X-MC-Unique: vUDihkDwOoayILh7KwoTIg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v9 2/3] test/atomic: add 128b compare and swap test X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Aug 14, 2019 at 10:29 AM Phil Yang wrote: > > Add 128b atomic compare and swap test for aarch64 and x86_64. > > Signed-off-by: Phil Yang > Reviewed-by: Honnappa Nagarahalli > Acked-by: Gage Eads > Acked-by: Jerin Jacob > Tested-by: Jerin Jacob > --- > app/test/test_atomic.c | 125 +++++++++++++++++++++++++++++++++++++++++++= +++++- > 1 file changed, 123 insertions(+), 2 deletions(-) > > diff --git a/app/test/test_atomic.c b/app/test/test_atomic.c > index 43be30e..0dad923 100644 > --- a/app/test/test_atomic.c > +++ b/app/test/test_atomic.c > @@ -1,5 +1,6 @@ > /* SPDX-License-Identifier: BSD-3-Clause > * Copyright(c) 2010-2014 Intel Corporation > + * Copyright(c) 2019 Arm Limited > */ > > #include > @@ -20,7 +21,7 @@ > * Atomic Variables > * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > * > - * - The main test function performs three subtests. The first test > + * - The main test function performs four subtests. The first test > * checks that the usual inc/dec/add/sub functions are working > * correctly: > * > @@ -61,11 +62,27 @@ > * atomic_sub(&count, tmp+1); > * > * - At the end of the test, the *count* value must be 0. > + * > + * - Test "128b compare and swap" (aarch64 and x86_64 only) > + * > + * - Initialize 128-bit atomic variables to zero. > + * > + * - Invoke ``test_atomici128_cmp_exchange()`` on each lcore. Before d= oing Typo, atomic128. > + * anything else, the cores are waiting a synchro. Each lcore does > + * these compare and swap (CAS) operations several times:: > + * > + * Acquired CAS update counter.val[0] + 2; counter.val[1] + 1; > + * Released CAS update counter.val[0] + 2; counter.val[1] + 1; > + * Acquired_Released CAS update counter.val[0] + 2; counter.val[1]= + 1; > + * Relaxed CAS update counter.val[0] + 2; counter.val[1] + 1; > + * > + * - At the end of the test, the *count128* first 64-bit value and > + * second 64-bit value differ by the total iterations. > */ > > #define NUM_ATOMIC_TYPES 3 > > -#define N 10000 > +#define N 1000000 This change the number of iterations for this test. Did you evaluate the impact on the test duration? I suppose this is fairly quick, but could you explain why this has been extended? The commitlog does not give hints. > > static rte_atomic16_t a16; > static rte_atomic32_t a32; > @@ -216,6 +233,78 @@ test_atomic_dec_and_test(__attribute__((unused)) voi= d *arg) > return 0; > } > > +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) > +static rte_int128_t count128; > + > +/* > + * rte_atomic128_cmp_exchange() should update a 128 bits counter's first= 64 > + * bits by 2 and the second 64 bits by 1 in this test. It should return = true > + * if the compare exchange operation is successful. > + * This test repeats 128 bits compare and swap operations 10K rounds. In= each s/10K/N/ > + * iteration it runs compare and swap operation with different memory mo= dels. > + */ > +static int > +test_atomic128_cmp_exchange(__attribute__((unused)) void *arg) > +{ > + rte_int128_t expected; > + int success; > + unsigned int i; > + > + while (rte_atomic32_read(&synchro) =3D=3D 0) > + ; > + > + expected =3D count128; > + > + for (i =3D 0; i < N; i++) { > + do { > + rte_int128_t desired; > + > + desired.val[0] =3D expected.val[0] + 2; > + desired.val[1] =3D expected.val[1] + 1; > + > + success =3D rte_atomic128_cmp_exchange(&count128, > + &expected, &desired, 1, > + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); > + } while (success =3D=3D 0); > + > + do { > + rte_int128_t desired; > + > + desired.val[0] =3D expected.val[0] + 2; > + desired.val[1] =3D expected.val[1] + 1; > + > + success =3D rte_atomic128_cmp_exchange(&count128, > + &expected, &desired, 1, > + __ATOMIC_RELEASE, __ATOMIC_RELAXE= D); > + } while (success =3D=3D 0); > + > + do { > + rte_int128_t desired; > + > + desired.val[0] =3D expected.val[0] + 2; > + desired.val[1] =3D expected.val[1] + 1; > + > + success =3D rte_atomic128_cmp_exchange(&count128, > + &expected, &desired, 1, > + __ATOMIC_ACQ_REL, __ATOMIC_RELAXE= D); > + } while (success =3D=3D 0); > + > + do { > + rte_int128_t desired; > + > + desired.val[0] =3D expected.val[0] + 2; > + desired.val[1] =3D expected.val[1] + 1; > + > + success =3D rte_atomic128_cmp_exchange(&count128, > + &expected, &desired, 1, > + __ATOMIC_RELAXED, __ATOMIC_RELAXE= D); > + } while (success =3D=3D 0); > + } > + > + return 0; > +} > +#endif > + > static int > test_atomic(void) > { > @@ -340,6 +429,38 @@ test_atomic(void) > return -1; > } > > +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) > + /* > + * This case tests the functionality of rte_atomic128b_cmp_exchan= ge > + * API. It calls rte_atomic128b_cmp_exchange with four kinds of m= emory > + * models successively on each slave core. Once each 128-bit atom= ic > + * compare and swap operation is successful, it updates the globa= l > + * 128-bit counter by 2 for the first 64-bit and 1 for the second > + * 64-bit. Each slave core iterates this test 10K times. N times. > + * At the end of test, verify whether the first 64-bits of the 12= 8-bit > + * counter and the second 64bits is differ by the total iteration= s. If > + * it is, the test passes. > + */ > + printf("128b compare and swap test\n"); > + uint64_t iterations =3D 0; > + > + rte_atomic32_clear(&synchro); > + count128.val[0] =3D 0; > + count128.val[1] =3D 0; > + > + rte_eal_mp_remote_launch(test_atomic128_cmp_exchange, NULL, > + SKIP_MASTER); > + rte_atomic32_set(&synchro, 1); > + rte_eal_mp_wait_lcore(); > + rte_atomic32_clear(&synchro); > + > + iterations =3D count128.val[0] - count128.val[1]; > + if (iterations !=3D 4*N*(rte_lcore_count()-1)) { > + printf("128b compare and swap failed\n"); > + return -1; > + } > +#endif > + > return 0; > } > > -- > 2.7.4 > -- David Marchand