From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42FC1A0A0A; Thu, 3 Jun 2021 09:18:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C6D7E40689; Thu, 3 Jun 2021 09:18:51 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mails.dpdk.org (Postfix) with ESMTP id 147044067A for ; Thu, 3 Jun 2021 09:18:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1622704729; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=WyJLek0FYBW1ZIEHgXjN+FSLi6Sj0nfUKbuBOGkGU/M=; b=BIlEWnt7lF4ZpyZUJZ2e+VrY1oPoTPJ3OBtjSDy71nT8k/OspeAtC0rVeTt/u884k0qfQE 6WR3PI2mKtxgkU2AWDBwJmXOs3kafd0i5TiSIHR9euQtCiT9MPkXPDbGT/0Cn0h0Myqner msx8NmHRNMwmCC68lgAXxB2NIEM+7DQ= Received: from mail-lf1-f71.google.com (mail-lf1-f71.google.com [209.85.167.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-399-1SYxgkZdOaKSoblXXnUOGA-1; Thu, 03 Jun 2021 03:18:47 -0400 X-MC-Unique: 1SYxgkZdOaKSoblXXnUOGA-1 Received: by mail-lf1-f71.google.com with SMTP id v10-20020a056512348ab02902beeb2f6412so1985423lfr.17 for ; Thu, 03 Jun 2021 00:18:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WyJLek0FYBW1ZIEHgXjN+FSLi6Sj0nfUKbuBOGkGU/M=; b=JR/UjbohMC67Yv9sZeP7S451uk7n5k35aOyxqToSlClTc790zfVWUnaCclmfwYrvPz Om88cGqRmIQSfqr3/nDbUFpraimTz6+LmGFPUagWewb9kFAar9zqqd9WqzPntFXG/oYn mzLSjBzJoykYlg4QmlacCu/XHoT2dpI1XO5GpQDcW4mIMFAOwqOPji53kNatA5PwJHHg lTRYwtRNpO/KO/WVXdB3qjm6Ksl1Av/1lgIsZ21UlrkqeD7B/vVj+iymMtb9jcORA2ie uVTTep6NF3URFRSvgdng2Z1Y2wWkj6EqKXIguGmb8zh3p5mF/YuvNkf8Y5gzjnUUVj7c rNZQ== X-Gm-Message-State: AOAM533WZh2JyKd0/YDLusa8QuIhHehi+pSPkCklYiK9qfh/ZKfJRtuT /3enNdopLIqbutwgQkfE8eYr/I1F/C6opvFjItgcR6AYZvPbu/VdzWD4fM0CnckcN/PFZQhzB4a /aystLrnviU1oMX9DItc= X-Received: by 2002:a19:7d82:: with SMTP id y124mr24605934lfc.76.1622704726256; Thu, 03 Jun 2021 00:18:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw1NMbEgrNmtepPeoMdLBcUwyRnuRxFKEzl942TfUREZWxZWnlntjPUyiYvRdXtcFniB9siVgwiTrER84HLFrk= X-Received: by 2002:a19:7d82:: with SMTP id y124mr24605925lfc.76.1622704726066; Thu, 03 Jun 2021 00:18:46 -0700 (PDT) MIME-Version: 1.0 References: <20210602203531.2288645-1-thomas@monjalon.net> In-Reply-To: <20210602203531.2288645-1-thomas@monjalon.net> From: David Marchand Date: Thu, 3 Jun 2021 09:18:33 +0200 Message-ID: To: Thomas Monjalon Cc: dev , Elena Agostini Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dmarchan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH] gpudev: introduce memory API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Quick pass: On Wed, Jun 2, 2021 at 10:36 PM Thomas Monjalon wrote: > diff --git a/lib/gpudev/gpu_driver.h b/lib/gpudev/gpu_driver.h > new file mode 100644 > index 0000000000..5ff609e49d > --- /dev/null > +++ b/lib/gpudev/gpu_driver.h > @@ -0,0 +1,44 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright 2021 NVIDIA Corporation & Affiliates > + */ > + > +#ifndef GPU_DRIVER_H > +#define GPU_DRIVER_H > + > +#include > + > +#include > + > +#include "rte_gpudev.h" > + > +struct rte_gpu_dev; > + > +typedef int (*gpu_malloc_t)(struct rte_gpu_dev *dev, size_t size, void **ptr); > +typedef int (*gpu_free_t)(struct rte_gpu_dev *dev, void *ptr); > + Great to see this structure hidden in a driver-only header. > +struct rte_gpu_dev { We could have a name[] field here, that will be later pointed at, in rte_gpu_info. Who is responsible for deciding of the device name? > + /* Backing device. */ > + struct rte_device *device; > + /* GPU info structure. */ > + struct rte_gpu_info info; > + /* Counter of processes using the device. */ > + uint16_t process_cnt; > + /* If device is currently used or not. */ > + enum rte_gpu_state state; > + /* FUNCTION: Allocate memory on the GPU. */ > + gpu_malloc_t gpu_malloc; > + /* FUNCTION: Allocate memory on the CPU visible from the GPU. */ > + gpu_malloc_t gpu_malloc_visible; > + /* FUNCTION: Free allocated memory on the GPU. */ > + gpu_free_t gpu_free; > + /* Device interrupt handle. */ > + struct rte_intr_handle *intr_handle; > + /* Driver-specific private data. */ > + void *dev_private; > +} __rte_cache_aligned; > + > +struct rte_gpu_dev *rte_gpu_dev_allocate(const char *name); > +struct rte_gpu_dev *rte_gpu_dev_get_by_name(const char *name); Those symbols will have to be marked internal (__rte_internal + version.map) for drivers to see them. > +int rte_gpu_dev_release(struct rte_gpu_dev *gpudev); > + > +#endif /* GPU_DRIVER_H */ > diff --git a/lib/gpudev/rte_gpudev.h b/lib/gpudev/rte_gpudev.h > new file mode 100644 > index 0000000000..b12f35c17e > --- /dev/null > +++ b/lib/gpudev/rte_gpudev.h > @@ -0,0 +1,183 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright 2021 NVIDIA Corporation & Affiliates > + */ > + > +#ifndef RTE_GPUDEV_H > +#define RTE_GPUDEV_H > + > +#include > +#include > + > +#include > + > +/** > + * @file > + * Generic library to interact with a GPU. > + * > + * @warning > + * @b EXPERIMENTAL: this API may change without prior notice. > + */ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/** Maximum number of GPU engines. */ > +#define RTE_GPU_MAX_DEVS UINT16_C(32) Bleh. Let's stop with max values. The iterator _next should return a special value indicating there is no more devs to list. > +/** Maximum length of device name. */ > +#define RTE_GPU_NAME_MAX_LEN 128 > + > +/** Flags indicate current state of GPU device. */ > +enum rte_gpu_state { > + RTE_GPU_STATE_UNUSED, /**< not initialized */ > + RTE_GPU_STATE_INITIALIZED, /**< initialized */ > +}; > + > +/** Store a list of info for a given GPU. */ > +struct rte_gpu_info { > + /** GPU device ID. */ > + uint16_t gpu_id; > + /** Unique identifier name. */ > + char name[RTE_GPU_NAME_MAX_LEN]; const char *name; Then the gpu generic layer simply fills this with the rte_gpu_dev->name field I proposed above. > + /** Total memory available on device. */ > + size_t total_memory; > + /** Total processors available on device. */ > + int processor_count; > +}; -- David Marchand