From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 218EFA31F3 for ; Fri, 18 Oct 2019 16:34:15 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B169F1C0B1; Fri, 18 Oct 2019 16:34:13 +0200 (CEST) Received: from us-smtp-delivery-1.mimecast.com (us-smtp-2.mimecast.com [207.211.31.81]) by dpdk.org (Postfix) with ESMTP id 3D2811BFF3 for ; Fri, 18 Oct 2019 16:34:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571409251; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=drnaB1oCvt9t3oZa/EodCT/s2mnhe/RHfHzZKKg5Ivk=; b=aC/YfpgUD4WkS90g3JFAowD2HBozi/Rq4pmCLIsvNh0zJn8QcukFmnmGTGtWn90FxM09VV o2EaTyM9dz3nSwALkWD4k0wlC90EhEcxij1CuKYeWb4+UMb+CSeLhhv/+krQFLOvFf5FDX YzsMiSWO/44aofNT3vrP1nHQg520ZbA= Received: from mail-ua1-f71.google.com (mail-ua1-f71.google.com [209.85.222.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-315-XHd7PgV2Ne2FotNmE-bosQ-1; Fri, 18 Oct 2019 10:34:09 -0400 Received: by mail-ua1-f71.google.com with SMTP id j13so773984uag.12 for ; Fri, 18 Oct 2019 07:34:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Pcvw1nw+8yYrKPGmWTsMGij3iw+I0xMRRSH+v7eqVK4=; b=Kts269Wy06wE4e8ADtuitz4XmyX2r+aQXO6vj5FTh7n1O2JQSZii6DNXVd9qqDvogT AkPZ22xuXIKVeG3qvcv+JMeuOlfYSdm153PWheFy0GcSYzBdWiDt+JYH2hUs9qeqjB9M Mf6KCInlHrZ87yrzw0yKFrejijWIry9VnhGMS0lWlXVi/i7HbSnWDCKam3u6D1vux8Ko YaM4dPtPAfAXzwPS4O0Ed+IGA5CKytsNKSQMaS3WNTSFtOTpYIFOwlChldt1eFy85yhg oQsSwbScbRRWbeoEq1giw4irYfoYVATvrHxNWIeVELtipScQA/xPvTrKgOYjWom1kIkY qKew== X-Gm-Message-State: APjAAAX1fOl0T5mY3J3cAk/lIPnW5atv9eE+D3dQV+zE7+rw33ZpA2rv iiaVrilzGYHEVqQBLc9HVAeMT9R4AzrELHZ4oRL+9iw3zbEj8BD9N7F0OTqGBVbOHkiziAR/GMq /FAPJtaUMK5MyS40OtS0= X-Received: by 2002:a1f:bd8c:: with SMTP id n134mr5515135vkf.39.1571409248304; Fri, 18 Oct 2019 07:34:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxInWnvI91rPWtxSgdPdY9+19Pi2mtFvjDvJmp4Js7p+XzfTYPRPxIv/d13e0/PB6A6ioJ1hu0WOibWBY/3Lv4= X-Received: by 2002:a1f:bd8c:: with SMTP id n134mr5515099vkf.39.1571409247840; Fri, 18 Oct 2019 07:34:07 -0700 (PDT) MIME-Version: 1.0 References: <1571139508-21701-1-git-send-email-phil.yang@arm.com> <1571397690-14116-1-git-send-email-phil.yang@arm.com> In-Reply-To: From: David Marchand Date: Fri, 18 Oct 2019 16:33:56 +0200 Message-ID: To: Jerin Jacob Cc: Jerin Jacob Kollanukkaran , Phil Yang , Gage Eads , dev , Thomas Monjalon , Hemant Agrawal , Honnappa Nagarahalli , Gavin Hu , nd , Bruce Richardson X-MC-Unique: XHd7PgV2Ne2FotNmE-bosQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v11 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Oct 18, 2019 at 4:25 PM Jerin Jacob wrote: > > On Fri, Oct 18, 2019 at 7:46 PM David Marchand > wrote: > > > > On Fri, Oct 18, 2019 at 1:22 PM Phil Yang wrote: > > > > > > This patch adds the implementation of the 128-bit atomic compare > > > exchange API on AArch64. Using 64-bit 'ldxp/stxp' instructions > > > can perform this operation. Moreover, on the LSE atomic extension > > > accelerated platforms, it implemented by 'casp' instructions for > > > better performance. > > > > > > Since the '__ARM_FEATURE_ATOMICS' flag only supports GCC-9, so this > > > patch adds a new config flag 'RTE_ARM_FEATURE_ATOMICS' to enable the > > > 'cas' version on elder version compilers. > > > > Jerin, Phil, > > > > I am getting a build error on the octeontx2 target: > > > > {standard input}: Assembler messages: > > {standard input}:672: Error: selected processor does not support `casp > > x0,x1,x2,x3,[x4]' > > {standard input}:690: Error: selected processor does not support > > `caspa x0,x1,x2,x3,[x4]' > > {standard input}:708: Error: selected processor does not support > > `caspl x0,x1,x2,x3,[x4]' > > {standard input}:726: Error: selected processor does not support > > `caspal x0,x1,x2,x3,[x4]' > > ninja: build stopped: subcommand failed. > > > > Looking into the meson logs, I can see: > > > > Native C compiler: ccache gcc (gcc 9.2.1 "gcc (GCC) 9.2.1 20190827 > > (Red Hat 9.2.1-1)") > > Cross C compiler: aarch64-linux-gnu-gcc (gcc 8.2.1) > > Host machine cpu family: aarch64 > > Host machine cpu: armv8-a > > Target machine cpu family: aarch64 > > Target machine cpu: armv8-a > > Build machine cpu family: x86_64 > > Build machine cpu: x86_64 > > ... > > Message: Implementer : Cavium > > Compiler for C supports arguments -mcpu=3Docteontx2: NO > > The compiler needs either +lse or mcpu=3Docteontx2 to generate casp instr= uction. > Could you try this patch, I can submit a patch if it works for you. Ah cool, I was looking at the march stuff. Tried your patch, it works fine. I'd say we can squash your bits in the current patch, since this was unneeded before this patch. Is this okay for you? > > [master][dpdk-next-net-mrvl] $ git diff > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 979018e16..466522786 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -96,7 +96,7 @@ machine_args_cavium =3D [ > ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra], > ['0xaf', ['-march=3Darmv8.1-a+crc+crypto','-mcpu=3Dthunderx2t99']= , > flags_thunderx2_extra], > - ['0xb2', ['-mcpu=3Docteontx2'], flags_octeontx2_extra]] > + ['0xb2', > ['-march=3Darmv8.2-a+crc+crypto+lse','-mcpu=3Docteontx2'], > flags_octeontx2_extra]] > > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] Thanks for the quick reply. --=20 David Marchand