From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B0A80A317C for ; Thu, 17 Oct 2019 17:45:37 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7E66F1E9CB; Thu, 17 Oct 2019 17:45:37 +0200 (CEST) Received: from us-smtp-1.mimecast.com (us-smtp-delivery-1.mimecast.com [205.139.110.120]) by dpdk.org (Postfix) with ESMTP id 46B561E9C7 for ; Thu, 17 Oct 2019 17:45:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571327134; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZlQ0dfQY3aNDegJc0yPicVH7nn8YxlM7OQ3nVShl2wI=; b=gheP7qa4pOPNVmZUljDAr3zWr/5OK1okQD4E0+546D7Al5Zgg2ltUjqi7/GnxoZn7GBSLt EYpVWmsRT2TTI7Qa9O/x1lWcJA04Tn5SlJeuM0jVxQj8wBvU56UiFTg0xbTxr1Sfsm78xX 7h57kX2Bqb3vXeQSaNcmpjk1/DD6bDA= Received: from mail-vk1-f198.google.com (mail-vk1-f198.google.com [209.85.221.198]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-176-eJ2PDydkNLiH84u3k-jS8w-1; Thu, 17 Oct 2019 11:45:33 -0400 Received: by mail-vk1-f198.google.com with SMTP id b11so1104388vkn.1 for ; Thu, 17 Oct 2019 08:45:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kvYDynU0cfJ5tewvl38US+9tq4YHNQq/ZFGjmdAWRYg=; b=SWu06Yvv+VEskaJZfF+rmzndV+oJwYISCEnJXYOOH4+frrgmrzcm+B1+dDb/VpB8xt T0LrxUtjdWR6GWtNmtHM9M5n8DiosYqBxyEuRGKENSuNEkfSRkpofAjWncCUmJ9KW86H 8QpkPtZKCNeuSOyH5AqtdzK5NXqNZuJvt3OcTxRhverRjCyn8y+rks/2N9jI0J0WsWuv GRup47d/WUkaSQxrJsLXb/qg7yS2yF6ab0q1t1RYYvjs0sGb3RYnA4DvBT4jqYTpUIOF erh4CbAidTqD/8ryJC110YD7vJwhhWrHCMmidA0DAzHF05PLcUrlprY0mSAZT2W1sVBj PfcQ== X-Gm-Message-State: APjAAAVEbPR3kANEXi0g8wDpuUD09ZMfa9Z1IZcSjgcxIKWIomYim1vo lRpSDT/GfseelgNl7q7W0Ts7w2J/pjwarRQWxTLz5vh0ed4mQ5ve5Oc6kwwME3OANH14IquwmBR 9MdrHh2IEM5fHths09HQ= X-Received: by 2002:a05:6122:10d4:: with SMTP id l20mr2361491vko.18.1571327132528; Thu, 17 Oct 2019 08:45:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqw8NmlbOo+wSiSgq53v5dikhulT6Sbz/MKYDk36+SgVTJlkvO5Bdq37HI8qL/IakbygvhsMjXsw/WC5nCz56cQ= X-Received: by 2002:a05:6122:10d4:: with SMTP id l20mr2361452vko.18.1571327131891; Thu, 17 Oct 2019 08:45:31 -0700 (PDT) MIME-Version: 1.0 References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> <1569562904-43950-1-git-send-email-gavin.hu@arm.com> <1569562904-43950-3-git-send-email-gavin.hu@arm.com> In-Reply-To: <1569562904-43950-3-git-send-email-gavin.hu@arm.com> From: David Marchand Date: Thu, 17 Oct 2019 17:45:20 +0200 Message-ID: To: Gavin Hu Cc: dev , nd , Thomas Monjalon , Stephen Hemminger , Hemant Agrawal , Jerin Jacob Kollanukkaran , Pavan Nikhilesh , Honnappa Nagarahalli , "Ruifeng Wang (Arm Technology China)" , Phil Yang , Steve Capper X-MC-Unique: eJ2PDydkNLiH84u3k-jS8w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v7 2/7] eal: add the APIs to wait until equal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Sep 27, 2019 at 7:42 AM Gavin Hu wrote: > > The rte_wait_until_equal_xx APIs abstract the functionality of > 'polling for a memory location to become equal to a given value'. > > Add the RTE_ARM_USE_WFE configuration entry for aarch64, disabled > by default. When it is enabled, the above APIs will call WFE instruction > to save CPU cycles and power. - As discussed on irc, I would prefer we have two stages for this: * first stage, an architecture announces it has its own implementation of this api, in such a case it defines RTE_ARCH_HAS_WFE in its arch/xxx/rte_pause.h header before including generic/rte_pause.h The default implementation with C11 is then skipped in the generic header= . * second stage, in the arm64 header, if RTE_ARM_USE_WFE is set in the configuration, then define RTE_ARCH_HAS_WFE - Can you add a little description on the limitation of using WFE instruction in the commit log? - This is a new api, should be marked experimental, even if inlined. Small comments inline. > > Signed-off-by: Gavin Hu > Reviewed-by: Ruifeng Wang > Reviewed-by: Steve Capper > Reviewed-by: Ola Liljedahl > Reviewed-by: Honnappa Nagarahalli > Reviewed-by: Phil Yang > Acked-by: Pavan Nikhilesh > --- > config/arm/meson.build | 1 + > config/common_base | 5 + > .../common/include/arch/arm/rte_pause_64.h | 30 ++++++ > lib/librte_eal/common/include/generic/rte_pause.h | 106 +++++++++++++++= ++++++ > 4 files changed, 142 insertions(+) > > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 979018e..b4b4cac 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -26,6 +26,7 @@ flags_common_default =3D [ > ['RTE_LIBRTE_AVP_PMD', false], > > ['RTE_SCHED_VECTOR', false], > + ['RTE_ARM_USE_WFE', false], > ] > > flags_generic =3D [ > diff --git a/config/common_base b/config/common_base > index 8ef75c2..8861713 100644 > --- a/config/common_base > +++ b/config/common_base > @@ -111,6 +111,11 @@ CONFIG_RTE_MAX_VFIO_CONTAINERS=3D64 > CONFIG_RTE_MALLOC_DEBUG=3Dn > CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn > CONFIG_RTE_USE_LIBBSD=3Dn > +# Use WFE instructions to implement the rte_wait_for_equal_xxx APIs, > +# calling these APIs put the cores in low power state while waiting > +# for the memory address to become equal to the expected value. > +# This is supported only by aarch64. > +CONFIG_RTE_ARM_USE_WFE=3Dn > > # > # Recognize/ignore the AVX/AVX512 CPU flags for performance/power testin= g. > diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/= librte_eal/common/include/arch/arm/rte_pause_64.h > index 93895d3..dabde17 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > @@ -1,5 +1,6 @@ > /* SPDX-License-Identifier: BSD-3-Clause > * Copyright(c) 2017 Cavium, Inc > + * Copyright(c) 2019 Arm Limited > */ > > #ifndef _RTE_PAUSE_ARM64_H_ > @@ -17,6 +18,35 @@ static inline void rte_pause(void) > asm volatile("yield" ::: "memory"); > } > > +#ifdef RTE_ARM_USE_WFE > +#define __WAIT_UNTIL_EQUAL(name, asm_op, wide, type) \ > +static __rte_always_inline void \ > +rte_wait_until_equal_##name(volatile type * addr, type expected) \ > +{ \ > + type tmp; \ > + asm volatile( \ > + #asm_op " %" #wide "[tmp], %[addr]\n" \ > + "cmp %" #wide "[tmp], %" #wide "[expected]\n" \ > + "b.eq 2f\n" \ > + "sevl\n" \ > + "1: wfe\n" \ > + #asm_op " %" #wide "[tmp], %[addr]\n" \ > + "cmp %" #wide "[tmp], %" #wide "[expected]\n" \ > + "bne 1b\n" \ > + "2:\n" \ > + : [tmp] "=3D&r" (tmp) \ > + : [addr] "Q"(*addr), [expected] "r"(expected) \ > + : "cc", "memory"); \ > +} > +/* Wait for *addr to be updated with expected value */ > +__WAIT_UNTIL_EQUAL(relaxed_16, ldxrh, w, uint16_t) > +__WAIT_UNTIL_EQUAL(acquire_16, ldaxrh, w, uint16_t) > +__WAIT_UNTIL_EQUAL(relaxed_32, ldxr, w, uint32_t) > +__WAIT_UNTIL_EQUAL(acquire_32, ldaxr, w, uint32_t) > +__WAIT_UNTIL_EQUAL(relaxed_64, ldxr, x, uint64_t) > +__WAIT_UNTIL_EQUAL(acquire_64, ldaxr, x, uint64_t) Missing #undef __WAIT_UNTIL_EQUAL > +#endif > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/common/include/generic/rte_pause.h b/lib/libr= te_eal/common/include/generic/rte_pause.h > index 52bd4db..8906473 100644 > --- a/lib/librte_eal/common/include/generic/rte_pause.h > +++ b/lib/librte_eal/common/include/generic/rte_pause.h > @@ -1,5 +1,6 @@ > /* SPDX-License-Identifier: BSD-3-Clause > * Copyright(c) 2017 Cavium, Inc > + * Copyright(c) 2019 Arm Limited > */ > > #ifndef _RTE_PAUSE_H_ > @@ -12,6 +13,10 @@ > * > */ > > +#include > +#include > +#include > + > /** > * Pause CPU execution for a short while > * > @@ -20,4 +25,105 @@ > */ > static inline void rte_pause(void); > > +/** Missing warning on experimental api. > + * Wait for *addr to be updated with a 16-bit expected value, with a rel= axed > + * memory ordering model meaning the loads around this API can be reorde= red. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 16-bit expected value to be in the memory location. > + */ Missing experimental tag. Saying this only once, please update declarations below, plus doxygen heade= r. > +__rte_always_inline > +static void > +rte_wait_until_equal_relaxed_16(volatile uint16_t *addr, uint16_t expect= ed); > + > +/** > + * Wait for *addr to be updated with a 32-bit expected value, with a rel= axed > + * memory ordering model meaning the loads around this API can be reorde= red. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 32-bit expected value to be in the memory location. > + */ > +__rte_always_inline > +static void > +rte_wait_until_equal_relaxed_32(volatile uint32_t *addr, uint32_t expect= ed); > + > +/** > + * Wait for *addr to be updated with a 64-bit expected value, with a rel= axed > + * memory ordering model meaning the loads around this API can be reorde= red. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 64-bit expected value to be in the memory location. > + */ > +__rte_always_inline > +static void > +rte_wait_until_equal_relaxed_64(volatile uint64_t *addr, uint64_t expect= ed); > + > +/** > + * Wait for *addr to be updated with a 16-bit expected value, with an ac= quire > + * memory ordering model meaning the loads after this API can't be obser= ved > + * before this API. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 16-bit expected value to be in the memory location. > + */ > +__rte_always_inline > +static void > +rte_wait_until_equal_acquire_16(volatile uint16_t *addr, uint16_t expect= ed); > + > +/** > + * Wait for *addr to be updated with a 32-bit expected value, with an ac= quire > + * memory ordering model meaning the loads after this API can't be obser= ved > + * before this API. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 32-bit expected value to be in the memory location. > + */ > +__rte_always_inline > +static void > +rte_wait_until_equal_acquire_32(volatile uint32_t *addr, uint32_t expect= ed); > + > +/** > + * Wait for *addr to be updated with a 64-bit expected value, with an ac= quire > + * memory ordering model meaning the loads after this API can't be obser= ved > + * before this API. > + * > + * @param addr > + * A pointer to the memory location. > + * @param expected > + * A 64-bit expected value to be in the memory location. > + */ > +__rte_always_inline > +static void > +rte_wait_until_equal_acquire_64(volatile uint64_t *addr, uint64_t expect= ed); > + > +#if !defined(RTE_ARM_USE_WFE) > +#define __WAIT_UNTIL_EQUAL(op_name, size, type, memorder) \ > +__rte_always_inline \ > +static void \ > +rte_wait_until_equal_##op_name##_##size(volatile type *addr, \ > + type expected) \ > +{ \ > + while (__atomic_load_n(addr, memorder) !=3D expected) \ > + rte_pause(); \ > +} > + > +/* Wait for *addr to be updated with expected value */ > +__WAIT_UNTIL_EQUAL(relaxed, 16, uint16_t, __ATOMIC_RELAXED) > +__WAIT_UNTIL_EQUAL(acquire, 16, uint16_t, __ATOMIC_ACQUIRE) > +__WAIT_UNTIL_EQUAL(relaxed, 32, uint32_t, __ATOMIC_RELAXED) > +__WAIT_UNTIL_EQUAL(acquire, 32, uint32_t, __ATOMIC_ACQUIRE) > +__WAIT_UNTIL_EQUAL(relaxed, 64, uint64_t, __ATOMIC_RELAXED) > +__WAIT_UNTIL_EQUAL(acquire, 64, uint64_t, __ATOMIC_ACQUIRE) #undef __WAIT_UNTIL_EQUAL > +#endif /* RTE_ARM_USE_WFE */ > + > #endif /* _RTE_PAUSE_H_ */ > -- > 2.7.4 > --=20 David Marchand