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From: David Marchand <david.marchand@redhat.com>
Date: Thu, 17 Oct 2019 17:45:20 +0200
Message-ID: <CAJFAV8zg5TvRw7NvjKqKUYFLakmHHLFYZVfJ=gcX-ead2BF50w@mail.gmail.com>
To: Gavin Hu <gavin.hu@arm.com>
Cc: dev <dev@dpdk.org>, nd <nd@arm.com>, Thomas Monjalon <thomas@monjalon.net>,
Stephen Hemminger <stephen@networkplumber.org>,
Hemant Agrawal <hemant.agrawal@nxp.com>,
Jerin Jacob Kollanukkaran <jerinj@marvell.com>,
Pavan Nikhilesh <pbhagavatula@marvell.com>,
Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
"Ruifeng Wang (Arm Technology China)" <ruifeng.wang@arm.com>,
Phil Yang <phil.yang@arm.com>, Steve Capper <steve.capper@arm.com>
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Subject: Re: [dpdk-dev] [PATCH v7 2/7] eal: add the APIs to wait until equal
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On Fri, Sep 27, 2019 at 7:42 AM Gavin Hu <gavin.hu@arm.com> wrote:
>
> The rte_wait_until_equal_xx APIs abstract the functionality of
> 'polling for a memory location to become equal to a given value'.
>
> Add the RTE_ARM_USE_WFE configuration entry for aarch64, disabled
> by default. When it is enabled, the above APIs will call WFE instruction
> to save CPU cycles and power.
- As discussed on irc, I would prefer we have two stages for this:
* first stage, an architecture announces it has its own implementation
of this api, in such a case it defines RTE_ARCH_HAS_WFE in its
arch/xxx/rte_pause.h header before including generic/rte_pause.h
The default implementation with C11 is then skipped in the generic header=
.
* second stage, in the arm64 header, if RTE_ARM_USE_WFE is set in the
configuration, then define RTE_ARCH_HAS_WFE
- Can you add a little description on the limitation of using WFE
instruction in the commit log?
- This is a new api, should be marked experimental, even if inlined.
Small comments inline.
>
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
> Reviewed-by: Steve Capper <steve.capper@arm.com>
> Reviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Reviewed-by: Phil Yang <phil.yang@arm.com>
> Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
> config/arm/meson.build | 1 +
> config/common_base | 5 +
> .../common/include/arch/arm/rte_pause_64.h | 30 ++++++
> lib/librte_eal/common/include/generic/rte_pause.h | 106 +++++++++++++++=
++++++
> 4 files changed, 142 insertions(+)
>
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 979018e..b4b4cac 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -26,6 +26,7 @@ flags_common_default =3D [
> ['RTE_LIBRTE_AVP_PMD', false],
>
> ['RTE_SCHED_VECTOR', false],
> + ['RTE_ARM_USE_WFE', false],
> ]
>
> flags_generic =3D [
> diff --git a/config/common_base b/config/common_base
> index 8ef75c2..8861713 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -111,6 +111,11 @@ CONFIG_RTE_MAX_VFIO_CONTAINERS=3D64
> CONFIG_RTE_MALLOC_DEBUG=3Dn
> CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn
> CONFIG_RTE_USE_LIBBSD=3Dn
> +# Use WFE instructions to implement the rte_wait_for_equal_xxx APIs,
> +# calling these APIs put the cores in low power state while waiting
> +# for the memory address to become equal to the expected value.
> +# This is supported only by aarch64.
> +CONFIG_RTE_ARM_USE_WFE=3Dn
>
> #
> # Recognize/ignore the AVX/AVX512 CPU flags for performance/power testin=
g.
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/=
librte_eal/common/include/arch/arm/rte_pause_64.h
> index 93895d3..dabde17 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h
> @@ -1,5 +1,6 @@
> /* SPDX-License-Identifier: BSD-3-Clause
> * Copyright(c) 2017 Cavium, Inc
> + * Copyright(c) 2019 Arm Limited
> */
>
> #ifndef _RTE_PAUSE_ARM64_H_
> @@ -17,6 +18,35 @@ static inline void rte_pause(void)
> asm volatile("yield" ::: "memory");
> }
>
> +#ifdef RTE_ARM_USE_WFE
> +#define __WAIT_UNTIL_EQUAL(name, asm_op, wide, type) \
> +static __rte_always_inline void \
> +rte_wait_until_equal_##name(volatile type * addr, type expected) \
> +{ \
> + type tmp; \
> + asm volatile( \
> + #asm_op " %" #wide "[tmp], %[addr]\n" \
> + "cmp %" #wide "[tmp], %" #wide "[expected]\n" \
> + "b.eq 2f\n" \
> + "sevl\n" \
> + "1: wfe\n" \
> + #asm_op " %" #wide "[tmp], %[addr]\n" \
> + "cmp %" #wide "[tmp], %" #wide "[expected]\n" \
> + "bne 1b\n" \
> + "2:\n" \
> + : [tmp] "=3D&r" (tmp) \
> + : [addr] "Q"(*addr), [expected] "r"(expected) \
> + : "cc", "memory"); \
> +}
> +/* Wait for *addr to be updated with expected value */
> +__WAIT_UNTIL_EQUAL(relaxed_16, ldxrh, w, uint16_t)
> +__WAIT_UNTIL_EQUAL(acquire_16, ldaxrh, w, uint16_t)
> +__WAIT_UNTIL_EQUAL(relaxed_32, ldxr, w, uint32_t)
> +__WAIT_UNTIL_EQUAL(acquire_32, ldaxr, w, uint32_t)
> +__WAIT_UNTIL_EQUAL(relaxed_64, ldxr, x, uint64_t)
> +__WAIT_UNTIL_EQUAL(acquire_64, ldaxr, x, uint64_t)
Missing #undef __WAIT_UNTIL_EQUAL
> +#endif
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/lib/librte_eal/common/include/generic/rte_pause.h b/lib/libr=
te_eal/common/include/generic/rte_pause.h
> index 52bd4db..8906473 100644
> --- a/lib/librte_eal/common/include/generic/rte_pause.h
> +++ b/lib/librte_eal/common/include/generic/rte_pause.h
> @@ -1,5 +1,6 @@
> /* SPDX-License-Identifier: BSD-3-Clause
> * Copyright(c) 2017 Cavium, Inc
> + * Copyright(c) 2019 Arm Limited
> */
>
> #ifndef _RTE_PAUSE_H_
> @@ -12,6 +13,10 @@
> *
> */
>
> +#include <stdint.h>
> +#include <rte_common.h>
> +#include <rte_atomic.h>
> +
> /**
> * Pause CPU execution for a short while
> *
> @@ -20,4 +25,105 @@
> */
> static inline void rte_pause(void);
>
> +/**
Missing warning on experimental api.
> + * Wait for *addr to be updated with a 16-bit expected value, with a rel=
axed
> + * memory ordering model meaning the loads around this API can be reorde=
red.
> + *
> + * @param addr
> + * A pointer to the memory location.
> + * @param expected
> + * A 16-bit expected value to be in the memory location.
> + */
Missing experimental tag.
Saying this only once, please update declarations below, plus doxygen heade=
r.
> +__rte_always_inline
> +static void
> +rte_wait_until_equal_relaxed_16(volatile uint16_t *addr, uint16_t expect=
ed);
> +
> +/**
> + * Wait for *addr to be updated with a 32-bit expected value, with a rel=
axed
> + * memory ordering model meaning the loads around this API can be reorde=
red.
> + *
> + * @param addr
> + * A pointer to the memory location.
> + * @param expected
> + * A 32-bit expected value to be in the memory location.
> + */
> +__rte_always_inline
> +static void
> +rte_wait_until_equal_relaxed_32(volatile uint32_t *addr, uint32_t expect=
ed);
> +
> +/**
> + * Wait for *addr to be updated with a 64-bit expected value, with a rel=
axed
> + * memory ordering model meaning the loads around this API can be reorde=
red.
> + *
> + * @param addr
> + * A pointer to the memory location.
> + * @param expected
> + * A 64-bit expected value to be in the memory location.
> + */
> +__rte_always_inline
> +static void
> +rte_wait_until_equal_relaxed_64(volatile uint64_t *addr, uint64_t expect=
ed);
> +
> +/**
> + * Wait for *addr to be updated with a 16-bit expected value, with an ac=
quire
> + * memory ordering model meaning the loads after this API can't be obser=
ved
> + * before this API.
> + *
> + * @param addr
> + * A pointer to the memory location.
> + * @param expected
> + * A 16-bit expected value to be in the memory location.
> + */
> +__rte_always_inline
> +static void
> +rte_wait_until_equal_acquire_16(volatile uint16_t *addr, uint16_t expect=
ed);
> +
> +/**
> + * Wait for *addr to be updated with a 32-bit expected value, with an ac=
quire
> + * memory ordering model meaning the loads after this API can't be obser=
ved
> + * before this API.
> + *
> + * @param addr
> + * A pointer to the memory location.
> + * @param expected
> + * A 32-bit expected value to be in the memory location.
> + */
> +__rte_always_inline
> +static void
> +rte_wait_until_equal_acquire_32(volatile uint32_t *addr, uint32_t expect=
ed);
> +
> +/**
> + * Wait for *addr to be updated with a 64-bit expected value, with an ac=
quire
> + * memory ordering model meaning the loads after this API can't be obser=
ved
> + * before this API.
> + *
> + * @param addr
> + * A pointer to the memory location.
> + * @param expected
> + * A 64-bit expected value to be in the memory location.
> + */
> +__rte_always_inline
> +static void
> +rte_wait_until_equal_acquire_64(volatile uint64_t *addr, uint64_t expect=
ed);
> +
> +#if !defined(RTE_ARM_USE_WFE)
> +#define __WAIT_UNTIL_EQUAL(op_name, size, type, memorder) \
> +__rte_always_inline \
> +static void \
> +rte_wait_until_equal_##op_name##_##size(volatile type *addr, \
> + type expected) \
> +{ \
> + while (__atomic_load_n(addr, memorder) !=3D expected) \
> + rte_pause(); \
> +}
> +
> +/* Wait for *addr to be updated with expected value */
> +__WAIT_UNTIL_EQUAL(relaxed, 16, uint16_t, __ATOMIC_RELAXED)
> +__WAIT_UNTIL_EQUAL(acquire, 16, uint16_t, __ATOMIC_ACQUIRE)
> +__WAIT_UNTIL_EQUAL(relaxed, 32, uint32_t, __ATOMIC_RELAXED)
> +__WAIT_UNTIL_EQUAL(acquire, 32, uint32_t, __ATOMIC_ACQUIRE)
> +__WAIT_UNTIL_EQUAL(relaxed, 64, uint64_t, __ATOMIC_RELAXED)
> +__WAIT_UNTIL_EQUAL(acquire, 64, uint64_t, __ATOMIC_ACQUIRE)
#undef __WAIT_UNTIL_EQUAL
> +#endif /* RTE_ARM_USE_WFE */
> +
> #endif /* _RTE_PAUSE_H_ */
> --
> 2.7.4
>
--=20
David Marchand