From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BD1DA31F3 for ; Fri, 18 Oct 2019 16:16:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 755041C02F; Fri, 18 Oct 2019 16:16:24 +0200 (CEST) Received: from us-smtp-delivery-1.mimecast.com (us-smtp-1.mimecast.com [207.211.31.81]) by dpdk.org (Postfix) with ESMTP id 74D5D1BEF8 for ; Fri, 18 Oct 2019 16:16:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571408181; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QPbkdDtjMZrO2t8Ha3Coxvi2ZQvn/NwysIx4Au9TKrM=; b=dux9opGF4Ubl3ErqrIsXDRnEmV2FmE6KdUFUqOhZsLbqwuStMfaeZzVmaxpQwqY7za8kQ8 oRm9hskEGuOtYtmwbqXiPYH/jvegyH6IsEA7I+QyFmmF4umXRit2pTeyIaDrp++KGIugcv lzsxToLUJbMMNp2yOphDSjj8AYhdBZ8= Received: from mail-ua1-f71.google.com (mail-ua1-f71.google.com [209.85.222.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-69-z-GDtnQOMDyUtC8gqQFBdA-1; Fri, 18 Oct 2019 10:16:18 -0400 Received: by mail-ua1-f71.google.com with SMTP id r39so778900uad.3 for ; Fri, 18 Oct 2019 07:16:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kfSqSWxEFOY286l++UX9K/SgeNuItV2xeFamXKLaMfc=; b=d9BLdRgYmPjvPz8M4odKp+vBq+pmn7GFcZ6Kza4S4yqbjvTVxo/CVqwysmTHsJ5jfL xC2ko+Qf5Q/gWEPLUVxNXLN6qsS/Y+iu0cETAmhTUebfs5DXUTLjUnf6A31RLhVOBkUl IPThxLPF/7jMUl0FejyArDonqeWByJ2tKqmx1ft/COljw06c7/HjlpfQPdQ/0xnvhbiQ zeo3HrNC23O/VIj2j7vPrkZuoR4c1XO8o+tmdh8l1kQdsgUit2Ja/PWq5KGPST/5X8Ea jSCLx5yr6ggBJYYaUIt8iUKomEkp7PZBI4dkm8SSDz5m4V+hw8rWmsqYiDYNcW4XaXXq /JTQ== X-Gm-Message-State: APjAAAUkzRrOW+EZCOzWjiOQCHKxcRiLNylny2WDP5Wijv6wdefrnBc3 /oWayXv9guzqVEvDCdzuq6YZ1ofB0TjfCs/ZveiLsh8Wr+zgO1yzcoRwqlQM/mckDCA3B5+1Eeq 0ytDoENYOZb5bTrmzlFo= X-Received: by 2002:a1f:a748:: with SMTP id q69mr5621679vke.80.1571408178157; Fri, 18 Oct 2019 07:16:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqzBXdbP/TF/aoYu7dDk5BvmQd0HpTq6ellqllcI35O7ZLgK1xlmEhEDKj7XFDZ6uORMExeHZ00s7e1rkjrm2j8= X-Received: by 2002:a1f:a748:: with SMTP id q69mr5621645vke.80.1571408177588; Fri, 18 Oct 2019 07:16:17 -0700 (PDT) MIME-Version: 1.0 References: <1571139508-21701-1-git-send-email-phil.yang@arm.com> <1571397690-14116-1-git-send-email-phil.yang@arm.com> In-Reply-To: <1571397690-14116-1-git-send-email-phil.yang@arm.com> From: David Marchand Date: Fri, 18 Oct 2019 16:16:06 +0200 Message-ID: To: Jerin Jacob Kollanukkaran , Phil Yang Cc: Gage Eads , dev , Thomas Monjalon , Hemant Agrawal , Honnappa Nagarahalli , Gavin Hu , nd , Bruce Richardson X-MC-Unique: z-GDtnQOMDyUtC8gqQFBdA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v11 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Oct 18, 2019 at 1:22 PM Phil Yang wrote: > > This patch adds the implementation of the 128-bit atomic compare > exchange API on AArch64. Using 64-bit 'ldxp/stxp' instructions > can perform this operation. Moreover, on the LSE atomic extension > accelerated platforms, it implemented by 'casp' instructions for > better performance. > > Since the '__ARM_FEATURE_ATOMICS' flag only supports GCC-9, so this > patch adds a new config flag 'RTE_ARM_FEATURE_ATOMICS' to enable the > 'cas' version on elder version compilers. Jerin, Phil, I am getting a build error on the octeontx2 target: {standard input}: Assembler messages: {standard input}:672: Error: selected processor does not support `casp x0,x1,x2,x3,[x4]' {standard input}:690: Error: selected processor does not support `caspa x0,x1,x2,x3,[x4]' {standard input}:708: Error: selected processor does not support `caspl x0,x1,x2,x3,[x4]' {standard input}:726: Error: selected processor does not support `caspal x0,x1,x2,x3,[x4]' ninja: build stopped: subcommand failed. Looking into the meson logs, I can see: Native C compiler: ccache gcc (gcc 9.2.1 "gcc (GCC) 9.2.1 20190827 (Red Hat 9.2.1-1)") Cross C compiler: aarch64-linux-gnu-gcc (gcc 8.2.1) Host machine cpu family: aarch64 Host machine cpu: armv8-a Target machine cpu family: aarch64 Target machine cpu: armv8-a Build machine cpu family: x86_64 Build machine cpu: x86_64 ... Message: Implementer : Cavium Compiler for C supports arguments -mcpu=3Docteontx2: NO Message: [] Fetching value of define "__ARM_NEON" : 1 Fetching value of define "__ARM_FEATURE_CRC32" : Fetching value of define "__ARM_FEATURE_CRYPTO" : My toolchain does not support the octeontx2 target, but RTE_ARM_FEATURE_ATOMICS ends up being set in the configuration anyway. Tried with Linaro toolchains (4.7.1, 7.4) mentionned in the dpdk documentation, same result. Looking at config/arm/meson.build, the "extra machine specific flags" are appended to the configuration, regardless of what the compiler replied when testing the machine args. --=20 David Marchand