From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2C3A2A3201 for ; Mon, 21 Oct 2019 10:24:31 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CB2BC374E; Mon, 21 Oct 2019 10:24:30 +0200 (CEST) Received: from us-smtp-1.mimecast.com (us-smtp-delivery-1.mimecast.com [205.139.110.120]) by dpdk.org (Postfix) with ESMTP id E44132D13 for ; Mon, 21 Oct 2019 10:24:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571646268; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vg2c0WmQEQeLtLyIhUBbh/gp2H+D0zRdxZHeEiuRhM8=; b=dduwRL4COVBdL0RZWOQJQ7wQeYjUq05qcJXk651Uhs5VkdE7k/a8THPKkHPzv3FnkbIpJT pmR7/7QXcTLMPW+6AbXbma4kTlAplZIU9TB4vbN/Sj+HEks6uEqJa9JhcuAxCQ8knaPDTS TNO/lzA4wWFARCy45jyYEjshn3JqsIE= Received: from mail-vk1-f198.google.com (mail-vk1-f198.google.com [209.85.221.198]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-18-lSigLTPVN1WbB8ZaEkVAQg-1; Mon, 21 Oct 2019 04:24:25 -0400 Received: by mail-vk1-f198.google.com with SMTP id q5so5885346vkg.20 for ; Mon, 21 Oct 2019 01:24:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rY7jZ/SI8XoDoKgfp4PO+QwsUrnJlm5RXk/cqKyOKFk=; b=IOPj5Rys4up8PYE4DAmoajzEIqA4qZ/7co+EckrBx45duHiCXh8kZ96s6PZx7OyoiV ILxg/q0FLW3Y5w6eNwUMGmZ317GqCL7/8+UTBRpF4Hdjjjc9+I+1zliqznGc9hxY4U/6 O/yPQly2lUrqpv/HB4V5NkQfPjK4kPRdaIRmpzhpAtdWYwIREMJOwO42Rz2gNe/L+7zT EJJaDhrPdNEfPRORnCxVgbYF+Zifnz6t9Tl+4Cr5Xe1KdXmFEtJrEy+s2i0YUu4AFM80 GkSEr74pee8DSq4ofnqgfhuW2ITpWAdtVKB4Ram1NPXOl4j9981ivYZIVK7EK0lbp/S2 PPpA== X-Gm-Message-State: APjAAAUhuXmefxOLf2Wm9TqwBCFuihXnkqU9JlV2WUNF23IhtDJnnoN8 V9VSd24d/aWmh6d+4PERzWwc2tubzUol7WiXqvvd8HsfmSRR5hi1G7u9RLKk/1GMJjE1SPNqrra Ov7YnoWAENZVSYq+mfo8= X-Received: by 2002:ab0:304e:: with SMTP id x14mr12399506ual.41.1571646264768; Mon, 21 Oct 2019 01:24:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqzhGBEhDx9iqSrh0nkebVHAFggUltyaWXTAkAgsa5nq4VClqbkfbl6GawH43w6PMqv2GGItaEfLtEOv2zeqJDE= X-Received: by 2002:ab0:304e:: with SMTP id x14mr12399491ual.41.1571646264447; Mon, 21 Oct 2019 01:24:24 -0700 (PDT) MIME-Version: 1.0 References: <1571139508-21701-1-git-send-email-phil.yang@arm.com> <1571397690-14116-1-git-send-email-phil.yang@arm.com> In-Reply-To: From: David Marchand Date: Mon, 21 Oct 2019 10:24:12 +0200 Message-ID: To: Jerin Jacob Cc: Jerin Jacob Kollanukkaran , Phil Yang , Gage Eads , dev , Thomas Monjalon , Hemant Agrawal , Honnappa Nagarahalli , Gavin Hu , nd , Bruce Richardson X-MC-Unique: lSigLTPVN1WbB8ZaEkVAQg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v11 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Oct 18, 2019 at 4:36 PM Jerin Jacob wrote: > > On Fri, Oct 18, 2019 at 8:04 PM David Marchand > wrote: > > > > On Fri, Oct 18, 2019 at 4:25 PM Jerin Jacob wro= te: > > > > > > On Fri, Oct 18, 2019 at 7:46 PM David Marchand > > > wrote: > > > > > > > > On Fri, Oct 18, 2019 at 1:22 PM Phil Yang wrote= : > > > > > > > > > > This patch adds the implementation of the 128-bit atomic compare > > > > > exchange API on AArch64. Using 64-bit 'ldxp/stxp' instructions > > > > > can perform this operation. Moreover, on the LSE atomic extension > > > > > accelerated platforms, it implemented by 'casp' instructions for > > > > > better performance. > > > > > > > > > > Since the '__ARM_FEATURE_ATOMICS' flag only supports GCC-9, so th= is > > > > > patch adds a new config flag 'RTE_ARM_FEATURE_ATOMICS' to enable = the > > > > > 'cas' version on elder version compilers. > > > > > > > > Jerin, Phil, > > > > > > > > I am getting a build error on the octeontx2 target: > > > > > > > > {standard input}: Assembler messages: > > > > {standard input}:672: Error: selected processor does not support `c= asp > > > > x0,x1,x2,x3,[x4]' > > > > {standard input}:690: Error: selected processor does not support > > > > `caspa x0,x1,x2,x3,[x4]' > > > > {standard input}:708: Error: selected processor does not support > > > > `caspl x0,x1,x2,x3,[x4]' > > > > {standard input}:726: Error: selected processor does not support > > > > `caspal x0,x1,x2,x3,[x4]' > > > > ninja: build stopped: subcommand failed. > > > > > > > > Looking into the meson logs, I can see: > > > > > > > > Native C compiler: ccache gcc (gcc 9.2.1 "gcc (GCC) 9.2.1 20190827 > > > > (Red Hat 9.2.1-1)") > > > > Cross C compiler: aarch64-linux-gnu-gcc (gcc 8.2.1) > > > > Host machine cpu family: aarch64 > > > > Host machine cpu: armv8-a > > > > Target machine cpu family: aarch64 > > > > Target machine cpu: armv8-a > > > > Build machine cpu family: x86_64 > > > > Build machine cpu: x86_64 > > > > ... > > > > Message: Implementer : Cavium > > > > Compiler for C supports arguments -mcpu=3Docteontx2: NO > > > > > > The compiler needs either +lse or mcpu=3Docteontx2 to generate casp i= nstruction. > > > Could you try this patch, I can submit a patch if it works for you. > > > > Ah cool, I was looking at the march stuff. > > Tried your patch, it works fine. > > > > I'd say we can squash your bits in the current patch, since this was > > unneeded before this patch. > > Is this okay for you? > > Yup. > > > > > > > > > > > [master][dpdk-next-net-mrvl] $ git diff > > > diff --git a/config/arm/meson.build b/config/arm/meson.build > > > index 979018e16..466522786 100644 > > > --- a/config/arm/meson.build > > > +++ b/config/arm/meson.build > > > @@ -96,7 +96,7 @@ machine_args_cavium =3D [ > > > ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > > > ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra], > > > ['0xaf', ['-march=3Darmv8.1-a+crc+crypto','-mcpu=3Dthunderx2t= 99'], > > > flags_thunderx2_extra], > > > - ['0xb2', ['-mcpu=3Docteontx2'], flags_octeontx2_extra]] > > > + ['0xb2', > > > ['-march=3Darmv8.2-a+crc+crypto+lse','-mcpu=3Docteontx2'], > > > flags_octeontx2_extra]] > > > > > > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-53= 21) > > > impl_generic =3D ['Generic armv8', flags_generic, machine_args_gener= ic] > > > > Thanks for the quick reply. > > Applied with above fix. Thanks. --=20 David Marchand