* [dpdk-dev] [PATCH 1/5] net/bnx2x: update and reorganize HW registers
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
@ 2019-09-06 7:25 ` Rasesh Mody
2019-09-12 12:17 ` Jerin Jacob
2019-09-23 10:47 ` [dpdk-dev] " Jerin Jacob
2019-09-06 7:25 ` [dpdk-dev] [PATCH 2/5] net/bnx2x: update HSI code Rasesh Mody
` (13 subsequent siblings)
14 siblings, 2 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-06 7:25 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, ferruh.yigit, jerinj, GR-Everest-DPDK-Dev
Update and reorganize HW registers in preparation to update the firmware
to version 7.13.11.
Move HW_INTERRUT_ASSERT_SET_0 out from ecore_reg.h to bnx2x.h.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/bnx2x/bnx2x.c | 3 +-
drivers/net/bnx2x/bnx2x.h | 67 +
drivers/net/bnx2x/ecore_reg.h | 6246 ++++++++++++++++++++++-----------
3 files changed, 4183 insertions(+), 2133 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 1a088269f..47972cd73 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -4095,7 +4095,7 @@ static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
REG_WR(sc, reg_offset, val);
rte_panic("FATAL HW block attention set0 0x%lx",
- (attn & HW_INTERRUT_ASSERT_SET_0));
+ (attn & (long unsigned)HW_INTERRUT_ASSERT_SET_0));
}
}
@@ -10394,7 +10394,6 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
- REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
if (!CHIP_REV_IS_SLOW(sc)) {
/* enable hw interrupt from doorbell Q */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index ceaecb031..1ea8b55c9 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -1714,6 +1714,73 @@ static const uint32_t dmae_reg_go_c[] = {
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
+#define HW_INTERRUT_ASSERT_SET_0 \
+ (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_1 \
+ (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_2 \
+ (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
+ AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
+
+#define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
+ (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
+
+#define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
+
+#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
+
#define MULTI_MASK 0x7f
#define PFS_PER_PORT(sc) \
diff --git a/drivers/net/bnx2x/ecore_reg.h b/drivers/net/bnx2x/ecore_reg.h
index 7af9a2d81..57ef5007e 100644
--- a/drivers/net/bnx2x/ecore_reg.h
+++ b/drivers/net/bnx2x/ecore_reg.h
@@ -13,2105 +13,3991 @@
#ifndef ECORE_REG_H
#define ECORE_REG_H
-
-#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \
- (0x1<<0)
-#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \
- (0x1<<2)
-#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \
- (0x1<<5)
-#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \
- (0x1<<3)
-#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \
- (0x1<<4)
-#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \
- (0x1<<1)
-#define ATC_REG_ATC_INIT_DONE \
- 0x1100bcUL
-#define ATC_REG_ATC_INT_STS_CLR \
- 0x1101c0UL
-#define ATC_REG_ATC_PRTY_MASK \
- 0x1101d8UL
-#define ATC_REG_ATC_PRTY_STS_CLR \
- 0x1101d0UL
-#define BRB1_REG_BRB1_INT_MASK \
- 0x60128UL
-#define BRB1_REG_BRB1_PRTY_MASK \
- 0x60138UL
-#define BRB1_REG_BRB1_PRTY_STS_CLR \
- 0x60130UL
-#define BRB1_REG_MAC_GUARANTIED_0 \
- 0x601e8UL
-#define BRB1_REG_MAC_GUARANTIED_1 \
- 0x60240UL
-#define BRB1_REG_NUM_OF_FULL_BLOCKS \
- 0x60090UL
-#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \
- 0x60078UL
-#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \
- 0x60068UL
-#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \
- 0x60094UL
-#define CCM_REG_CCM_INT_MASK \
- 0xd01e4UL
-#define CCM_REG_CCM_PRTY_MASK \
- 0xd01f4UL
-#define CCM_REG_CCM_PRTY_STS_CLR \
- 0xd01ecUL
-#define CDU_REG_CDU_GLOBAL_PARAMS \
- 0x101020UL
-#define CDU_REG_CDU_INT_MASK \
- 0x10103cUL
-#define CDU_REG_CDU_PRTY_MASK \
- 0x10104cUL
-#define CDU_REG_CDU_PRTY_STS_CLR \
- 0x101044UL
-#define CFC_REG_AC_INIT_DONE \
- 0x104078UL
-#define CFC_REG_CAM_INIT_DONE \
- 0x10407cUL
-#define CFC_REG_CFC_INT_MASK \
- 0x104108UL
-#define CFC_REG_CFC_INT_STS_CLR \
- 0x104100UL
-#define CFC_REG_CFC_PRTY_MASK \
- 0x104118UL
-#define CFC_REG_CFC_PRTY_STS_CLR \
- 0x104110UL
-#define CFC_REG_DEBUG0 \
- 0x104050UL
-#define CFC_REG_INIT_REG \
- 0x10404cUL
-#define CFC_REG_LL_INIT_DONE \
- 0x104074UL
-#define CFC_REG_NUM_LCIDS_INSIDE_PF \
- 0x104120UL
-#define CFC_REG_STRONG_ENABLE_PF \
- 0x104128UL
-#define CFC_REG_WEAK_ENABLE_PF \
- 0x104124UL
-#define CSDM_REG_CSDM_INT_MASK_0 \
- 0xc229cUL
-#define CSDM_REG_CSDM_INT_MASK_1 \
- 0xc22acUL
-#define CSDM_REG_CSDM_PRTY_MASK \
- 0xc22bcUL
-#define CSDM_REG_CSDM_PRTY_STS_CLR \
- 0xc22b4UL
-#define CSEM_REG_CSEM_INT_MASK_0 \
- 0x200110UL
-#define CSEM_REG_CSEM_INT_MASK_1 \
- 0x200120UL
-#define CSEM_REG_CSEM_PRTY_MASK_0 \
- 0x200130UL
-#define CSEM_REG_CSEM_PRTY_MASK_1 \
- 0x200140UL
-#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \
- 0x200128UL
-#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \
- 0x200138UL
-#define CSEM_REG_FAST_MEMORY \
- 0x220000UL
-#define CSEM_REG_INT_TABLE \
- 0x200400UL
-#define CSEM_REG_PASSIVE_BUFFER \
- 0x202000UL
-#define CSEM_REG_PRAM \
- 0x240000UL
-#define CSEM_REG_VFPF_ERR_NUM \
- 0x200380UL
-#define DBG_REG_DBG_PRTY_MASK \
- 0xc0a8UL
-#define DBG_REG_DBG_PRTY_STS_CLR \
- 0xc0a0UL
-#define DMAE_REG_BACKWARD_COMP_EN \
- 0x10207cUL
-#define DMAE_REG_CMD_MEM \
- 0x102400UL
-#define DMAE_REG_DMAE_INT_MASK \
- 0x102054UL
-#define DMAE_REG_DMAE_PRTY_MASK \
- 0x102064UL
-#define DMAE_REG_DMAE_PRTY_STS_CLR \
- 0x10205cUL
-#define DMAE_REG_GO_C0 \
- 0x102080UL
-#define DMAE_REG_GO_C1 \
- 0x102084UL
-#define DMAE_REG_GO_C10 \
- 0x102088UL
-#define DMAE_REG_GO_C11 \
- 0x10208cUL
-#define DMAE_REG_GO_C12 \
- 0x102090UL
-#define DMAE_REG_GO_C13 \
- 0x102094UL
-#define DMAE_REG_GO_C14 \
- 0x102098UL
-#define DMAE_REG_GO_C15 \
- 0x10209cUL
-#define DMAE_REG_GO_C2 \
- 0x1020a0UL
-#define DMAE_REG_GO_C3 \
- 0x1020a4UL
-#define DMAE_REG_GO_C4 \
- 0x1020a8UL
-#define DMAE_REG_GO_C5 \
- 0x1020acUL
-#define DMAE_REG_GO_C6 \
- 0x1020b0UL
-#define DMAE_REG_GO_C7 \
- 0x1020b4UL
-#define DMAE_REG_GO_C8 \
- 0x1020b8UL
-#define DMAE_REG_GO_C9 \
- 0x1020bcUL
-#define DORQ_REG_DORQ_INT_MASK \
- 0x170180UL
-#define DORQ_REG_DORQ_INT_STS_CLR \
- 0x170178UL
-#define DORQ_REG_DORQ_PRTY_MASK \
- 0x170190UL
-#define DORQ_REG_DORQ_PRTY_STS_CLR \
- 0x170188UL
-#define DORQ_REG_DPM_CID_OFST \
- 0x170030UL
-#define DORQ_REG_MAX_RVFID_SIZE \
- 0x1701ecUL
-#define DORQ_REG_NORM_CID_OFST \
- 0x17002cUL
-#define DORQ_REG_PF_USAGE_CNT \
- 0x1701d0UL
-#define DORQ_REG_VF_NORM_CID_BASE \
- 0x1701a0UL
-#define DORQ_REG_VF_NORM_CID_OFST \
- 0x1701f4UL
-#define DORQ_REG_VF_NORM_CID_WND_SIZE \
- 0x1701a4UL
-#define DORQ_REG_VF_NORM_MAX_CID_COUNT \
- 0x1701e4UL
-#define DORQ_REG_VF_NORM_VF_BASE \
- 0x1701a8UL
-#define DORQ_REG_VF_TYPE_MASK_0 \
- 0x170218UL
-#define DORQ_REG_VF_TYPE_MAX_MCID_0 \
- 0x1702d8UL
-#define DORQ_REG_VF_TYPE_MIN_MCID_0 \
- 0x170298UL
-#define DORQ_REG_VF_TYPE_VALUE_0 \
- 0x170258UL
-#define DORQ_REG_VF_USAGE_CNT \
- 0x170320UL
-#define DORQ_REG_VF_USAGE_CT_LIMIT \
- 0x170340UL
-#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \
- (0x1<<4)
-#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \
- (0x1<<0)
-#define HC_CONFIG_0_REG_INT_LINE_EN_0 \
- (0x1<<3)
-#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \
- (0x1<<7)
-#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \
- (0x1<<2)
-#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \
- (0x1<<1)
-#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \
- (0x1<<0)
-#define HC_REG_ATTN_MSG0_ADDR_L \
- 0x108018UL
-#define HC_REG_ATTN_MSG1_ADDR_L \
- 0x108020UL
-#define HC_REG_COMMAND_REG \
- 0x108180UL
-#define HC_REG_CONFIG_0 \
- 0x108000UL
-#define HC_REG_CONFIG_1 \
- 0x108004UL
-#define HC_REG_HC_PRTY_MASK \
- 0x1080a0UL
-#define HC_REG_HC_PRTY_STS_CLR \
- 0x108098UL
-#define HC_REG_INT_MASK \
- 0x108108UL
-#define HC_REG_LEADING_EDGE_0 \
- 0x108040UL
-#define HC_REG_MAIN_MEMORY \
- 0x108800UL
-#define HC_REG_MAIN_MEMORY_SIZE \
- 152
-#define HC_REG_TRAILING_EDGE_0 \
- 0x108044UL
-#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \
- (0x1<<1)
-#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \
- (0x1<<0)
-#define IGU_REG_ATTENTION_ACK_BITS \
- 0x130108UL
-#define IGU_REG_ATTN_MSG_ADDR_H \
- 0x13011cUL
-#define IGU_REG_ATTN_MSG_ADDR_L \
- 0x130120UL
-#define IGU_REG_BLOCK_CONFIGURATION \
- 0x130000UL
-#define IGU_REG_COMMAND_REG_32LSB_DATA \
- 0x130124UL
-#define IGU_REG_COMMAND_REG_CTRL \
- 0x13012cUL
-#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \
- 0x130200UL
-#define IGU_REG_IGU_PRTY_MASK \
- 0x1300a8UL
-#define IGU_REG_IGU_PRTY_STS_CLR \
- 0x1300a0UL
-#define IGU_REG_LEADING_EDGE_LATCH \
- 0x130134UL
-#define IGU_REG_MAPPING_MEMORY \
- 0x131000UL
-#define IGU_REG_MAPPING_MEMORY_SIZE \
- 136
-#define IGU_REG_PBA_STATUS_LSB \
- 0x130138UL
-#define IGU_REG_PBA_STATUS_MSB \
- 0x13013cUL
-#define IGU_REG_PCI_PF_MSIX_EN \
- 0x130144UL
-#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \
- 0x130148UL
-#define IGU_REG_PCI_PF_MSI_EN \
- 0x130140UL
-#define IGU_REG_PENDING_BITS_STATUS \
- 0x130300UL
-#define IGU_REG_PF_CONFIGURATION \
- 0x130154UL
-#define IGU_REG_PROD_CONS_MEMORY \
- 0x132000UL
-#define IGU_REG_RESET_MEMORIES \
- 0x130158UL
-#define IGU_REG_SB_INT_BEFORE_MASK_LSB \
- 0x13015cUL
-#define IGU_REG_SB_INT_BEFORE_MASK_MSB \
- 0x130160UL
-#define IGU_REG_SB_MASK_LSB \
- 0x130164UL
-#define IGU_REG_SB_MASK_MSB \
- 0x130168UL
-#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \
- 0x130800UL
-#define IGU_REG_TRAILING_EDGE_LATCH \
- 0x130104UL
-#define IGU_REG_VF_CONFIGURATION \
- 0x130170UL
-#define MCP_REG_MCPR_ACCESS_LOCK \
- 0x8009c
-#define MCP_REG_MCPR_GP_INPUTS \
- 0x800c0
-#define MCP_REG_MCPR_GP_OENABLE \
- 0x800c8
-#define MCP_REG_MCPR_GP_OUTPUTS \
- 0x800c4
-#define MCP_REG_MCPR_IMC_COMMAND \
- 0x85900
-#define MCP_REG_MCPR_IMC_DATAREG0 \
- 0x85920
-#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \
- 0x85904
-#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \
- 0x86424
-#define MCP_REG_MCPR_NVM_ADDR \
- 0x8640c
-#define MCP_REG_MCPR_NVM_CFG4 \
- 0x8642c
-#define MCP_REG_MCPR_NVM_COMMAND \
- 0x86400
-#define MCP_REG_MCPR_NVM_READ \
- 0x86410
-#define MCP_REG_MCPR_NVM_SW_ARB \
- 0x86420
-#define MCP_REG_MCPR_NVM_WRITE \
- 0x86408
-#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \
- (0x1<<1)
-#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \
- (0x1<<0)
-#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \
- 0xa42cUL
-#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \
- 0xa438UL
-#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \
- 0xa444UL
-#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \
- 0xa450UL
-#define MISC_REG_AEU_AFTER_INVERT_4_MCP \
- 0xa458UL
-#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \
- 0xa700UL
-#define MISC_REG_AEU_CLR_LATCH_SIGNAL \
- 0xa45cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \
- 0xa06cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \
- 0xa07cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \
- 0xa08cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \
- 0xa10cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \
- 0xa11cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \
- 0xa12cUL
-#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \
- 0xa078UL
-#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \
- 0xa118UL
-#define MISC_REG_AEU_ENABLE4_NIG_0 \
- 0xa0f8UL
-#define MISC_REG_AEU_ENABLE4_NIG_1 \
- 0xa198UL
-#define MISC_REG_AEU_ENABLE4_PXP_0 \
- 0xa108UL
-#define MISC_REG_AEU_ENABLE4_PXP_1 \
- 0xa1a8UL
-#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \
- 0xa688UL
-#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \
- 0xa6b0UL
-#define MISC_REG_AEU_GENERAL_ATTN_0 \
- 0xa000UL
-#define MISC_REG_AEU_GENERAL_ATTN_1 \
- 0xa004UL
-#define MISC_REG_AEU_GENERAL_ATTN_10 \
- 0xa028UL
-#define MISC_REG_AEU_GENERAL_ATTN_11 \
- 0xa02cUL
-#define MISC_REG_AEU_GENERAL_ATTN_12 \
- 0xa030UL
-#define MISC_REG_AEU_GENERAL_ATTN_2 \
- 0xa008UL
-#define MISC_REG_AEU_GENERAL_ATTN_3 \
- 0xa00cUL
-#define MISC_REG_AEU_GENERAL_ATTN_4 \
- 0xa010UL
-#define MISC_REG_AEU_GENERAL_ATTN_5 \
- 0xa014UL
-#define MISC_REG_AEU_GENERAL_ATTN_6 \
- 0xa018UL
-#define MISC_REG_AEU_GENERAL_ATTN_7 \
- 0xa01cUL
-#define MISC_REG_AEU_GENERAL_ATTN_8 \
- 0xa020UL
-#define MISC_REG_AEU_GENERAL_ATTN_9 \
- 0xa024UL
-#define MISC_REG_AEU_GENERAL_MASK \
- 0xa61cUL
-#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \
- 0xa060UL
-#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \
- 0xa064UL
-#define MISC_REG_BOND_ID \
- 0xa400UL
-#define MISC_REG_CHIP_NUM \
- 0xa408UL
-#define MISC_REG_CHIP_REV \
- 0xa40cUL
-#define MISC_REG_CHIP_TYPE \
- 0xac60UL
-#define MISC_REG_CHIP_TYPE_57811_MASK \
- (1<<1)
-#define MISC_REG_CPMU_LP_DR_ENABLE \
- 0xa858UL
-#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \
- 0xa84cUL
-#define MISC_REG_CPMU_LP_IDLE_THR_P0 \
- 0xa8a0UL
-#define MISC_REG_CPMU_LP_MASK_ENT_P0 \
- 0xa880UL
-#define MISC_REG_CPMU_LP_MASK_EXT_P0 \
- 0xa888UL
-#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \
- 0xa8b8UL
-#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \
- 0xa8bcUL
-#define MISC_REG_DRIVER_CONTROL_1 \
- 0xa510UL
-#define MISC_REG_DRIVER_CONTROL_7 \
- 0xa3c8UL
-#define MISC_REG_FOUR_PORT_PATH_SWAP \
- 0xa75cUL
-#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \
- 0xa738UL
-#define MISC_REG_FOUR_PORT_PORT_SWAP \
- 0xa754UL
-#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \
- 0xa734UL
-#define MISC_REG_GENERIC_CR_0 \
- 0xa460UL
-#define MISC_REG_GENERIC_CR_1 \
- 0xa464UL
-#define MISC_REG_GENERIC_POR_1 \
- 0xa474UL
-#define MISC_REG_GEN_PURP_HWG \
- 0xa9a0UL
-#define MISC_REG_GPIO \
- 0xa490UL
-#define MISC_REG_GPIO_EVENT_EN \
- 0xa2bcUL
-#define MISC_REG_GPIO_INT \
- 0xa494UL
-#define MISC_REG_GRC_RSV_ATTN \
- 0xa3c0UL
-#define MISC_REG_GRC_TIMEOUT_ATTN \
- 0xa3c4UL
-#define MISC_REG_LCPLL_E40_PWRDWN \
- 0xaa74UL
-#define MISC_REG_LCPLL_E40_RESETB_ANA \
- 0xaa78UL
-#define MISC_REG_LCPLL_E40_RESETB_DIG \
- 0xaa7cUL
-#define MISC_REG_MISC_INT_MASK \
- 0xa388UL
-#define MISC_REG_MISC_PRTY_MASK \
- 0xa398UL
-#define MISC_REG_MISC_PRTY_STS_CLR \
- 0xa390UL
-#define MISC_REG_PORT4MODE_EN \
- 0xa750UL
-#define MISC_REG_PORT4MODE_EN_OVWR \
- 0xa720UL
-#define MISC_REG_RESET_REG_1 \
- 0xa580UL
-#define MISC_REG_RESET_REG_2 \
- 0xa590UL
-#define MISC_REG_SHARED_MEM_ADDR \
- 0xa2b4UL
-#define MISC_REG_SPIO \
- 0xa4fcUL
-#define MISC_REG_SPIO_EVENT_EN \
- 0xa2b8UL
-#define MISC_REG_SPIO_INT \
- 0xa500UL
-#define MISC_REG_TWO_PORT_PATH_SWAP \
- 0xa758UL
-#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \
- 0xa72cUL
-#define MISC_REG_UNPREPARED \
- 0xa424UL
-#define MISC_REG_WC0_CTRL_PHY_ADDR \
- 0xa9ccUL
-#define MISC_REG_WC0_RESET \
- 0xac30UL
-#define MISC_REG_XMAC_CORE_PORT_MODE \
- 0xa964UL
-#define MISC_REG_XMAC_PHY_PORT_MODE \
- 0xa960UL
-#define MSTAT_REG_RX_STAT_GR64_LO \
- 0x200UL
-#define MSTAT_REG_TX_STAT_GTXPOK_LO \
- 0UL
-#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \
- (0x1<<0)
-#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \
- (0x1<<0)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \
- (0x1<<0)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \
- (0x1<<9)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \
- (0x1<<15)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \
- (0xf<<18)
-#define NIG_REG_BMAC0_IN_EN \
- 0x100acUL
-#define NIG_REG_BMAC0_OUT_EN \
- 0x100e0UL
-#define NIG_REG_BMAC0_PAUSE_OUT_EN \
- 0x10110UL
-#define NIG_REG_BMAC0_REGS_OUT_EN \
- 0x100e8UL
-#define NIG_REG_BRB0_PAUSE_IN_EN \
- 0x100c4UL
-#define NIG_REG_BRB1_PAUSE_IN_EN \
- 0x100c8UL
-#define NIG_REG_DEBUG_PACKET_LB \
- 0x10800UL
-#define NIG_REG_EGRESS_DRAIN0_MODE \
- 0x10060UL
-#define NIG_REG_EGRESS_EMAC0_OUT_EN \
- 0x10120UL
-#define NIG_REG_EGRESS_EMAC0_PORT \
- 0x10058UL
-#define NIG_REG_EMAC0_IN_EN \
- 0x100a4UL
-#define NIG_REG_EMAC0_PAUSE_OUT_EN \
- 0x10118UL
-#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \
- 0x10494UL
-#define NIG_REG_INGRESS_BMAC0_MEM \
- 0x10c00UL
-#define NIG_REG_INGRESS_BMAC1_MEM \
- 0x11000UL
-#define NIG_REG_INGRESS_EOP_LB_EMPTY \
- 0x104e0UL
-#define NIG_REG_INGRESS_EOP_LB_FIFO \
- 0x104e4UL
-#define NIG_REG_LATCH_BC_0 \
- 0x16210UL
-#define NIG_REG_LATCH_STATUS_0 \
- 0x18000UL
-#define NIG_REG_LED_10G_P0 \
- 0x10320UL
-#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \
- 0x10318UL
-#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \
- 0x10310UL
-#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \
- 0x10308UL
-#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \
- 0x102f8UL
-#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \
- 0x10300UL
-#define NIG_REG_LED_MODE_P0 \
- 0x102f0UL
-#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \
- 0x16070UL
-#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \
- 0x16074UL
-#define NIG_REG_LLFC_ENABLE_0 \
- 0x16208UL
-#define NIG_REG_LLFC_ENABLE_1 \
- 0x1620cUL
-#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \
- 0x16058UL
-#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \
- 0x1605cUL
-#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \
- 0x16060UL
-#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \
- 0x16064UL
-#define NIG_REG_LLFC_OUT_EN_0 \
- 0x160c8UL
-#define NIG_REG_LLFC_OUT_EN_1 \
- 0x160ccUL
-#define NIG_REG_LLH0_BRB1_DRV_MASK \
- 0x10244UL
-#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \
- 0x16048UL
-#define NIG_REG_LLH0_BRB1_NOT_MCP \
- 0x1025cUL
-#define NIG_REG_LLH0_CLS_TYPE \
- 0x16080UL
-#define NIG_REG_LLH0_FUNC_EN \
- 0x160fcUL
-#define NIG_REG_LLH0_FUNC_MEM \
- 0x16180UL
-#define NIG_REG_LLH0_FUNC_MEM_ENABLE \
- 0x16140UL
-#define NIG_REG_LLH0_FUNC_VLAN_ID \
- 0x16100UL
-#define NIG_REG_LLH0_XCM_MASK \
- 0x10130UL
-#define NIG_REG_LLH1_BRB1_NOT_MCP \
- 0x102dcUL
-#define NIG_REG_LLH1_CLS_TYPE \
- 0x16084UL
-#define NIG_REG_LLH1_FUNC_MEM \
- 0x161c0UL
-#define NIG_REG_LLH1_FUNC_MEM_ENABLE \
- 0x16160UL
-#define NIG_REG_LLH1_FUNC_MEM_SIZE \
- 16
-#define NIG_REG_LLH1_MF_MODE \
- 0x18614UL
-#define NIG_REG_LLH1_XCM_MASK \
- 0x10134UL
-#define NIG_REG_LLH_E1HOV_MODE \
- 0x160d8UL
-#define NIG_REG_LLH_MF_MODE \
- 0x16024UL
-#define NIG_REG_MASK_INTERRUPT_PORT0 \
- 0x10330UL
-#define NIG_REG_MASK_INTERRUPT_PORT1 \
- 0x10334UL
-#define NIG_REG_NIG_EMAC0_EN \
- 0x1003cUL
-#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \
- 0x10044UL
-#define NIG_REG_NIG_INT_STS_CLR_0 \
- 0x103b4UL
-#define NIG_REG_NIG_PRTY_MASK \
- 0x103dcUL
-#define NIG_REG_NIG_PRTY_MASK_0 \
- 0x183c8UL
-#define NIG_REG_NIG_PRTY_MASK_1 \
- 0x183d8UL
-#define NIG_REG_NIG_PRTY_STS_CLR \
- 0x103d4UL
-#define NIG_REG_NIG_PRTY_STS_CLR_0 \
- 0x183c0UL
-#define NIG_REG_NIG_PRTY_STS_CLR_1 \
- 0x183d0UL
-#define NIG_REG_P0_HDRS_AFTER_BASIC \
- 0x18038UL
-#define NIG_REG_P0_HWPFC_ENABLE \
- 0x18078UL
-#define NIG_REG_P0_LLH_FUNC_MEM2 \
- 0x18480UL
-#define NIG_REG_P0_MAC_IN_EN \
- 0x185acUL
-#define NIG_REG_P0_MAC_OUT_EN \
- 0x185b0UL
-#define NIG_REG_P0_MAC_PAUSE_OUT_EN \
- 0x185b4UL
-#define NIG_REG_P0_PKT_PRIORITY_TO_COS \
- 0x18054UL
-#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \
- 0x18058UL
-#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \
- 0x1805cUL
-#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \
- 0x186b0UL
-#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \
- 0x186b4UL
-#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \
- 0x186b8UL
-#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \
- 0x186bcUL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \
- 0x180f0UL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
- 0x18688UL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
- 0x1868cUL
-#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \
- 0x180e8UL
-#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
- 0x180ecUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \
- 0x1810cUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \
- 0x18110UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \
- 0x18114UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \
- 0x18118UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \
- 0x1811cUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \
- 0x186a0UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \
- 0x186a4UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \
- 0x186a8UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \
- 0x186acUL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \
- 0x180f8UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \
- 0x180fcUL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \
- 0x18100UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \
- 0x18104UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \
- 0x18108UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \
- 0x18690UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \
- 0x18694UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \
- 0x18698UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \
- 0x1869cUL
-#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \
- 0x180f4UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \
- 0x180e4UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \
- 0x18680UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \
- 0x18684UL
-#define NIG_REG_P1_HDRS_AFTER_BASIC \
- 0x1818cUL
-#define NIG_REG_P1_HWPFC_ENABLE \
- 0x181d0UL
-#define NIG_REG_P1_LLH_FUNC_MEM2 \
- 0x184c0UL
-#define NIG_REG_P1_MAC_IN_EN \
- 0x185c0UL
-#define NIG_REG_P1_MAC_OUT_EN \
- 0x185c4UL
-#define NIG_REG_P1_MAC_PAUSE_OUT_EN \
- 0x185c8UL
-#define NIG_REG_P1_PKT_PRIORITY_TO_COS \
- 0x181a8UL
-#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \
- 0x181acUL
-#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \
- 0x181b0UL
-#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \
- 0x186f8UL
-#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
- 0x186e8UL
-#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
- 0x186ecUL
-#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \
- 0x18234UL
-#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
- 0x18238UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \
- 0x18258UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \
- 0x1825cUL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \
- 0x18260UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \
- 0x18264UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \
- 0x18268UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \
- 0x186f4UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \
- 0x18244UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \
- 0x18248UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \
- 0x1824cUL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \
- 0x18250UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \
- 0x18254UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \
- 0x186f0UL
-#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \
- 0x18240UL
-#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \
- 0x186e0UL
-#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \
- 0x186e4UL
-#define NIG_REG_PAUSE_ENABLE_0 \
- 0x160c0UL
-#define NIG_REG_PAUSE_ENABLE_1 \
- 0x160c4UL
-#define NIG_REG_PORT_SWAP \
- 0x10394UL
-#define NIG_REG_PPP_ENABLE_0 \
- 0x160b0UL
-#define NIG_REG_PPP_ENABLE_1 \
- 0x160b4UL
-#define NIG_REG_PRS_REQ_IN_EN \
- 0x100b8UL
-#define NIG_REG_SERDES0_CTRL_MD_DEVAD \
- 0x10370UL
-#define NIG_REG_SERDES0_CTRL_MD_ST \
- 0x1036cUL
-#define NIG_REG_SERDES0_CTRL_PHY_ADDR \
- 0x10374UL
-#define NIG_REG_SERDES0_STATUS_LINK_STATUS \
- 0x10578UL
-#define NIG_REG_STAT0_BRB_DISCARD \
- 0x105f0UL
-#define NIG_REG_STAT0_BRB_TRUNCATE \
- 0x105f8UL
-#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \
- 0x10750UL
-#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \
- 0x10760UL
-#define NIG_REG_STAT1_BRB_DISCARD \
- 0x10628UL
-#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \
- 0x107a0UL
-#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \
- 0x107b0UL
-#define NIG_REG_STAT2_BRB_OCTET \
- 0x107e0UL
-#define NIG_REG_STATUS_INTERRUPT_PORT0 \
- 0x10328UL
-#define NIG_REG_STRAP_OVERRIDE \
- 0x10398UL
-#define NIG_REG_XCM0_OUT_EN \
- 0x100f0UL
-#define NIG_REG_XCM1_OUT_EN \
- 0x100f4UL
-#define NIG_REG_XGXS0_CTRL_MD_DEVAD \
- 0x1033cUL
-#define NIG_REG_XGXS0_CTRL_MD_ST \
- 0x10338UL
-#define NIG_REG_XGXS0_CTRL_PHY_ADDR \
- 0x10340UL
-#define NIG_REG_XGXS0_STATUS_LINK10G \
- 0x10680UL
-#define NIG_REG_XGXS0_STATUS_LINK_STATUS \
- 0x10684UL
-#define NIG_REG_XGXS_LANE_SEL_P0 \
- 0x102e8UL
-#define NIG_REG_XGXS_SERDES0_MODE_SEL \
- 0x102e0UL
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \
- (0x1<<0)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \
- (0x1<<9)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \
- (0x1<<15)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \
- (0xf<<18)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \
- 18
-#define PBF_REG_COS0_UPPER_BOUND \
- 0x15c05cUL
-#define PBF_REG_COS0_UPPER_BOUND_P0 \
- 0x15c2ccUL
-#define PBF_REG_COS0_UPPER_BOUND_P1 \
- 0x15c2e4UL
-#define PBF_REG_COS0_WEIGHT \
- 0x15c054UL
-#define PBF_REG_COS0_WEIGHT_P0 \
- 0x15c2a8UL
-#define PBF_REG_COS0_WEIGHT_P1 \
- 0x15c2c0UL
-#define PBF_REG_COS1_UPPER_BOUND \
- 0x15c060UL
-#define PBF_REG_COS1_WEIGHT \
- 0x15c058UL
-#define PBF_REG_COS1_WEIGHT_P0 \
- 0x15c2acUL
-#define PBF_REG_COS1_WEIGHT_P1 \
- 0x15c2c4UL
-#define PBF_REG_COS2_WEIGHT_P0 \
- 0x15c2b0UL
-#define PBF_REG_COS2_WEIGHT_P1 \
- 0x15c2c8UL
-#define PBF_REG_COS3_WEIGHT_P0 \
- 0x15c2b4UL
-#define PBF_REG_COS4_WEIGHT_P0 \
- 0x15c2b8UL
-#define PBF_REG_COS5_WEIGHT_P0 \
- 0x15c2bcUL
-#define PBF_REG_CREDIT_LB_Q \
- 0x140338UL
-#define PBF_REG_CREDIT_Q0 \
- 0x14033cUL
-#define PBF_REG_CREDIT_Q1 \
- 0x140340UL
-#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \
- 0x14005cUL
-#define PBF_REG_DISABLE_PF \
- 0x1402e8UL
-#define PBF_REG_DISABLE_VF \
- 0x1402ecUL
-#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \
- 0x15c288UL
-#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \
- 0x15c28cUL
-#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \
- 0x15c278UL
-#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \
- 0x15c27cUL
-#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \
- 0x15c280UL
-#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \
- 0x15c284UL
-#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \
- 0x15c2a0UL
-#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \
- 0x15c2a4UL
-#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \
- 0x15c270UL
-#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \
- 0x15c274UL
-#define PBF_REG_ETS_ENABLED \
- 0x15c050UL
-#define PBF_REG_HDRS_AFTER_BASIC \
- 0x15c0a8UL
-#define PBF_REG_HDRS_AFTER_TAG_0 \
- 0x15c0b8UL
-#define PBF_REG_HIGH_PRIORITY_COS_NUM \
- 0x15c04cUL
-#define PBF_REG_INIT_CRD_LB_Q \
- 0x15c248UL
-#define PBF_REG_INIT_CRD_Q0 \
- 0x15c230UL
-#define PBF_REG_INIT_CRD_Q1 \
- 0x15c234UL
-#define PBF_REG_INIT_P0 \
- 0x140004UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \
- 0x140354UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \
- 0x140358UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \
- 0x14035cUL
-#define PBF_REG_MUST_HAVE_HDRS \
- 0x15c0c4UL
-#define PBF_REG_NUM_STRICT_ARB_SLOTS \
- 0x15c064UL
-#define PBF_REG_P0_ARB_THRSH \
- 0x1400e4UL
-#define PBF_REG_P0_CREDIT \
- 0x140200UL
-#define PBF_REG_P0_INIT_CRD \
- 0x1400d0UL
-#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \
- 0x140308UL
-#define PBF_REG_P0_PAUSE_ENABLE \
- 0x140014UL
-#define PBF_REG_P0_TQ_LINES_FREED_CNT \
- 0x1402f0UL
-#define PBF_REG_P0_TQ_OCCUPANCY \
- 0x1402fcUL
-#define PBF_REG_P1_CREDIT \
- 0x140208UL
-#define PBF_REG_P1_INIT_CRD \
- 0x1400d4UL
-#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \
- 0x14030cUL
-#define PBF_REG_P1_TQ_LINES_FREED_CNT \
- 0x1402f4UL
-#define PBF_REG_P1_TQ_OCCUPANCY \
- 0x140300UL
-#define PBF_REG_P4_CREDIT \
- 0x140210UL
-#define PBF_REG_P4_INIT_CRD \
- 0x1400e0UL
-#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \
- 0x140310UL
-#define PBF_REG_P4_TQ_LINES_FREED_CNT \
- 0x1402f8UL
-#define PBF_REG_P4_TQ_OCCUPANCY \
- 0x140304UL
-#define PBF_REG_PBF_INT_MASK \
- 0x1401d4UL
-#define PBF_REG_PBF_PRTY_MASK \
- 0x1401e4UL
-#define PBF_REG_PBF_PRTY_STS_CLR \
- 0x1401dcUL
-#define PBF_REG_TAG_ETHERTYPE_0 \
- 0x15c090UL
-#define PBF_REG_TAG_LEN_0 \
- 0x15c09cUL
-#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \
- 0x14038cUL
-#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \
- 0x140390UL
-#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \
- 0x140394UL
-#define PBF_REG_TQ_OCCUPANCY_LB_Q \
- 0x1403a8UL
-#define PBF_REG_TQ_OCCUPANCY_Q0 \
- 0x1403acUL
-#define PBF_REG_TQ_OCCUPANCY_Q1 \
- 0x1403b0UL
-#define PB_REG_PB_INT_MASK \
- 0x28UL
-#define PB_REG_PB_PRTY_MASK \
- 0x38UL
-#define PB_REG_PB_PRTY_STS_CLR \
- 0x30UL
-#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \
- (0x1<<0)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \
- (0x1<<8)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \
- (0x1<<1)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \
- (0x1<<6)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \
- (0x1<<7)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \
- (0x1<<4)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \
- (0x1<<3)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \
- (0x1<<5)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \
- (0x1<<2)
-#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \
- 0x9418UL
-#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
- 0x9478UL
-#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR \
- 0x947cUL
-#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR \
- 0x9480UL
-#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR \
- 0x9474UL
-#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
- 0x942cUL
-#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
- 0x9430UL
-#define PGLUE_B_REG_INTERNAL_VFID_ENABLE \
- 0x9438UL
-#define PGLUE_B_REG_PGLUE_B_INT_STS \
- 0x9298UL
-#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \
- 0x929cUL
-#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \
- 0x92b4UL
-#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \
- 0x92acUL
-#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \
- 0x9458UL
-#define PGLUE_B_REG_TAGS_63_32 \
- 0x9244UL
-#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \
- 0x9470UL
-#define PRS_REG_A_PRSU_20 \
- 0x40134UL
-#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \
- 0x4011cUL
-#define PRS_REG_E1HOV_MODE \
- 0x401c8UL
-#define PRS_REG_HDRS_AFTER_BASIC \
- 0x40238UL
-#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \
- 0x40270UL
-#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \
- 0x40290UL
-#define PRS_REG_HDRS_AFTER_TAG_0 \
- 0x40248UL
-#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \
- 0x40280UL
-#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \
- 0x402a0UL
-#define PRS_REG_MUST_HAVE_HDRS \
- 0x40254UL
-#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \
- 0x4028cUL
-#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \
- 0x402acUL
-#define PRS_REG_NIC_MODE \
- 0x40138UL
-#define PRS_REG_NUM_OF_PACKETS \
- 0x40124UL
-#define PRS_REG_PRS_PRTY_MASK \
- 0x401a4UL
-#define PRS_REG_PRS_PRTY_STS_CLR \
- 0x4019cUL
-#define PRS_REG_TAG_ETHERTYPE_0 \
- 0x401d4UL
-#define PRS_REG_TAG_LEN_0 \
- 0x4022cUL
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \
- (0x1<<19)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \
- (0x1<<20)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \
- (0x1<<22)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \
- (0x1<<23)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \
- (0x1<<24)
-#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \
- (0x1<<7)
-#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \
- (0x1<<7)
-#define PXP2_REG_PGL_ADDR_88_F0 \
- 0x120534UL
-#define PXP2_REG_PGL_ADDR_88_F1 \
- 0x120544UL
-#define PXP2_REG_PGL_ADDR_8C_F0 \
- 0x120538UL
-#define PXP2_REG_PGL_ADDR_8C_F1 \
- 0x120548UL
-#define PXP2_REG_PGL_ADDR_90_F0 \
- 0x12053cUL
-#define PXP2_REG_PGL_ADDR_90_F1 \
- 0x12054cUL
-#define PXP2_REG_PGL_ADDR_94_F0 \
- 0x120540UL
-#define PXP2_REG_PGL_ADDR_94_F1 \
- 0x120550UL
-#define PXP2_REG_PGL_EXP_ROM2 \
- 0x120808UL
-#define PXP2_REG_PGL_PRETEND_FUNC_F0 \
- 0x120674UL
-#define PXP2_REG_PGL_PRETEND_FUNC_F1 \
- 0x120678UL
-#define PXP2_REG_PGL_TAGS_LIMIT \
- 0x1205a8UL
-#define PXP2_REG_PSWRQ_BW_ADD1 \
- 0x1201c0UL
-#define PXP2_REG_PSWRQ_BW_ADD10 \
- 0x1201e4UL
-#define PXP2_REG_PSWRQ_BW_ADD11 \
- 0x1201e8UL
-#define PXP2_REG_PSWRQ_BW_ADD2 \
- 0x1201c4UL
-#define PXP2_REG_PSWRQ_BW_ADD28 \
- 0x120228UL
-#define PXP2_REG_PSWRQ_BW_ADD3 \
- 0x1201c8UL
-#define PXP2_REG_PSWRQ_BW_ADD6 \
- 0x1201d4UL
-#define PXP2_REG_PSWRQ_BW_ADD7 \
- 0x1201d8UL
-#define PXP2_REG_PSWRQ_BW_ADD8 \
- 0x1201dcUL
-#define PXP2_REG_PSWRQ_BW_ADD9 \
- 0x1201e0UL
-#define PXP2_REG_PSWRQ_BW_L1 \
- 0x1202b0UL
-#define PXP2_REG_PSWRQ_BW_L10 \
- 0x1202d4UL
-#define PXP2_REG_PSWRQ_BW_L11 \
- 0x1202d8UL
-#define PXP2_REG_PSWRQ_BW_L2 \
- 0x1202b4UL
-#define PXP2_REG_PSWRQ_BW_L28 \
- 0x120318UL
-#define PXP2_REG_PSWRQ_BW_L3 \
- 0x1202b8UL
-#define PXP2_REG_PSWRQ_BW_L6 \
- 0x1202c4UL
-#define PXP2_REG_PSWRQ_BW_L7 \
- 0x1202c8UL
-#define PXP2_REG_PSWRQ_BW_L8 \
- 0x1202ccUL
-#define PXP2_REG_PSWRQ_BW_L9 \
- 0x1202d0UL
-#define PXP2_REG_PSWRQ_BW_RD \
- 0x120324UL
-#define PXP2_REG_PSWRQ_BW_UB1 \
- 0x120238UL
-#define PXP2_REG_PSWRQ_BW_UB10 \
- 0x12025cUL
-#define PXP2_REG_PSWRQ_BW_UB11 \
- 0x120260UL
-#define PXP2_REG_PSWRQ_BW_UB2 \
- 0x12023cUL
-#define PXP2_REG_PSWRQ_BW_UB28 \
- 0x1202a0UL
-#define PXP2_REG_PSWRQ_BW_UB3 \
- 0x120240UL
-#define PXP2_REG_PSWRQ_BW_UB6 \
- 0x12024cUL
-#define PXP2_REG_PSWRQ_BW_UB7 \
- 0x120250UL
-#define PXP2_REG_PSWRQ_BW_UB8 \
- 0x120254UL
-#define PXP2_REG_PSWRQ_BW_UB9 \
- 0x120258UL
-#define PXP2_REG_PSWRQ_BW_WR \
- 0x120328UL
-#define PXP2_REG_PSWRQ_CDU0_L2P \
- 0x120000UL
-#define PXP2_REG_PSWRQ_QM0_L2P \
- 0x120038UL
-#define PXP2_REG_PSWRQ_SRC0_L2P \
- 0x120054UL
-#define PXP2_REG_PSWRQ_TM0_L2P \
- 0x12001cUL
-#define PXP2_REG_PXP2_INT_MASK_0 \
- 0x120578UL
-#define PXP2_REG_PXP2_INT_MASK_1 \
- 0x120614UL
-#define PXP2_REG_PXP2_INT_STS_0 \
- 0x12056cUL
-#define PXP2_REG_PXP2_INT_STS_1 \
- 0x120608UL
-#define PXP2_REG_PXP2_INT_STS_CLR_0 \
- 0x120570UL
-#define PXP2_REG_PXP2_PRTY_MASK_0 \
- 0x120588UL
-#define PXP2_REG_PXP2_PRTY_MASK_1 \
- 0x120598UL
-#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \
- 0x120580UL
-#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \
- 0x120590UL
-#define PXP2_REG_RD_BLK_CNT \
- 0x120418UL
-#define PXP2_REG_RD_CDURD_SWAP_MODE \
- 0x120404UL
-#define PXP2_REG_RD_DISABLE_INPUTS \
- 0x120374UL
-#define PXP2_REG_RD_INIT_DONE \
- 0x120370UL
-#define PXP2_REG_RD_PBF_SWAP_MODE \
- 0x1203f4UL
-#define PXP2_REG_RD_PORT_IS_IDLE_0 \
- 0x12041cUL
-#define PXP2_REG_RD_PORT_IS_IDLE_1 \
- 0x120420UL
-#define PXP2_REG_RD_QM_SWAP_MODE \
- 0x1203f8UL
-#define PXP2_REG_RD_SRC_SWAP_MODE \
- 0x120400UL
-#define PXP2_REG_RD_SR_CNT \
- 0x120414UL
-#define PXP2_REG_RD_START_INIT \
- 0x12036cUL
-#define PXP2_REG_RD_TM_SWAP_MODE \
- 0x1203fcUL
-#define PXP2_REG_RQ_BW_RD_ADD0 \
- 0x1201bcUL
-#define PXP2_REG_RQ_BW_RD_ADD12 \
- 0x1201ecUL
-#define PXP2_REG_RQ_BW_RD_ADD13 \
- 0x1201f0UL
-#define PXP2_REG_RQ_BW_RD_ADD14 \
- 0x1201f4UL
-#define PXP2_REG_RQ_BW_RD_ADD15 \
- 0x1201f8UL
-#define PXP2_REG_RQ_BW_RD_ADD16 \
- 0x1201fcUL
-#define PXP2_REG_RQ_BW_RD_ADD17 \
- 0x120200UL
-#define PXP2_REG_RQ_BW_RD_ADD18 \
- 0x120204UL
-#define PXP2_REG_RQ_BW_RD_ADD19 \
- 0x120208UL
-#define PXP2_REG_RQ_BW_RD_ADD20 \
- 0x12020cUL
-#define PXP2_REG_RQ_BW_RD_ADD22 \
- 0x120210UL
-#define PXP2_REG_RQ_BW_RD_ADD23 \
- 0x120214UL
-#define PXP2_REG_RQ_BW_RD_ADD24 \
- 0x120218UL
-#define PXP2_REG_RQ_BW_RD_ADD25 \
- 0x12021cUL
-#define PXP2_REG_RQ_BW_RD_ADD26 \
- 0x120220UL
-#define PXP2_REG_RQ_BW_RD_ADD27 \
- 0x120224UL
-#define PXP2_REG_RQ_BW_RD_ADD4 \
- 0x1201ccUL
-#define PXP2_REG_RQ_BW_RD_ADD5 \
- 0x1201d0UL
-#define PXP2_REG_RQ_BW_RD_L0 \
- 0x1202acUL
-#define PXP2_REG_RQ_BW_RD_L12 \
- 0x1202dcUL
-#define PXP2_REG_RQ_BW_RD_L13 \
- 0x1202e0UL
-#define PXP2_REG_RQ_BW_RD_L14 \
- 0x1202e4UL
-#define PXP2_REG_RQ_BW_RD_L15 \
- 0x1202e8UL
-#define PXP2_REG_RQ_BW_RD_L16 \
- 0x1202ecUL
-#define PXP2_REG_RQ_BW_RD_L17 \
- 0x1202f0UL
-#define PXP2_REG_RQ_BW_RD_L18 \
- 0x1202f4UL
-#define PXP2_REG_RQ_BW_RD_L19 \
- 0x1202f8UL
-#define PXP2_REG_RQ_BW_RD_L20 \
- 0x1202fcUL
-#define PXP2_REG_RQ_BW_RD_L22 \
- 0x120300UL
-#define PXP2_REG_RQ_BW_RD_L23 \
- 0x120304UL
-#define PXP2_REG_RQ_BW_RD_L24 \
- 0x120308UL
-#define PXP2_REG_RQ_BW_RD_L25 \
- 0x12030cUL
-#define PXP2_REG_RQ_BW_RD_L26 \
- 0x120310UL
-#define PXP2_REG_RQ_BW_RD_L27 \
- 0x120314UL
-#define PXP2_REG_RQ_BW_RD_L4 \
- 0x1202bcUL
-#define PXP2_REG_RQ_BW_RD_L5 \
- 0x1202c0UL
-#define PXP2_REG_RQ_BW_RD_UBOUND0 \
- 0x120234UL
-#define PXP2_REG_RQ_BW_RD_UBOUND12 \
- 0x120264UL
-#define PXP2_REG_RQ_BW_RD_UBOUND13 \
- 0x120268UL
-#define PXP2_REG_RQ_BW_RD_UBOUND14 \
- 0x12026cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND15 \
- 0x120270UL
-#define PXP2_REG_RQ_BW_RD_UBOUND16 \
- 0x120274UL
-#define PXP2_REG_RQ_BW_RD_UBOUND17 \
- 0x120278UL
-#define PXP2_REG_RQ_BW_RD_UBOUND18 \
- 0x12027cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND19 \
- 0x120280UL
-#define PXP2_REG_RQ_BW_RD_UBOUND20 \
- 0x120284UL
-#define PXP2_REG_RQ_BW_RD_UBOUND22 \
- 0x120288UL
-#define PXP2_REG_RQ_BW_RD_UBOUND23 \
- 0x12028cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND24 \
- 0x120290UL
-#define PXP2_REG_RQ_BW_RD_UBOUND25 \
- 0x120294UL
-#define PXP2_REG_RQ_BW_RD_UBOUND26 \
- 0x120298UL
-#define PXP2_REG_RQ_BW_RD_UBOUND27 \
- 0x12029cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND4 \
- 0x120244UL
-#define PXP2_REG_RQ_BW_RD_UBOUND5 \
- 0x120248UL
-#define PXP2_REG_RQ_BW_WR_ADD29 \
- 0x12022cUL
-#define PXP2_REG_RQ_BW_WR_ADD30 \
- 0x120230UL
-#define PXP2_REG_RQ_BW_WR_L29 \
- 0x12031cUL
-#define PXP2_REG_RQ_BW_WR_L30 \
- 0x120320UL
-#define PXP2_REG_RQ_BW_WR_UBOUND29 \
- 0x1202a4UL
-#define PXP2_REG_RQ_BW_WR_UBOUND30 \
- 0x1202a8UL
-#define PXP2_REG_RQ_CDU_ENDIAN_M \
- 0x1201a0UL
-#define PXP2_REG_RQ_CDU_FIRST_ILT \
- 0x12061cUL
-#define PXP2_REG_RQ_CDU_LAST_ILT \
- 0x120620UL
-#define PXP2_REG_RQ_CDU_P_SIZE \
- 0x120018UL
-#define PXP2_REG_RQ_CFG_DONE \
- 0x1201b4UL
-#define PXP2_REG_RQ_DBG_ENDIAN_M \
- 0x1201a4UL
-#define PXP2_REG_RQ_DISABLE_INPUTS \
- 0x120330UL
-#define PXP2_REG_RQ_DRAM_ALIGN \
- 0x1205b0UL
-#define PXP2_REG_RQ_DRAM_ALIGN_RD \
- 0x12092cUL
-#define PXP2_REG_RQ_DRAM_ALIGN_SEL \
- 0x120930UL
-#define PXP2_REG_RQ_HC_ENDIAN_M \
- 0x1201a8UL
-#define PXP2_REG_RQ_ONCHIP_AT \
- 0x122000UL
-#define PXP2_REG_RQ_ONCHIP_AT_B0 \
- 0x128000UL
-#define PXP2_REG_RQ_PDR_LIMIT \
- 0x12033cUL
-#define PXP2_REG_RQ_QM_ENDIAN_M \
- 0x120194UL
-#define PXP2_REG_RQ_QM_FIRST_ILT \
- 0x120634UL
-#define PXP2_REG_RQ_QM_LAST_ILT \
- 0x120638UL
-#define PXP2_REG_RQ_QM_P_SIZE \
- 0x120050UL
-#define PXP2_REG_RQ_RBC_DONE \
- 0x1201b0UL
-#define PXP2_REG_RQ_RD_MBS0 \
- 0x120160UL
-#define PXP2_REG_RQ_RD_MBS1 \
- 0x120168UL
-#define PXP2_REG_RQ_SRC_ENDIAN_M \
- 0x12019cUL
-#define PXP2_REG_RQ_SRC_FIRST_ILT \
- 0x12063cUL
-#define PXP2_REG_RQ_SRC_LAST_ILT \
- 0x120640UL
-#define PXP2_REG_RQ_SRC_P_SIZE \
- 0x12006cUL
-#define PXP2_REG_RQ_TM_ENDIAN_M \
- 0x120198UL
-#define PXP2_REG_RQ_TM_FIRST_ILT \
- 0x120644UL
-#define PXP2_REG_RQ_TM_LAST_ILT \
- 0x120648UL
-#define PXP2_REG_RQ_TM_P_SIZE \
- 0x120034UL
-#define PXP2_REG_RQ_WR_MBS0 \
- 0x12015cUL
-#define PXP2_REG_RQ_WR_MBS1 \
- 0x120164UL
-#define PXP2_REG_WR_CDU_MPS \
- 0x1205f0UL
-#define PXP2_REG_WR_CSDM_MPS \
- 0x1205d0UL
-#define PXP2_REG_WR_DBG_MPS \
- 0x1205e8UL
-#define PXP2_REG_WR_DMAE_MPS \
- 0x1205ecUL
-#define PXP2_REG_WR_HC_MPS \
- 0x1205c8UL
-#define PXP2_REG_WR_QM_MPS \
- 0x1205dcUL
-#define PXP2_REG_WR_SRC_MPS \
- 0x1205e4UL
-#define PXP2_REG_WR_TM_MPS \
- 0x1205e0UL
-#define PXP2_REG_WR_TSDM_MPS \
- 0x1205d4UL
-#define PXP2_REG_WR_USDMDP_TH \
- 0x120348UL
-#define PXP2_REG_WR_USDM_MPS \
- 0x1205ccUL
-#define PXP2_REG_WR_XSDM_MPS \
- 0x1205d8UL
-#define PXP_REG_HST_DISCARD_DOORBELLS \
- 0x1030a4UL
-#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \
- 0x1030a8UL
-#define PXP_REG_HST_ZONE_PERMISSION_TABLE \
- 0x103400UL
-#define PXP_REG_PXP_INT_MASK_0 \
- 0x103074UL
-#define PXP_REG_PXP_INT_MASK_1 \
- 0x103084UL
-#define PXP_REG_PXP_INT_STS_CLR_0 \
- 0x10306cUL
-#define PXP_REG_PXP_INT_STS_CLR_1 \
- 0x10307cUL
-#define PXP_REG_PXP_PRTY_MASK \
- 0x103094UL
-#define PXP_REG_PXP_PRTY_STS_CLR \
- 0x10308cUL
-#define QM_REG_BASEADDR \
- 0x168900UL
-#define QM_REG_BASEADDR_EXT_A \
- 0x16e100UL
-#define QM_REG_BYTECRDCMDQ_0 \
- 0x16e6e8UL
-#define QM_REG_CONNNUM_0 \
- 0x168020UL
-#define QM_REG_PF_EN \
- 0x16e70cUL
-#define QM_REG_PF_USG_CNT_0 \
- 0x16e040UL
-#define QM_REG_PTRTBL \
- 0x168a00UL
-#define QM_REG_PTRTBL_EXT_A \
- 0x16e200UL
-#define QM_REG_QM_INT_MASK \
- 0x168444UL
-#define QM_REG_QM_PRTY_MASK \
- 0x168454UL
-#define QM_REG_QM_PRTY_STS_CLR \
- 0x16844cUL
-#define QM_REG_QVOQIDX_0 \
- 0x1680f4UL
-#define QM_REG_SOFT_RESET \
- 0x168428UL
-#define QM_REG_VOQQMASK_0_LSB \
- 0x168240UL
-#define SEM_FAST_REG_PARITY_RST \
- 0x18840UL
-#define SRC_REG_COUNTFREE0 \
- 0x40500UL
-#define SRC_REG_FIRSTFREE0 \
- 0x40510UL
-#define SRC_REG_KEYSEARCH_0 \
- 0x40458UL
-#define SRC_REG_KEYSEARCH_1 \
- 0x4045cUL
-#define SRC_REG_KEYSEARCH_2 \
- 0x40460UL
-#define SRC_REG_KEYSEARCH_3 \
- 0x40464UL
-#define SRC_REG_KEYSEARCH_4 \
- 0x40468UL
-#define SRC_REG_KEYSEARCH_5 \
- 0x4046cUL
-#define SRC_REG_KEYSEARCH_6 \
- 0x40470UL
-#define SRC_REG_KEYSEARCH_7 \
- 0x40474UL
-#define SRC_REG_KEYSEARCH_8 \
- 0x40478UL
-#define SRC_REG_KEYSEARCH_9 \
- 0x4047cUL
-#define SRC_REG_LASTFREE0 \
- 0x40530UL
-#define SRC_REG_NUMBER_HASH_BITS0 \
- 0x40400UL
-#define SRC_REG_SOFT_RST \
- 0x4049cUL
-#define SRC_REG_SRC_PRTY_MASK \
- 0x404c8UL
-#define SRC_REG_SRC_PRTY_STS_CLR \
- 0x404c0UL
-#define TCM_REG_PRS_IFEN \
- 0x50020UL
-#define TCM_REG_TCM_INT_MASK \
- 0x501dcUL
-#define TCM_REG_TCM_PRTY_MASK \
- 0x501ecUL
-#define TCM_REG_TCM_PRTY_STS_CLR \
- 0x501e4UL
-#define TM_REG_EN_LINEAR0_TIMER \
- 0x164014UL
-#define TM_REG_LIN0_MAX_ACTIVE_CID \
- 0x164048UL
-#define TM_REG_LIN0_NUM_SCANS \
- 0x1640a0UL
-#define TM_REG_LIN0_SCAN_ON \
- 0x1640d0UL
-#define TM_REG_LIN0_SCAN_TIME \
- 0x16403cUL
-#define TM_REG_LIN0_VNIC_UC \
- 0x164128UL
-#define TM_REG_TM_INT_MASK \
- 0x1640fcUL
-#define TM_REG_TM_PRTY_MASK \
- 0x16410cUL
-#define TM_REG_TM_PRTY_STS_CLR \
- 0x164104UL
-#define TSDM_REG_ENABLE_IN1 \
- 0x42238UL
-#define TSDM_REG_TSDM_INT_MASK_0 \
- 0x4229cUL
-#define TSDM_REG_TSDM_INT_MASK_1 \
- 0x422acUL
-#define TSDM_REG_TSDM_PRTY_MASK \
- 0x422bcUL
-#define TSDM_REG_TSDM_PRTY_STS_CLR \
- 0x422b4UL
-#define TSEM_REG_FAST_MEMORY \
- 0x1a0000UL
-#define TSEM_REG_INT_TABLE \
- 0x180400UL
-#define TSEM_REG_PASSIVE_BUFFER \
- 0x181000UL
-#define TSEM_REG_PRAM \
- 0x1c0000UL
-#define TSEM_REG_TSEM_INT_MASK_0 \
- 0x180100UL
-#define TSEM_REG_TSEM_INT_MASK_1 \
- 0x180110UL
-#define TSEM_REG_TSEM_PRTY_MASK_0 \
- 0x180120UL
-#define TSEM_REG_TSEM_PRTY_MASK_1 \
- 0x180130UL
-#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \
- 0x180118UL
-#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \
- 0x180128UL
-#define TSEM_REG_VFPF_ERR_NUM \
- 0x180380UL
-#define UCM_REG_UCM_INT_MASK \
- 0xe01d4UL
-#define UCM_REG_UCM_PRTY_MASK \
- 0xe01e4UL
-#define UCM_REG_UCM_PRTY_STS_CLR \
- 0xe01dcUL
-#define UMAC_COMMAND_CONFIG_REG_HD_ENA \
- (0x1<<10)
-#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \
- (0x1<<28)
-#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \
- (0x1<<15)
-#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \
- (0x1<<24)
-#define UMAC_COMMAND_CONFIG_REG_PAD_EN \
- (0x1<<5)
-#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \
- (0x1<<8)
-#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \
- (0x1<<4)
-#define UMAC_COMMAND_CONFIG_REG_RX_ENA \
- (0x1<<1)
-#define UMAC_COMMAND_CONFIG_REG_SW_RESET \
- (0x1<<13)
-#define UMAC_COMMAND_CONFIG_REG_TX_ENA \
- (0x1<<0)
-#define UMAC_REG_COMMAND_CONFIG \
- 0x8UL
-#define UMAC_REG_EEE_WAKE_TIMER \
- 0x6cUL
-#define UMAC_REG_MAC_ADDR0 \
- 0xcUL
-#define UMAC_REG_MAC_ADDR1 \
- 0x10UL
-#define UMAC_REG_MAXFR \
- 0x14UL
-#define UMAC_REG_UMAC_EEE_CTRL \
- 0x64UL
-#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \
- (0x1<<3)
-#define USDM_REG_USDM_INT_MASK_0 \
- 0xc42a0UL
-#define USDM_REG_USDM_INT_MASK_1 \
- 0xc42b0UL
-#define USDM_REG_USDM_PRTY_MASK \
- 0xc42c0UL
-#define USDM_REG_USDM_PRTY_STS_CLR \
- 0xc42b8UL
-#define USEM_REG_FAST_MEMORY \
- 0x320000UL
-#define USEM_REG_INT_TABLE \
- 0x300400UL
-#define USEM_REG_PASSIVE_BUFFER \
- 0x302000UL
-#define USEM_REG_PRAM \
- 0x340000UL
-#define USEM_REG_USEM_INT_MASK_0 \
- 0x300110UL
-#define USEM_REG_USEM_INT_MASK_1 \
- 0x300120UL
-#define USEM_REG_USEM_PRTY_MASK_0 \
- 0x300130UL
-#define USEM_REG_USEM_PRTY_MASK_1 \
- 0x300140UL
-#define USEM_REG_USEM_PRTY_STS_CLR_0 \
- 0x300128UL
-#define USEM_REG_USEM_PRTY_STS_CLR_1 \
- 0x300138UL
-#define USEM_REG_VFPF_ERR_NUM \
- 0x300380UL
-#define VFC_MEMORIES_RST_REG_CAM_RST \
- (0x1<<0)
-#define VFC_MEMORIES_RST_REG_RAM_RST \
- (0x1<<1)
-#define VFC_REG_MEMORIES_RST \
- 0x1943cUL
-#define XCM_REG_XCM_INT_MASK \
- 0x202b4UL
-#define XCM_REG_XCM_PRTY_MASK \
- 0x202c4UL
-#define XCM_REG_XCM_PRTY_STS_CLR \
- 0x202bcUL
-#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \
- (0x1<<0)
-#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \
- (0x1<<1)
-#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \
- (0x1<<2)
-#define XMAC_CTRL_REG_RX_EN \
- (0x1<<1)
-#define XMAC_CTRL_REG_SOFT_RESET \
- (0x1<<6)
-#define XMAC_CTRL_REG_TX_EN \
- (0x1<<0)
-#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \
- (0x1<<7)
-#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \
- (0x1<<18)
-#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \
- (0x1<<17)
-#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \
- (0x1<<1)
-#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \
- (0x1<<0)
-#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \
- (0x1<<3)
-#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \
- (0x1<<4)
-#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \
- (0x1<<5)
-#define XMAC_REG_CLEAR_RX_LSS_STATUS \
- 0x60UL
-#define XMAC_REG_CTRL \
- 0UL
-#define XMAC_REG_CTRL_SA_HI \
- 0x2cUL
-#define XMAC_REG_CTRL_SA_LO \
- 0x28UL
-#define XMAC_REG_EEE_CTRL \
- 0xd8UL
-#define XMAC_REG_EEE_TIMERS_HI \
- 0xe4UL
-#define XMAC_REG_PAUSE_CTRL \
- 0x68UL
-#define XMAC_REG_PFC_CTRL \
- 0x70UL
-#define XMAC_REG_PFC_CTRL_HI \
- 0x74UL
-#define XMAC_REG_RX_LSS_CTRL \
- 0x50UL
-#define XMAC_REG_RX_LSS_STATUS \
- 0x58UL
-#define XMAC_REG_RX_MAX_SIZE \
- 0x40UL
-#define XMAC_REG_TX_CTRL \
- 0x20UL
-#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \
- (0x1<<0)
-#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \
- (0x1<<1)
-#define XSDM_REG_OPERATION_GEN \
- 0x1664c4UL
-#define XSDM_REG_XSDM_INT_MASK_0 \
- 0x16629cUL
-#define XSDM_REG_XSDM_INT_MASK_1 \
- 0x1662acUL
-#define XSDM_REG_XSDM_PRTY_MASK \
- 0x1662bcUL
-#define XSDM_REG_XSDM_PRTY_STS_CLR \
- 0x1662b4UL
-#define XSEM_REG_FAST_MEMORY \
- 0x2a0000UL
-#define XSEM_REG_INT_TABLE \
- 0x280400UL
-#define XSEM_REG_PASSIVE_BUFFER \
- 0x282000UL
-#define XSEM_REG_PRAM \
- 0x2c0000UL
-#define XSEM_REG_VFPF_ERR_NUM \
- 0x280380UL
-#define XSEM_REG_XSEM_INT_MASK_0 \
- 0x280110UL
-#define XSEM_REG_XSEM_INT_MASK_1 \
- 0x280120UL
-#define XSEM_REG_XSEM_PRTY_MASK_0 \
- 0x280130UL
-#define XSEM_REG_XSEM_PRTY_MASK_1 \
- 0x280140UL
-#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \
- 0x280128UL
-#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \
- 0x280138UL
-#define MCPR_ACCESS_LOCK_LOCK (1L<<31)
-#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
-#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
-#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
-#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
-#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
-#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
-#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
-#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
-#define MCPR_NVM_COMMAND_DOIT (1L<<4)
-#define MCPR_NVM_COMMAND_DONE (1L<<3)
-#define MCPR_NVM_COMMAND_FIRST (1L<<7)
-#define MCPR_NVM_COMMAND_LAST (1L<<8)
-#define MCPR_NVM_COMMAND_WR (1L<<5)
-#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
-#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
-#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
-
-
-#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
-#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
-#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
-#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
-#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
-#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
-#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
-#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
-#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
-#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
-#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
-#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
-#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
-#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
-#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
-#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
-#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
-#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
-#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
-#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
-#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
-#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
-#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
-#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
-#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
-#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
-#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
-#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
-#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
-#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
-#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
-
-
-#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
-#define EMAC_LED_100MB_OVERRIDE (1L<<2)
-#define EMAC_LED_10MB_OVERRIDE (1L<<3)
-#define EMAC_LED_OVERRIDE (1L<<0)
-#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
-#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
-#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
-#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
-#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
-#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
-#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
-#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
-#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
-#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
-#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
-#define EMAC_MDIO_STATUS_10MB (1L<<1)
-#define EMAC_MODE_25G_MODE (1L<<5)
-#define EMAC_MODE_HALF_DUPLEX (1L<<1)
-#define EMAC_MODE_PORT_GMII (2L<<2)
-#define EMAC_MODE_PORT_MII (1L<<2)
-#define EMAC_MODE_PORT_MII_10M (3L<<2)
-#define EMAC_MODE_RESET (1L<<0)
-#define EMAC_REG_EMAC_LED 0xc
-#define EMAC_REG_EMAC_MAC_MATCH 0x10
-#define EMAC_REG_EMAC_MDIO_COMM 0xac
-#define EMAC_REG_EMAC_MDIO_MODE 0xb4
-#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
-#define EMAC_REG_EMAC_MODE 0x0
-#define EMAC_REG_EMAC_RX_MODE 0xc8
-#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
-#define EMAC_REG_EMAC_RX_STAT_AC 0x180
-#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
-#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
-#define EMAC_REG_EMAC_TX_MODE 0xbc
-#define EMAC_REG_EMAC_TX_STAT_AC 0x280
-#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
-#define EMAC_REG_RX_PFC_MODE 0x320
-#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
-#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
-#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
-#define EMAC_REG_RX_PFC_PARAM 0x324
-#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
-#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
-#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
-#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
-#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
-#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
-#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
-#define EMAC_RX_MODE_FLOW_EN (1L<<2)
-#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
-#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
-#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
-#define EMAC_RX_MODE_RESET (1L<<0)
-#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
-#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
-#define EMAC_TX_MODE_FLOW_EN (1L<<4)
-#define EMAC_TX_MODE_RESET (1L<<0)
-
-
-#define MISC_REGISTERS_GPIO_0 0
-#define MISC_REGISTERS_GPIO_1 1
-#define MISC_REGISTERS_GPIO_2 2
-#define MISC_REGISTERS_GPIO_3 3
-#define MISC_REGISTERS_GPIO_CLR_POS 16
-#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
-#define MISC_REGISTERS_GPIO_FLOAT_POS 24
-#define MISC_REGISTERS_GPIO_HIGH 1
-#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
-#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
-#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
-#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
-#define MISC_REGISTERS_GPIO_INT_SET_POS 16
-#define MISC_REGISTERS_GPIO_LOW 0
-#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
-#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
-#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
-#define MISC_REGISTERS_GPIO_SET_POS 8
-#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
-#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \
- (0x1<<19)
-#define MISC_REGISTERS_RESET_REG_1_RST_HC \
- (0x1<<29)
-#define MISC_REGISTERS_RESET_REG_1_RST_PXP \
- (0x1<<26)
-#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \
- (0x1<<27)
-#define MISC_REGISTERS_RESET_REG_1_RST_QM \
- (0x1<<17)
-#define MISC_REGISTERS_RESET_REG_1_SET 0x584
-#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
-#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \
- (0x1<<24)
-#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \
- (0x1<<25)
-#define MISC_REGISTERS_RESET_REG_2_PGLC \
- (0x1<<19)
-#define MISC_REGISTERS_RESET_REG_2_RST_ATC \
- (0x1<<17)
-#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \
- (0x1<<14)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \
- (0x1<<15)
-#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
-#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \
- (0x1<<11)
-#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \
- (0x1<<13)
-#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \
- (0x1<<16)
-#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
-#define MISC_REGISTERS_RESET_REG_2_SET 0x594
-#define MISC_REGISTERS_RESET_REG_2_UMAC0 \
- (0x1<<20)
-#define MISC_REGISTERS_RESET_REG_2_UMAC1 \
- (0x1<<21)
-#define MISC_REGISTERS_RESET_REG_2_XMAC \
- (0x1<<22)
-#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \
- (0x1<<23)
-#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
-#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
-#define MISC_SPIO_CLR_POS 16
-#define MISC_SPIO_FLOAT (0xffL<<24)
-#define MISC_SPIO_FLOAT_POS 24
-#define MISC_SPIO_INPUT_HI_Z 2
-#define MISC_SPIO_INT_OLD_SET_POS 16
-#define MISC_SPIO_OUTPUT_HIGH 1
-#define MISC_SPIO_OUTPUT_LOW 0
-#define MISC_SPIO_SET_POS 8
-#define MISC_SPIO_SPIO4 0x10
-#define MISC_SPIO_SPIO5 0x20
-#define HW_LOCK_MAX_RESOURCE_VALUE 31
-#define HW_LOCK_RESOURCE_DRV_FLAGS 10
-#define HW_LOCK_RESOURCE_GPIO 1
-#define HW_LOCK_RESOURCE_MDIO 0
-#define HW_LOCK_RESOURCE_NVRAM 12
-#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
-#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
-#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
-#define HW_LOCK_RESOURCE_RECOVERY_REG 11
-#define HW_LOCK_RESOURCE_RESET 5
-#define HW_LOCK_RESOURCE_SPIO 2
-
-
-#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
-#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
-#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1U<<31)
-#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
-#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
-#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
-#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
-#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
-#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
-#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
-#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
-#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
-#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
-#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
-#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
-#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
-#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
-#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
-#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
-#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
-#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
-#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
-#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
-#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
-#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
-#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
-#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
-#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
-#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
-#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
-#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
-#define HW_PRTY_ASSERT_SET_0 \
-(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_1 \
-(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_2 \
-(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_3 \
-(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
-#define HW_PRTY_ASSERT_SET_4 \
-(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
-#define HW_INTERRUT_ASSERT_SET_0 \
-(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
-#define HW_INTERRUT_ASSERT_SET_1 \
-(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
-#define HW_INTERRUT_ASSERT_SET_2 \
-(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
-
-
+#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
+#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
+#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
+#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
+#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
+#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
+/* [R 1] ATC initalization done */
+#define ATC_REG_ATC_INIT_DONE 0x1100bc
+/* [RW 6] Interrupt mask register #0 read/write */
+#define ATC_REG_ATC_INT_MASK 0x1101c8
+/* [R 6] Interrupt register #0 read */
+#define ATC_REG_ATC_INT_STS 0x1101bc
+/* [RC 6] Interrupt register #0 read clear */
+#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
+/* [RW 5] Parity mask register #0 read/write */
+#define ATC_REG_ATC_PRTY_MASK 0x1101d8
+/* [R 5] Parity register #0 read */
+#define ATC_REG_ATC_PRTY_STS 0x1101cc
+/* [RC 5] Parity register #0 read clear */
+#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
+/* [RW 19] Interrupt mask register #0 read/write */
+#define BRB1_REG_BRB1_INT_MASK 0x60128
+/* [R 19] Interrupt register #0 read */
+#define BRB1_REG_BRB1_INT_STS 0x6011c
+/* [RC 19] Interrupt register #0 read clear */
+#define BRB1_REG_BRB1_INT_STS_CLR 0x60120
+/* [RW 4] Parity mask register #0 read/write */
+#define BRB1_REG_BRB1_PRTY_MASK 0x60138
+/* [R 4] Parity register #0 read */
+#define BRB1_REG_BRB1_PRTY_STS 0x6012c
+/* [RC 4] Parity register #0 read clear */
+#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
+/* [RW 11] The number of blocks guarantied for the MAC port. The register is
+ * applicable only when per_class_guaranty_mode is reset. */
+#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
+#define BRB1_REG_MAC_GUARANTIED_1 0x60240
+/* [R 24] The number of full blocks. */
+#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
+/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
+#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
+/* [RW 10] Write client 0: Assert pause threshold. Not Functional */
+#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
+/* [R 24] The number of full blocks occpied by port. */
+#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
+/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
+#define CCM_REG_CAM_OCCUP 0xd0188
+/* [RW 11] Interrupt mask register #0 read/write */
+#define CCM_REG_CCM_INT_MASK 0xd01e4
+/* [R 11] Interrupt register #0 read */
+#define CCM_REG_CCM_INT_STS 0xd01d8
+/* [RC 11] Interrupt register #0 read clear */
+#define CCM_REG_CCM_INT_STS_CLR 0xd01dc
+/* [RW 27] Parity mask register #0 read/write */
+#define CCM_REG_CCM_PRTY_MASK 0xd01f4
+/* [R 27] Parity register #0 read */
+#define CCM_REG_CCM_PRTY_STS 0xd01e8
+/* [RC 27] Parity register #0 read clear */
+#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up. */
+#define CCM_REG_CFC_INIT_CRD 0xd0204
+/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up. */
+#define CCM_REG_CQM_INIT_CRD 0xd020c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the SDM interface is detected. */
+#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
+/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up. */
+#define CCM_REG_FIC0_INIT_CRD 0xd0210
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up. */
+#define CCM_REG_FIC1_INIT_CRD 0xd0214
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the pbf interface is detected. */
+#define CCM_REG_PBF_LENGTH_MIS 0xd0180
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the STORM interface is detected. */
+#define CCM_REG_STORM_LENGTH_MIS 0xd016c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the tsem interface is detected. */
+#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
+/* [RC 1] Set when message length mismatch (relative to last indication) at
+ * the usem interface is detected. */
+#define CCM_REG_USEM_LENGTH_MIS 0xd017c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the xsem interface is detected. */
+#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
+/* [RW 19] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - message length; [12:6] - message
+ * pointer; 18:13] - next pointer. */
+#define CCM_REG_XX_DESCR_TABLE 0xd0300
+#define CCM_REG_XX_DESCR_TABLE_SIZE 24
+/* [R 7] Used to read the value of XX protection Free counter. */
+#define CCM_REG_XX_FREE 0xd0184
+#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
+/* [RW 7] Interrupt mask register #0 read/write */
+#define CDU_REG_CDU_INT_MASK 0x10103c
+/* [R 7] Interrupt register #0 read */
+#define CDU_REG_CDU_INT_STS 0x101030
+/* [RC 7] Interrupt register #0 read clear */
+#define CDU_REG_CDU_INT_STS_CLR 0x101034
+/* [RW 5] Parity mask register #0 read/write */
+#define CDU_REG_CDU_PRTY_MASK 0x10104c
+/* [R 5] Parity register #0 read */
+#define CDU_REG_CDU_PRTY_STS 0x101040
+/* [RC 5] Parity register #0 read clear */
+#define CDU_REG_CDU_PRTY_STS_CLR 0x101044
+/* [RW 32] logging of error data in case of a CDU load error:
+ * {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
+ * ype_error; ctual_active; ctual_compressed_context}; */
+#define CDU_REG_ERROR_DATA 0x101014
+/* [RW 13] activity counter ram access */
+#define CFC_REG_ACTIVITY_COUNTER 0x104400
+#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
+/* [R 1] indication the initializing the activity counter by the hardware
+ * was done. */
+#define CFC_REG_AC_INIT_DONE 0x104078
+/* [R 1] indication the initializing the cams by the hardware was done. */
+#define CFC_REG_CAM_INIT_DONE 0x10407c
+/* [RW 2] Interrupt mask register #0 read/write */
+#define CFC_REG_CFC_INT_MASK 0x104108
+/* [R 2] Interrupt register #0 read */
+#define CFC_REG_CFC_INT_STS 0x1040fc
+/* [RC 2] Interrupt register #0 read clear */
+#define CFC_REG_CFC_INT_STS_CLR 0x104100
+/* [RW 6] Parity mask register #0 read/write */
+#define CFC_REG_CFC_PRTY_MASK 0x104118
+/* [R 6] Parity register #0 read */
+#define CFC_REG_CFC_PRTY_STS 0x10410c
+/* [RC 6] Parity register #0 read clear */
+#define CFC_REG_CFC_PRTY_STS_CLR 0x104110
+/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
+#define CFC_REG_CID_CAM 0x104800
+#define CFC_REG_DEBUG0 0x104050
+/* [R 16] CFC error vector. when the CFC detects an internal error it will
+ * set one of these bits. the bit description can be found in CFC
+ * specifications */
+#define CFC_REG_ERROR_VECTOR 0x10403c
+/* [WB 97] LCID info ram access = {96-vpf; 5:93-pfid; 2:89-type;
+ * 8:85-action; 4-paddrv; 3:20-paddr; 9:4-rstates; -lsf; :0-lstate} */
+#define CFC_REG_INFO_RAM 0x105000
+#define CFC_REG_INFO_RAM_SIZE 1024
+#define CFC_REG_INIT_REG 0x10404c
+/* [RW 22] Link List ram access; data = {prev_pfid; rev_lcid; ext_pfid;
+ * ext_lcid} */
+#define CFC_REG_LINK_LIST 0x104c00
+#define CFC_REG_LINK_LIST_SIZE 256
+/* [R 1] indication the initializing the link list by the hardware was done. */
+#define CFC_REG_LL_INIT_DONE 0x104074
+/* [R 9] Number of allocated LCIDs which are at empty state */
+#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
+/* [R 9] Number of Arriving LCIDs in Link List Block */
+#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
+#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
+/* [R 9] Number of Leaving LCIDs in Link List Block */
+#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
+#define CFC_REG_STRONG_ENABLE_PF 0x104128
+#define CFC_REG_WEAK_ENABLE_PF 0x104124
+/* [RW 32] Interrupt mask register #0 read/write */
+#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
+#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
+/* [R 32] Interrupt register #0 read */
+#define CSDM_REG_CSDM_INT_STS_0 0xc2290
+#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
+/* [RC 32] Interrupt register #0 read clear */
+#define CSDM_REG_CSDM_INT_STS_CLR_0 0xc2294
+#define CSDM_REG_CSDM_INT_STS_CLR_1 0xc22a4
+/* [RW 11] Parity mask register #0 read/write */
+#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
+/* [R 11] Parity register #0 read */
+#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
+/* [RC 11] Parity register #0 read clear */
+#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define CSEM_REG_CSEM_INT_MASK_0 0x200110
+#define CSEM_REG_CSEM_INT_MASK_1 0x200120
+/* [R 32] Interrupt register #0 read */
+#define CSEM_REG_CSEM_INT_STS_0 0x200104
+#define CSEM_REG_CSEM_INT_STS_1 0x200114
+/* [RC 32] Interrupt register #0 read clear */
+#define CSEM_REG_CSEM_INT_STS_CLR_0 0x200108
+#define CSEM_REG_CSEM_INT_STS_CLR_1 0x200118
+/* [RW 32] Parity mask register #0 read/write */
+#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
+#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
+/* [R 32] Parity register #0 read */
+#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
+#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
+/* [RC 32] Parity register #0 read clear */
+#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
+#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each
+ * SEM_FAST register offset. */
+#define CSEM_REG_FAST_MEMORY 0x220000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work */
+#define CSEM_REG_INT_TABLE 0x200400
+/* [WB 128] Debug only. Passive buffer memory */
+#define CSEM_REG_PASSIVE_BUFFER 0x202000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define CSEM_REG_PRAM 0x240000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
+#define CSEM_REG_VFPF_ERR_NUM 0x200380
+/* [RW 2] Interrupt mask register #0 read/write */
+#define DBG_REG_DBG_INT_MASK 0xc098
+/* [R 2] Interrupt register #0 read */
+#define DBG_REG_DBG_INT_STS 0xc08c
+/* [RC 2] Interrupt register #0 read clear */
+#define DBG_REG_DBG_INT_STS_CLR 0xc090
+/* [RW 1] Parity mask register #0 read/write */
+#define DBG_REG_DBG_PRTY_MASK 0xc0a8
+/* [R 1] Parity register #0 read */
+#define DBG_REG_DBG_PRTY_STS 0xc09c
+/* [RC 1] Parity register #0 read clear */
+#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
+/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
+ * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
+ * 4.Completion function=0; 5.Error handling=0 */
+#define DMAE_REG_BACKWARD_COMP_EN 0x10207c
+/* [RW 32] Commands memory. The address to command X; row Y is to calculated
+ * as 14*X+Y. */
+#define DMAE_REG_CMD_MEM 0x102400
+#define DMAE_REG_CMD_MEM_SIZE 224
+/* [RW 2] Interrupt mask register #0 read/write */
+#define DMAE_REG_DMAE_INT_MASK 0x102054
+/* [R 2] Interrupt register #0 read */
+#define DMAE_REG_DMAE_INT_STS 0x102048
+/* [RC 2] Interrupt register #0 read clear */
+#define DMAE_REG_DMAE_INT_STS_CLR 0x10204c
+/* [RW 4] Parity mask register #0 read/write */
+#define DMAE_REG_DMAE_PRTY_MASK 0x102064
+/* [R 4] Parity register #0 read */
+#define DMAE_REG_DMAE_PRTY_STS 0x102058
+/* [RC 4] Parity register #0 read clear */
+#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
+/* [RW 1] Command 0 go. */
+#define DMAE_REG_GO_C0 0x102080
+/* [RW 1] Command 1 go. */
+#define DMAE_REG_GO_C1 0x102084
+/* [RW 1] Command 10 go. */
+#define DMAE_REG_GO_C10 0x102088
+/* [RW 1] Command 11 go. */
+#define DMAE_REG_GO_C11 0x10208c
+/* [RW 1] Command 12 go. */
+#define DMAE_REG_GO_C12 0x102090
+/* [RW 1] Command 13 go. */
+#define DMAE_REG_GO_C13 0x102094
+/* [RW 1] Command 14 go. */
+#define DMAE_REG_GO_C14 0x102098
+/* [RW 1] Command 15 go. */
+#define DMAE_REG_GO_C15 0x10209c
+/* [RW 1] Command 2 go. */
+#define DMAE_REG_GO_C2 0x1020a0
+/* [RW 1] Command 3 go. */
+#define DMAE_REG_GO_C3 0x1020a4
+/* [RW 1] Command 4 go. */
+#define DMAE_REG_GO_C4 0x1020a8
+/* [RW 1] Command 5 go. */
+#define DMAE_REG_GO_C5 0x1020ac
+/* [RW 1] Command 6 go. */
+#define DMAE_REG_GO_C6 0x1020b0
+/* [RW 1] Command 7 go. */
+#define DMAE_REG_GO_C7 0x1020b4
+/* [RW 1] Command 8 go. */
+#define DMAE_REG_GO_C8 0x1020b8
+/* [RW 1] Command 9 go. */
+#define DMAE_REG_GO_C9 0x1020bc
+/* [RW 32] Doorbell address for RBC doorbells (function 0). */
+#define DORQ_REG_DB_ADDR0 0x17008c
+/* [RW 6] Interrupt mask register #0 read/write */
+#define DORQ_REG_DORQ_INT_MASK 0x170180
+/* [R 6] Interrupt register #0 read */
+#define DORQ_REG_DORQ_INT_STS 0x170174
+/* [RC 6] Interrupt register #0 read clear */
+#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
+/* [RW 2] Parity mask register #0 read/write */
+#define DORQ_REG_DORQ_PRTY_MASK 0x170190
+/* [R 2] Parity register #0 read */
+#define DORQ_REG_DORQ_PRTY_STS 0x170184
+/* [RC 2] Parity register #0 read clear */
+#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
+/* [R 13] Current value of the DQ FIFO fill level according to following
+ * pointer. The range is 0 - 256 FIFO rows; where each row stands for the
+ * doorbell. */
+#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
+/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
+ * equal to full threshold; reset on full clear. */
+#define DORQ_REG_DQ_FULL_ST 0x1700c0
+#define DORQ_REG_MAX_RVFID_SIZE 0x1701ec
+#define DORQ_REG_MODE_ACT 0x170008
+/* [RW 5] The normal mode CID extraction offset. */
+#define DORQ_REG_NORM_CID_OFST 0x17002c
+#define DORQ_REG_PF_USAGE_CNT 0x1701d0
+/* [R 4] Current value of response A counter credit. Initial credit is
+ * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+ * register. */
+#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
+/* [R 4] Current value of response B counter credit. Initial credit is
+ * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+ * register. */
+#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
+#define DORQ_REG_VF_NORM_CID_BASE 0x1701a0
+#define DORQ_REG_VF_NORM_CID_OFST 0x1701f4
+#define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4
+#define DORQ_REG_VF_NORM_VF_BASE 0x1701a8
+/* [RW 10] VF type validation mask value */
+#define DORQ_REG_VF_TYPE_MASK_0 0x170218
+/* [RW 17] VF type validation Min MCID value */
+#define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8
+/* [RW 17] VF type validation Max MCID value */
+#define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298
+/* [RW 10] VF type validation comp value */
+#define DORQ_REG_VF_TYPE_VALUE_0 0x170258
+#define DORQ_REG_VF_USAGE_CNT 0x170320
+#define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340
+#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
+#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
+#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
+#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
+#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
+#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
+#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
+#define HC_REG_AGG_INT_0 0x108050
+#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
+#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
+#define HC_REG_COMMAND_REG 0x108180
+#define HC_REG_CONFIG_0 0x108000
+#define HC_REG_CONFIG_1 0x108004
+/* [RW 7] Interrupt mask register #0 read/write */
+#define HC_REG_HC_INT_MASK 0x108090
+/* [R 7] Interrupt register #0 read */
+#define HC_REG_HC_INT_STS 0x108084
+/* [RC 7] Interrupt register #0 read clear */
+#define HC_REG_HC_INT_STS_CLR 0x108088
+/* [RW 3] Parity mask register #0 read/write */
+#define HC_REG_HC_PRTY_MASK 0x1080a0
+/* [R 3] Parity register #0 read */
+#define HC_REG_HC_PRTY_STS 0x108094
+/* [RC 3] Parity register #0 read clear */
+#define HC_REG_HC_PRTY_STS_CLR 0x108098
+#define HC_REG_INT_MASK 0x108108
+#define HC_REG_LEADING_EDGE_0 0x108040
+#define HC_REG_MAIN_MEMORY 0x108800
+#define HC_REG_MAIN_MEMORY_SIZE 152
+#define HC_REG_TRAILING_EDGE_0 0x108044
+#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
+#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
+#define IGU_REG_ATTENTION_ACK_BITS 0x130108
+/* [R 4] Debug: attn_fsm */
+#define IGU_REG_ATTN_FSM 0x130054
+#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
+#define IGU_REG_ATTN_MSG_ADDR_L 0x130120
+/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
+ * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
+ * write done didnt receive. */
+#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
+#define IGU_REG_BLOCK_CONFIGURATION 0x130000
+#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
+#define IGU_REG_COMMAND_REG_CTRL 0x13012c
+/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
+ * is clear. The bits in this registers are set and clear via the producer
+ * command. Data valid only in addresses 0-4. all the rest are zero. */
+#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
+/* [R 5] Debug: ctrl_fsm */
+#define IGU_REG_CTRL_FSM 0x130064
+/* [R 1] data availble for error memory. If this bit is clear do not red
+ * from error_handling_memory. */
+#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
+/* [RW 11] Interrupt mask register #0 read/write */
+#define IGU_REG_IGU_INT_MASK 0x130098
+/* [R 11] Interrupt register #0 read */
+#define IGU_REG_IGU_INT_STS 0x13008c
+/* [RC 11] Interrupt register #0 read clear */
+#define IGU_REG_IGU_INT_STS_CLR 0x130090
+/* [RW 11] Parity mask register #0 read/write */
+#define IGU_REG_IGU_PRTY_MASK 0x1300a8
+/* [R 11] Parity register #0 read */
+#define IGU_REG_IGU_PRTY_STS 0x13009c
+/* [RC 11] Parity register #0 read clear */
+#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
+/* [R 4] Debug: int_handle_fsm */
+#define IGU_REG_INT_HANDLE_FSM 0x130050
+#define IGU_REG_LEADING_EDGE_LATCH 0x130134
+/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
+ * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
+ * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
+#define IGU_REG_MAPPING_MEMORY 0x131000
+#define IGU_REG_MAPPING_MEMORY_SIZE 136
+#define IGU_REG_PBA_STATUS_LSB 0x130138
+#define IGU_REG_PBA_STATUS_MSB 0x13013c
+#define IGU_REG_PCI_PF_MSIX_EN 0x130144
+#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
+#define IGU_REG_PCI_PF_MSI_EN 0x130140
+/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
+ * pending; 1 = pending. Pendings means interrupt was asserted; and write
+ * done was not received. Data valid only in addresses 0-4. all the rest are
+ * zero. */
+#define IGU_REG_PENDING_BITS_STATUS 0x130300
+#define IGU_REG_PF_CONFIGURATION 0x130154
+/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
+ * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
+ * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
+ * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
+ * - In backward compatible mode; for non default SB; each even line in the
+ * memory holds the U producer and each odd line hold the C producer. The
+ * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
+ * last 20 producers are for the DSB for each PF. each PF has five segments
+ * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
+ * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
+#define IGU_REG_PROD_CONS_MEMORY 0x132000
+/* [R 3] Debug: pxp_arb_fsm */
+#define IGU_REG_PXP_ARB_FSM 0x130068
+/* [RW 6] Write one for each bit will reset the appropriate memory. When the
+ * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
+ * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
+ * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
+#define IGU_REG_RESET_MEMORIES 0x130158
+/* [R 4] Debug: sb_ctrl_fsm */
+#define IGU_REG_SB_CTRL_FSM 0x13004c
+#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
+#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
+#define IGU_REG_SB_MASK_LSB 0x130164
+#define IGU_REG_SB_MASK_MSB 0x130168
+/* [RW 16] Number of command that were dropped without causing an interrupt
+ * due to: read access for WO BAR address; or write access for RO BAR
+ * address or any access for reserved address or PCI function error is set
+ * and address is not MSIX; PBA or cleanup */
+#define IGU_REG_SILENT_DROP 0x13016c
+/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
+ * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
+ * PF; 68-71 number of ATTN messages per PF */
+#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
+#define IGU_REG_TRAILING_EDGE_LATCH 0x130104
+#define IGU_REG_VF_CONFIGURATION 0x130170
+/* [WB_R 32] Each bit represent write done pending bits status for that SB
+ * (MSI/MSIX message was sent and write done was not received yet). 0 =
+ * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
+#define IGU_REG_WRITE_DONE_PENDING 0x130480
+#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
+#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
+#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
+#define MCP_REG_MCPR_GP_INPUTS 0x800c0
+#define MCP_REG_MCPR_GP_OENABLE 0x800c8
+#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
+#define MCP_REG_MCPR_IMC_COMMAND 0x85900
+#define MCP_REG_MCPR_IMC_DATAREG0 0x85920
+#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
+#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
+#define MCP_REG_MCPR_NVM_ADDR 0x8640c
+#define MCP_REG_MCPR_NVM_CFG4 0x8642c
+#define MCP_REG_MCPR_NVM_COMMAND 0x86400
+#define MCP_REG_MCPR_NVM_READ 0x86410
+#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
+#define MCP_REG_MCPR_NVM_WRITE 0x86408
+#define MCP_REG_MCPR_SCRATCH 0xa0000
+#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
+#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
+/* [R 32] read first 32 bit after inversion of function 0. mapped as
+ * follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
+ * [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
+ * GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
+ * glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
+ * [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
+ * MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
+ * Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
+ * interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
+ * error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
+ * interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30]
+ * PBClient Parity error; [31] PBClient Hw interrupt; */
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
+/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
+ * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+ * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+ * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+ * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+ * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+ * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+ * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+ * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+ * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+ * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+ * Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31]
+ * PBClient Hw interrupt; */
+#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
+/* [R 32] read second 32 bit after inversion of function 0. mapped as
+ * follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error;
+ * [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
+ * [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
+ * XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+ * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+ * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+ * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+ * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+ * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+ * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+ * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
+/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
+ * PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw
+ * interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
+ * Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
+ * interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+ * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+ * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+ * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+ * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+ * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+ * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+ * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
+#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
+/* [R 32] read third 32 bit after inversion of function 0. mapped as
+ * follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
+ * error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
+ * PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+ * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+ * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+ * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+ * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+ * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+ * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+ * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+ * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+ * attn1; */
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
+/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
+ * CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
+ * Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
+ * Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
+ * error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
+ * interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
+ * MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
+ * Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
+ * timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
+ * func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
+ * func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
+ * timers attn_4 func1; [30] General attn0; [31] General attn1; */
+#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
+/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
+ * follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
+/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
+ * General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
+ * [4] General attn6; [5] General attn7; [6] General attn8; [7] General
+ * attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
+ * General attn13; [12] General attn14; [13] General attn15; [14] General
+ * attn16; [15] General attn17; [16] General attn18; [17] General attn19;
+ * [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
+ * RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
+ * RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
+ * attention; [27] GRC Latched reserved access attention; [28] MCP Latched
+ * rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
+ * ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
+/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
+ * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved; */
+#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
+/* [W 14] write to this register results with the clear of the latched
+ * signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
+ * d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
+ * latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
+ * GRC Latched reserved access attention; one in d7 clears Latched
+ * rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
+ * Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
+ * ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
+ * pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
+ * from this register return zero */
+#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
+/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+ * 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw
+ * interrupt; */
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
+/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
+ * 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw
+ * interrupt; */
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
+/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
+/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
+/* [RW 32] fourth 32b for enabling the output for close the gate nig. Mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
+#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
+/* [RW 32] fourth 32b for enabling the output for close the gate pxp. Mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
+#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
+/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
+ * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved; */
+#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
+/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
+ * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved; */
+#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
+/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
+ * 128 bit vector */
+#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
+#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
+#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
+#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
+#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
+#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
+#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
+#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
+#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
+#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
+#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
+#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
+#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
+#define MISC_REG_AEU_GENERAL_MASK 0xa61c
+/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
+ * [9:8] = reserved. 0 = mask; 1 = unmask */
+#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
+#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
+/* [RW 1] If set a system kill occurred. Reset on POR reset. */
+#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
+/* [RW 32] Represent the status of the input vector to the AEU when a system
+ * kill occurred. The register is reset in por reset. Mapped as follows: [0]
+ * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+ * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+ * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+ * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+ * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+ * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+ * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+ * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+ * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+ * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+ * Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31]
+ * PBClient Hw interrupt. Reset on POR reset. */
+#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
+#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
+#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
+#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
+/* [R 32] This field indicates the type of the device. '0' - 2 Ports; '1' -
+ * 1 Port. Global register. */
+#define MISC_REG_BOND_ID 0xa400
+/* [R 16] These bits indicate the part number for the chip. Global register. */
+#define MISC_REG_CHIP_NUM 0xa408
+/* [R 4] These bits indicate the base revision of the chip. This value
+ * starts at 0x0 for the A0 tape-out and increments by one for each
+ * all-layer tape-out. Global register. */
+#define MISC_REG_CHIP_REV 0xa40c
+/* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
+ * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
+ * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
+#define MISC_REG_CHIP_TYPE 0xac60
+#define MISC_REG_CHIP_TYPE_57811_MASK (1<<1)
+#define MISC_REG_CPMU_LP_DR_ENABLE 0xa858
+/* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
+ * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
+ * 25MHz. Reset on hard reset. */
+#define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c
+/* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
+ * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */
+#define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0
+/* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
+ * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
+ * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
+ * the FW command that all Queues are empty is disabled. When 0 indicates
+ * that the FW command that all Queues are empty is enabled. [2] - FW Early
+ * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early
+ * Exit command is disabled. When 0 indicates that the FW Early Exit command
+ * is enabled. This bit applicable only in the EXIT Events Mask registers.
+ * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
+ * is disabled. When 0 indicates that the PBF Request indication is enabled.
+ * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
+ * Request indication is disabled. When 0 indicates that the Tx Other Than
+ * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
+ * indicates that the RX EEE LPI Status indication is disabled. When 0
+ * indicates that the RX EEE LPI Status indication is enabled. In the EXIT
+ * Events Masks registers; this bit masks the falling edge detect of the LPI
+ * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
+ * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
+ * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
+ * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
+ * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
+ * IDLE indication is disabled. When 0 indicates that the QM IDLE indication
+ * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
+ * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
+ * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
+ * Status Mask. When 1 indicates that the L1 Status indication from the PCIE
+ * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
+ * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this
+ * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
+ * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
+ * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
+ * indicates that the P0 EEE LPI REQ indication is disabled. When =0
+ * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
+ * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
+ * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
+ * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
+ * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
+ * REQ indication is disabled. When =0 indicates that the L1 indication is
+ * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
+ * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx
+ * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
+ * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
+ * bit is applicable only in the EXIT Events Masks registers. [17] - L1
+ * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling
+ * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
+ * When =0 indicates that the L1 Status Falling Edge Detect indication from
+ * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
+ * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */
+#define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880
+/* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
+ * that the Vmain SM end state is disabled. When 0 indicates that the Vmain
+ * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
+ * that the FW command that all Queues are empty is disabled. When 0
+ * indicates that the FW command that all Queues are empty is enabled. [2] -
+ * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW
+ * Early Exit command is disabled. When 0 indicates that the FW Early Exit
+ * command is enabled. This bit applicable only in the EXIT Events Mask
+ * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
+ * indication is disabled. When 0 indicates that the PBF Request indication
+ * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
+ * Than PBF Request indication is disabled. When 0 indicates that the Tx
+ * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
+ * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.
+ * When 0 indicates that the RX LPI Status indication is enabled. In the
+ * EXIT Events Masks registers; this bit masks the falling edge detect of
+ * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
+ * indicates that the Tx Pause indication is disabled. When 0 indicates that
+ * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
+ * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
+ * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
+ * indicates that the QM IDLE indication is disabled. When 0 indicates that
+ * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]
+ * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
+ * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
+ * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
+ * Status indication from the PCIE CORE is disabled. When 0 indicates that
+ * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the
+ * EXIT Events Masks registers; this bit masks the falling edge detect of
+ * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
+ * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
+ * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
+ * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
+ * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
+ * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
+ * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
+ * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
+ * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
+ * indicates that the L1 REQ indication is disabled. When =0 indicates that
+ * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
+ * When =1 indicates that the RX EEE LPI Status Falling Edge Detect
+ * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
+ * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE
+ * LPI is on - off). This bit is applicable only in the EXIT Events Masks
+ * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
+ * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled
+ * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
+ * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
+ * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.
+ * Reset on hard reset. */
+#define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888
+/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
+ * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
+ * register. Reset on hard reset. */
+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
+/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
+ * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
+ * register. Reset on hard reset. */
+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
+/* [RW 32] The following driver registers(1...16) represent 16 drivers and
+ * 32 clients. Each client can be controlled by one driver only. One in each
+ * bit represent that this driver control the appropriate client (Ex: bit 5
+ * is set means this driver control client number 5). addr1 = set; addr0 =
+ * clear; read from both addresses will give the same result = status. write
+ * to address 1 will set a request to control all the clients that their
+ * appropriate bit (in the write command) is set. if the client is free (the
+ * appropriate bit in all the other drivers is clear) one will be written to
+ * that driver register; if the client isn't free the bit will remain zero.
+ * if the appropriate bit is set (the driver request to gain control on a
+ * client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
+ * interrupt will be asserted). write to address 0 will set a request to
+ * free all the clients that their appropriate bit (in the write command) is
+ * set. if the appropriate bit is clear (the driver request to free a client
+ * it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
+ * be asserted). */
+#define MISC_REG_DRIVER_CONTROL_1 0xa510
+#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
+/* [R 1] Status of four port mode path swap input pin. */
+#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
+/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
+ * the path_swap output is equal to 4 port mode path swap input pin; if it
+ * is 1 - the path_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the path_swap output. Reset on Hard reset. */
+#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
+/* [R 1] Status of 4 port mode port swap input pin. */
+#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
+/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
+ * the port_swap output is equal to 4 port mode port swap input pin; if it
+ * is 1 - the port_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the port_swap output. Reset on Hard reset. */
+#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
+/* [RW 32] Debug only: spare RW register reset by core reset. Global
+ * register. Reset on core reset. */
+#define MISC_REG_GENERIC_CR_0 0xa460
+#define MISC_REG_GENERIC_CR_1 0xa464
+/* [RW 32] Debug only: spare RW register reset by por reset. Global
+ * register. Reset on POR reset. */
+#define MISC_REG_GENERIC_POR_1 0xa474
+/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
+ * use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
+ * can not be configured as an output. Each output has its output enable in
+ * the MCP register space; but this bit needs to be set to make use of that.
+ * Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
+ * set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
+ * When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
+ * the i/o to an output and will drive the TimeSync output. Bit[31:7]:
+ * spare. Global register. Reset by hard reset. */
+#define MISC_REG_GEN_PURP_HWG 0xa9a0
+/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
+ * these bits is written as a '1'; the corresponding GPIO bit will turn off
+ * it's drivers and become an input. This is the reset state of all GPIO
+ * pins. The read value of these bits will be a '1' if that last command
+ * (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
+ * [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
+ * as a '1'; the corresponding GPIO bit will drive low. The read value of
+ * these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
+ * this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
+ * SET When any of these bits is written as a '1'; the corresponding GPIO
+ * bit will drive high (if it has that capability). The read value of these
+ * bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
+ * bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
+ * RO; These bits indicate the read value of each of the eight GPIO pins.
+ * This is the result value of the pin; not the drive value. Writing these
+ * bits will have not effect. Global register. */
+#define MISC_REG_GPIO 0xa490
+/* [RW 8] These bits enable the GPIO_INTs to signals event to the
+ * IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
+ * p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
+ * [7] p1_gpio_3; Global register. */
+#define MISC_REG_GPIO_EVENT_EN 0xa2bc
+/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
+ * '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
+ * This will acknowledge an interrupt on the falling edge of corresponding
+ * GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
+ * Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
+ * register. This will acknowledge an interrupt on the rising edge of
+ * corresponding GPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
+ * OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
+ * value. When the ~INT_STATE bit is set; this bit indicates the OLD value
+ * of the pin such that if ~INT_STATE is set and this bit is '0'; then the
+ * interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
+ * is '1'; then the interrupt is due to a high to low edge (reset value 0).
+ * [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
+ * current GPIO interrupt state for each GPIO pin. This bit is cleared when
+ * the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
+ * set when the GPIO input does not match the current value in #OLD_VALUE
+ * (reset value 0). Global register. */
+#define MISC_REG_GPIO_INT 0xa494
+/* [R 28] this field hold the last information that caused reserved
+ * attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ * [27:24] the master that caused the attention - according to the following
+ * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+ * dbu; 8 = dmae */
+#define MISC_REG_GRC_RSV_ATTN 0xa3c0
+/* [R 28] this field hold the last information that caused timeout
+ * attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ * [27:24] the master that caused the attention - according to the following
+ * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+ * dbu; 8 = dmae */
+#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
+/* [R 10] Holds the last FID that caused timeout attention. Need to be used
+ * in conjunction with ~misc_registers_timeout_attn; where 3 bits of
+ * function (3 lsb) are also represented. Bit[2:0] - PFID; bit[3] - VFID
+ * valid; bit[9:4] - VFID. Global register. */
+#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa714
+/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
+ * reset. */
+#define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
+/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
+#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
+/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
+ * reset. */
+#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
+/* [RW 8] Interrupt mask register #0 read/write */
+#define MISC_REG_MISC_INT_MASK 0xa388
+/* [R 8] Interrupt register #0 read */
+#define MISC_REG_MISC_INT_STS 0xa37c
+/* [RC 8] Interrupt register #0 read clear */
+#define MISC_REG_MISC_INT_STS_CLR 0xa380
+/* [RW 1] Parity mask register #0 read/write */
+#define MISC_REG_MISC_PRTY_MASK 0xa398
+/* [R 1] Parity register #0 read */
+#define MISC_REG_MISC_PRTY_STS 0xa38c
+/* [RC 1] Parity register #0 read clear */
+#define MISC_REG_MISC_PRTY_STS_CLR 0xa390
+/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
+ * assertion. Global register. */
+#define MISC_REG_PCIE_HOT_RESET 0xa618
+/* [R 1] Status of 4 port mode enable input pin. */
+#define MISC_REG_PORT4MODE_EN 0xa750
+/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
+ * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
+ * the port4mode_en output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the port4mode_en output. Reset on Hard reset. */
+#define MISC_REG_PORT4MODE_EN_OVWR 0xa720
+/* [RW 32] reset reg#1; rite/read one = the specific block is out of reset;
+ * write/read zero = the specific block is in reset; addr 0-wr- the write
+ * value will be written to the register; addr 1-set - one will be written
+ * to all the bits that have the value of one in the data written (bits that
+ * have the value of zero will not be change) ; addr 2-clear - zero will be
+ * written to all the bits that have the value of one in the data written
+ * (bits that have the value of zero will not be change); addr 3-ignore;
+ * read ignore from all addr except addr 00; inside order of the bits is:
+ * [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5]
+ * rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10]
+ * rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15]
+ * rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20]
+ * rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25]
+ * rst_cfc; [26] rst_pxp_hst; [27] rst_pxpv (global register); [28]
+ * rst_rbcp; [29] rst_hc; [30] rst_dmae; [31] rst_semi_rtc; */
+#define MISC_REG_RESET_REG_1 0xa580
+#define MISC_REG_RESET_REG_2 0xa590
+/* [RW 22] 22 bit GRC address where the scratch-pad of the MCP that is
+ * shared with the driver resides */
+#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
+/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
+ * the corresponding SPIO bit will turn off it's drivers and become an
+ * input. This is the reset state of all SPIO pins. The read value of these
+ * bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
+ * bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
+ * is written as a '1'; the corresponding SPIO bit will drive low. The read
+ * value of these bits will be a '1' if that last command (#SET; #CLR; or
+ * #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
+ * these bits is written as a '1'; the corresponding SPIO bit will drive
+ * high (if it has that capability). The read value of these bits will be a
+ * '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
+ * (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
+ * each of the eight SPIO pins. This is the result value of the pin; not the
+ * drive value. Writing these bits will have not effect. Each 8 bits field
+ * is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
+ * from VAUX. (This is an output pin only; the FLOAT field is not applicable
+ * for this pin); [1] VAUX Disable; when pulsed low; disables supply form
+ * VAUX. (This is an output pin only; FLOAT field is not applicable for this
+ * pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
+ * select VAUX supply. (This is an output pin only; it is not controlled by
+ * the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
+ * field is not applicable for this pin; only the VALUE fields is relevant -
+ * it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
+ * Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
+ * device ID select; read by UMP firmware. Global register. */
+#define MISC_REG_SPIO 0xa4fc
+/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
+ * according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
+ * [7:6] reserved. Global register. */
+#define MISC_REG_SPIO_EVENT_EN 0xa2b8
+/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
+ * corresponding bit in the #OLD_VALUE register. This will acknowledge an
+ * interrupt on the falling edge of corresponding SPIO input (reset value
+ * 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
+ * in the #OLD_VALUE register. This will acknowledge an interrupt on the
+ * rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
+ * RO; These bits indicate the old value of the SPIO input value. When the
+ * ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
+ * that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
+ * to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
+ * interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
+ * RO; These bits indicate the current SPIO interrupt state for each SPIO
+ * pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
+ * command bit is written. This bit is set when the SPIO input does not
+ * match the current value in #OLD_VALUE (reset value 0). Global register. */
+#define MISC_REG_SPIO_INT 0xa500
+/* [R 1] Status of two port mode path swap input pin. */
+#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
+/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
+ * path_swap output is equal to 2 port mode path swap input pin; if it is 1
+ * - the path_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the path_swap output. Reset on Hard reset. */
+#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
+/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
+ * loaded; 0-prepare; -unprepare. Global register. Reset on hard reset. */
+#define MISC_REG_UNPREPARED 0xa424
+/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
+ * not it is the recipient of the message on the MDIO interface. The value
+ * is compared to the value on ctrl_md_devad. Drives output
+ * misc_xgxs0_phy_addr. Global register. */
+#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
+/* [RW 10] reset reg#3; rite/read one = the specific block is out of reset;
+ * write/read zero = the specific block is in reset; addr 0-wr- the write
+ * value will be written to the register; addr 1-set - one will be written
+ * to all the bits that have the value of one in the data written (bits that
+ * have the value of zero will not be change) ; addr 2-clear - zero will be
+ * written to all the bits that have the value of one in the data written
+ * (bits that have the value of zero will not be change); addr 3-ignore;
+ * read ignore from all addr except addr 00. [0]: rstb_hw: Active low reset
+ * which when asserted drives entire WC into the reset state. All flops
+ * which within WC are driven into an initial state; as well as the analog
+ * core. Output clocks txck_out; rxck0_10g; and clk_25 will be driven to 0
+ * upon its assertion. [1]: iddq. Enables iddq testing where the supply
+ * current (Idd) is measured in the quiescent state. [2]: pwrdwn: Active
+ * high control which forces the analog core of the WC into power-down mode;
+ * and forces digital logic of the WC into reset. Output clock (refclk)
+ * remains active. [3]: pwrdwn_sd: Power down signal detect. [4]:
+ * txd10g_fifo_rstb: Transmit 10Gbps FIFO reset; active low. Used to reset
+ * the transmit FIFO used in xlgmii operation. [8:5]: txd1g_fifo_rstb:
+ * Transmit 1Gbps FIFO reset; active low. Used to reset the per-lane
+ * transmit FIFOs used in the mii/gmii operation. [9]:
+ * txd10g_fifo_rstb_dxgxs1: Transmit 10Gbps DXGXS FIFO reset; active low.
+ * Used to reset the transmit FIFO used in the DXGXS logic in xlgmii
+ * operation. Global register. */
+#define MISC_REG_WC0_RESET 0xac30
+/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
+ * side. This should be less than or equal to phy_port_mode; if some of the
+ * ports are not used. This enables reduction of frequency on the core side.
+ * This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
+ * Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
+ * input for the XMAC_MP core; and should be changed only while reset is
+ * held low. Reset on Hard reset. */
+#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
+/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
+ * Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
+ * 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
+ * XMAC_MP core; and should be changed only while reset is held low. Reset
+ * on Hard reset. */
+#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
+/* [RW 1] Interrupt mask register #0 read/write */
+#define MSTAT_REG_MSTAT_INT_MASK 0x7fc
+/* [R 1] Interrupt register #0 read */
+#define MSTAT_REG_MSTAT_INT_STS 0x7f0
+/* [RC 1] Interrupt register #0 read clear */
+#define MSTAT_REG_MSTAT_INT_STS_CLR 0x7f4
+/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
+ * Reads from this register will clear bits 31:0. */
+#define MSTAT_REG_RX_STAT_GR64_LO 0x200
+/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
+ * 31:0. Reads from this register will clear bits 31:0. */
+#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
+#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
+#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
+/* [R 1] Input enable for RX_BMAC0 IF */
+#define NIG_REG_BMAC0_IN_EN 0x100ac
+/* [R 1] output enable for TX_BMAC0 IF */
+#define NIG_REG_BMAC0_OUT_EN 0x100e0
+/* [R 1] output enable for TX BMAC pause port 0 IF */
+#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
+/* [R 1] output enable for RX_BMAC0_REGS IF */
+#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
+/* [RW 1] output enable for RX BRB1 port0 IF */
+#define NIG_REG_BRB0_OUT_EN 0x100f8
+/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
+#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
+/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
+#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
+/* [WB_W 90] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
+ * error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
+ * 72:73]-vnic_num; 89:74]-sideband_info */
+#define NIG_REG_DEBUG_PACKET_LB 0x10800
+/* [R 1] FIFO empty in DEBUG_FIFO in NIG_TX_DBG */
+#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418
+/* [R 1] FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT0 */
+#define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420
+/* [R 1] FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT1 */
+#define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862c
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638
+/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
+ * packets from PBFare not forwarded to the MAC and just deleted from FIFO.
+ * First packet may be deleted from the middle. And last packet will be
+ * always deleted till the end. */
+#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
+/* [R 1] Output enable to EMAC0 */
+#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
+/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
+ * to emac for port0; other way to bmac for port0 */
+#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
+/* [R 1] FIFO empty in MNG_FIFO in NIG_TX_PORT0 */
+#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460
+/* [R 1] FIFO empty in MNG_FIFO in NIG_TX_PORT1 */
+#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474
+/* [RW 1] Input enable for TX UMP management packet port0 IF */
+#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
+/* [R 1] Input enable for RX_EMAC0 IF */
+#define NIG_REG_EMAC0_IN_EN 0x100a4
+/* [R 1] output enable for TX EMAC pause port 0 IF */
+#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
+/* [R 1] status from emac0. This bit is set when MDINT from either the
+ * EXT_MDINT pin or from the Copper PHY is driven low. This condition must
+ * be cleared in the attached PHY device that is driving the MINT pin. */
+#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
+/* [R 48] This address space contains BMAC0 registers. The BMAC registers
+ * are described in appendix A. In order to access the BMAC0 registers; the
+ * base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
+ * added to each BMAC register offset */
+#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
+/* [R 48] This address space contains BMAC1 registers. The BMAC registers
+ * are described in appendix A. In order to access the BMAC0 registers; the
+ * base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
+ * added to each BMAC register offset */
+#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
+/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
+/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
+ * packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
+#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
+/* [R 1] FIFO empty in EOP descriptor FIFO of port 0 in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ec
+/* [R 1] FIFO empty in EOP descriptor FIFO of port 1 in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8
+/* [R 1] FIFO empty in PBF_DELAY_lb_FIFO in NIG_RX_lb */
+#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508
+/* [R 1] FIFO empty in dscr_fifo in NIG_RX_RMP block */
+#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530
+/* [R 1] FIFO empty in dscr_fifo in NIG_RX_RMP block */
+#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538
+/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
+ * logic for interrupts must be used. Enable per bit of interrupt of
+ * ~latch_status.latch_status */
+#define NIG_REG_LATCH_BC_0 0x16210
+/* [RW 27] Latch for each interrupt from Unicore.b[0]
+ * status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
+ * b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
+ * b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
+ * b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
+ * b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
+ * b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
+ * b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
+ * b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
+ * b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
+ * b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
+ * b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
+ * b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
+#define NIG_REG_LATCH_STATUS_0 0x18000
+/* [RW 1] led 10g for port 0 */
+#define NIG_REG_LED_10G_P0 0x10320
+/* [RW 1] Port0: This bit is set to enable the use of the
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
+ * defined below. If this bit is cleared; then the blink rate will be about
+ * 8Hz. */
+#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
+/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
+ * Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
+ * is reset to 0x080; giving a default blink period of approximately 8Hz. */
+#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
+/* [RW 1] Port0: If set along with the
+ * \
+ s_led_control_override_traffic_p0.led_control_override_traffic_p0
+ * bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
+ * bit; the Traffic LED will blink with the blink rate specified in
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+ * ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+ * fields. */
+#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
+/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
+ * Traffic LED will then be controlled via bit ~nig_registers_
+ * led_control_traffic_p0.led_control_traffic_p0 and bit
+ * ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
+#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
+/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
+ * turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
+ * set; the LED will blink with blink rate specified in
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+ * ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+ * fields. */
+#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
+/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
+ * 9-11PHY7; 12 MAC4; 13-15 PHY10; */
+#define NIG_REG_LED_MODE_P0 0x102f0
+/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
+ * tsdm enable; b2- usdm enable */
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
+/* [RW 1] SAFC enable for port0. This register may get 1 only when
+ * ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
+ * port */
+#define NIG_REG_LLFC_ENABLE_0 0x16208
+#define NIG_REG_LLFC_ENABLE_1 0x1620c
+/* [RW 16] classes are high-priority for port0 */
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
+/* [RW 16] classes are low-priority for port0 */
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
+/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
+#define NIG_REG_LLFC_OUT_EN_0 0x160c8
+#define NIG_REG_LLFC_OUT_EN_1 0x160cc
+#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
+#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
+#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
+#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
+/* [RW 2] Determine the classification participants. 0: no classification.1:
+ * classification upon VLAN id. 2: classification upon MAC address. 3:
+ * classification upon both VLAN id & MAC addr. */
+#define NIG_REG_LLH0_CLS_TYPE 0x16080
+#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
+#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
+/* [RW 16] destination TCP address 1. The LLH will look for this address in
+ * all incoming packets. */
+#define NIG_REG_LLH0_DEST_TCP_0 0x10220
+/* [RW 16] destination UDP address 1 The LLH will look for this address in
+ * all incoming packets. */
+#define NIG_REG_LLH0_DEST_UDP_0 0x10214
+/* [R 1] FIFO empty in LLH port0 */
+#define NIG_REG_LLH0_FIFO_EMPTY 0x10548
+#define NIG_REG_LLH0_FUNC_EN 0x160fc
+#define NIG_REG_LLH0_FUNC_MEM 0x16180
+#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
+#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
+/* [RW 1] Determine the IP version to look for in
+ * ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
+#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
+/* [RW 1] t bit for llh0 */
+#define NIG_REG_LLH0_T_BIT 0x10074
+/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
+#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
+#define NIG_REG_LLH0_XCM_MASK 0x10130
+#define NIG_REG_LLH1_BRB1_DRV_MASK_MF 0x1604c
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
+/* [RW 2] Determine the classification participants. 0: no classification.1:
+ * classification upon VLAN id. 2: classification upon MAC address. 3:
+ * classification upon both VLAN id & MAC addr. */
+#define NIG_REG_LLH1_CLS_TYPE 0x16084
+/* [R 1] FIFO empty in LLH port1 */
+#define NIG_REG_LLH1_FIFO_EMPTY 0x10558
+#define NIG_REG_LLH1_FUNC_EN 0x16104
+#define NIG_REG_LLH1_FUNC_MEM 0x161c0
+#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
+#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
+/* [RW 1] When this bit is set; the LLH will classify the packet before
+ * sending it to the BRB or calculating WoL on it. This bit controls port 1
+ * only. The legacy llh_multi_function_mode bit controls port 0. */
+#define NIG_REG_LLH1_MF_MODE 0x18614
+#define NIG_REG_LLH1_XCM_MASK 0x10134
+/* [RW 1] When this bit is set; the LLH will expect all packets to be with
+ * outer VLAN. This is not applicable to E2. */
+#define NIG_REG_LLH_E1HOV_MODE 0x160d8
+/* [RW 16] Outer VLAN type identifier for multi-function mode. In non
+ * multi-function mode; it will hold the inner VLAN type. Typically 0x8100. */
+#define NIG_REG_LLH_E1HOV_TYPE_1 0x16028
+/* [RW 1] When this bit is set; the LLH will classify the packet before
+ * sending it to the BRB or calculating WoL on it. This bit is applicable to
+ * both ports 0 and 1 for E2. This bit only controls port 0 in E3. */
+#define NIG_REG_LLH_MF_MODE 0x16024
+#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
+#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
+/* [R 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
+#define NIG_REG_NIG_EMAC0_EN 0x1003c
+/* [R 1] Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0
+ * to strip the CRC from the ingress packets. */
+#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
+/* [RW 32] Interrupt mask register #0 read/write */
+#define NIG_REG_NIG_INT_MASK_0 0x103bc
+#define NIG_REG_NIG_INT_MASK_1 0x103cc
+/* [R 32] Interrupt register #0 read */
+#define NIG_REG_NIG_INT_STS_0 0x103b0
+#define NIG_REG_NIG_INT_STS_1 0x103c0
+/* [RC 32] Interrupt register #0 read clear */
+#define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
+#define NIG_REG_NIG_INT_STS_CLR_1 0x103c4
+/* [R 32] Legacy E1 and E1H location for parity error mask register. */
+#define NIG_REG_NIG_PRTY_MASK 0x103dc
+/* [RW 32] Parity mask register #0 read/write */
+#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
+#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
+/* [R 32] Legacy E1 and E1H location for parity error status register. */
+#define NIG_REG_NIG_PRTY_STS 0x103d0
+/* [R 32] Parity register #0 read */
+#define NIG_REG_NIG_PRTY_STS_0 0x183bc
+#define NIG_REG_NIG_PRTY_STS_1 0x183cc
+/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
+#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
+/* [RC 32] Parity register #0 read clear */
+#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
+#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
+/* [R 1] Indication that HBUF descriptor FIFO is empty. */
+#define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header. */
+#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
+/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
+ * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
+ * disabled when this bit is set. */
+#define NIG_REG_P0_HWPFC_ENABLE 0x18078
+#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
+/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Writing a 1 to bit 16
+ * will clear the buffer. */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the lower 32 bits of timestamp value. */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the upper 32 bits of timestamp value. */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters. */
+#define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
+ * packets only and require that the packet is IPv4 for the rules to match.
+ * Note that rules 4-7 are for IPv6 packets only and require that the packet
+ * is IPv6 for the rules to match. */
+#define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4
+/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
+#define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac
+/* [RW 1] Input enable for RX MAC interface. */
+#define NIG_REG_P0_MAC_IN_EN 0x185ac
+/* [RW 1] Output enable for TX MAC interface */
+#define NIG_REG_P0_MAC_OUT_EN 0x185b0
+/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
+#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
+/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
+ * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
+ * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
+ * priority field is extracted from the outer-most VLAN in receive packet.
+ * Only COS 0 and COS 1 are supported in E2. */
+#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
+/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
+ * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
+ * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
+ * frame format in timesync event detection on RX side. Bit 3 enables
+ * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
+ * detection on TX side. Bit 5 enables V2 frame format in timesync event
+ * detection on TX side. Note that for HW to detect PTP packet and extract
+ * data from the packet, at least one of the version bits of that traffic
+ * direction has to be enabled. */
+#define NIG_REG_P0_PTP_EN 0x18788
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
+ * priority is mapped to COS 0 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
+ * priority is mapped to COS 1 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
+ * priority is mapped to COS 2 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
+ * priority is mapped to COS 3 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
+ * priority is mapped to COS 4 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
+ * priority is mapped to COS 5 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
+/* [R 1] RX FIFO for receiving data from MAC is empty. */
+#define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570
+/* [R 1] TLLH FIFO is empty. */
+#define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308
+/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Bit 17 indicates that
+ * the sequence ID is valid and it is waiting for the TX timestamp value.
+ * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
+ * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer. */
+#define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the lower 32 bits of timestamp value. */
+#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the upper 32 bits of timestamp value. */
+#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters. */
+#define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. */
+#define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4
+/* [R 15] Specify which of the credit registers the client is to be mapped
+ * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
+ * clients that are not subject to WFQ credit blocking - their
+ * specifications here are not used. */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
+/* [RW 32] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients. */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
+/* [RW 4] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients. */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
+/* [RW 9] Specify whether the client competes directly in the strict
+ * priority arbiter. The bits are mapped according to client ID (client IDs
+ * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
+ * Default value is set to enable strict priorities for all clients. */
+#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
+/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
+ * bits are mapped according to client ID (client IDs are defined in
+ * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
+ * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
+ * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
+ * 0 for not using WFQ credit blocking. */
+#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
+/* [RW 32] Specify the upper bound that credit register 0 is allowed to
+ * reach. */
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
+/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
+ * when it is time to increment. */
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
+/* [RW 12] Specify the number of strict priority arbitration slots between
+ * two round-robin arbitration slots to avoid starvation. A value of 0 means
+ * no strict priority cycles - the strict priority with anti-starvation
+ * arbiter becomes a round-robin arbiter. */
+#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
+/* [R 15] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
+ * are for priority 0 client; bits [14:12] are for priority 4 client. The
+ * clients are assigned the following IDs: 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
+ * for management at priority 0; debug traffic at priorities 1 and 2; COS0
+ * traffic at priority 3; and COS1 traffic at priority 4. */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
+/* [RW 32] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter. */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
+/* [RW 4] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter. */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
+/* [R 1] TX FIFO for transmitting data to MAC is empty. */
+#define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578
+/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
+ * packets to BRB LB interface to forward the packet to the host. All
+ * packets from MCP are forwarded to the network when this bit is cleared -
+ * regardless of the configured destination in tx_mng_destination register.
+ * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
+ * for BRB LB interface is bypassed and PBF LB traffic is always selected to
+ * send to BRB LB. */
+#define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4
+/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
+ * forwarded to the host. */
+#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8
+/* [R 1] Indication that HBUF descriptor FIFO is empty. */
+#define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header. */
+#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
+/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
+ * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
+ * disabled when this bit is set. */
+#define NIG_REG_P1_HWPFC_ENABLE 0x181d0
+#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
+/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Writing a 1 to bit 16
+ * will clear the buffer. */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the lower 32 bits of timestamp value. */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the upper 32 bits of timestamp value. */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters. */
+#define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
+ * packets only and require that the packet is IPv4 for the rules to match.
+ * Note that rules 4-7 are for IPv6 packets only and require that the packet
+ * is IPv6 for the rules to match. */
+#define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc
+/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
+#define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4
+/* [RW 1] Input enable for RX MAC interface. */
+#define NIG_REG_P1_MAC_IN_EN 0x185c0
+/* [RW 1] Output enable for TX MAC interface */
+#define NIG_REG_P1_MAC_OUT_EN 0x185c4
+/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
+#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
+/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
+ * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
+ * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
+ * priority field is extracted from the outer-most VLAN in receive packet.
+ * Only COS 0 and COS 1 are supported in E2. */
+#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
+/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
+ * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
+ * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
+ * frame format in timesync event detection on RX side. Bit 3 enables
+ * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
+ * detection on TX side. Bit 5 enables V2 frame format in timesync event
+ * detection on TX side. Note that for HW to detect PTP packet and extract
+ * data from the packet, at least one of the version bits of that traffic
+ * direction has to be enabled. */
+#define NIG_REG_P1_PTP_EN 0x187b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
+ * priority is mapped to COS 0 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
+ * priority is mapped to COS 1 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
+ * priority is mapped to COS 2 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS. */
+#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
+/* [R 1] RX FIFO for receiving data from MAC is empty. */
+#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
+/* [R 1] TLLH FIFO is empty. */
+#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
+/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Bit 17 indicates that
+ * the sequence ID is valid and it is waiting for the TX timestamp value.
+ * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
+ * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer. */
+#define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the lower 32 bits of timestamp value. */
+#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the upper 32 bits of timestamp value. */
+#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters. */
+#define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. */
+#define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc
+/* [RW 32] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients. Note also that there are
+ * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
+ * credit registers 0-5 are valid. This register should be configured
+ * appropriately before enabling WFQ. */
+#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
+/* [RW 4] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients. Note also that there are
+ * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
+ * credit registers 0-5 are valid. This register should be configured
+ * appropriately before enabling WFQ. */
+#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
+/* [RW 9] Specify whether the client competes directly in the strict
+ * priority arbiter. The bits are mapped according to client ID (client IDs
+ * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
+ * Default value is set to enable strict priorities for all clients. */
+#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
+/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
+ * bits are mapped according to client ID (client IDs are defined in
+ * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
+ * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
+ * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
+ * 0 for not using WFQ credit blocking. */
+#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
+/* [RW 32] Specify the upper bound that credit register 0 is allowed to
+ * reach. */
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
+/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
+ * when it is time to increment. */
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
+/* [RW 12] Specify the number of strict priority arbitration slots between
+ * two round-robin arbitration slots to avoid starvation. A value of 0 means
+ * no strict priority cycles - the strict priority with anti-starvation
+ * arbiter becomes a round-robin arbiter. */
+#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
+/* [RW 32] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter. Note that this register
+ * is the same as the one for port 0, except that port 1 only has COS 0-2
+ * traffic. There is no traffic for COS 3-5 of port 1. */
+#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
+/* [RW 4] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter. Note that this register
+ * is the same as the one for port 0, except that port 1 only has COS 0-2
+ * traffic. There is no traffic for COS 3-5 of port 1. */
+#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
+/* [R 1] TX FIFO for transmitting data to MAC is empty. */
+#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
+/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
+ * packets to BRB LB interface to forward the packet to the host. All
+ * packets from MCP are forwarded to the network when this bit is cleared -
+ * regardless of the configured destination in tx_mng_destination register. */
+#define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8
+/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
+ * forwarded to the host. */
+#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
+/* [RW 1] Pause enable for port0. This register may get 1 only when
+ * ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
+ * port */
+#define NIG_REG_PAUSE_ENABLE_0 0x160c0
+#define NIG_REG_PAUSE_ENABLE_1 0x160c4
+/* [RW 1] Value of this register will be transmitted to port swap when
+ * ~nig_registers_strap_override.strap_override =1 */
+#define NIG_REG_PORT_SWAP 0x10394
+/* [RW 1] PPP enable for port0. This register may get 1 only when
+ * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
+ * same port */
+#define NIG_REG_PPP_ENABLE_0 0x160b0
+#define NIG_REG_PPP_ENABLE_1 0x160b4
+/* [RW 1] Input enable for RX parser request IF */
+#define NIG_REG_PRS_REQ_IN_EN 0x100b8
+/* [R 5] control to serdes - CL45 DEVAD */
+#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
+/* [R 1] control to serdes; 0 - clause 45; 1 - clause 22 */
+#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
+/* [R 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
+#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
+/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
+#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
+/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
+ * for port 0 COS0 */
+#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
+/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
+ * for port 0 COS0 */
+#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
+/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
+ * between 1024 and 1522 bytes for port0 */
+#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
+/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
+ * between 1523 bytes and above for port0 */
+#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
+/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
+ * for port 1 COS0 */
+#define NIG_REG_STAT1_BRB_DISCARD 0x10628
+/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
+ * between 1024 and 1522 bytes for port1 */
+#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
+/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
+ * between 1523 bytes and above for port1 */
+#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
+/* [WB_R 64] Rx statistics : User octets received for LP */
+#define NIG_REG_STAT2_BRB_OCTET 0x107e0
+#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
+/* [RW 1] port swap mux selection. If this register equal to 0 then port
+ * swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
+ * ort swap is equal to ~nig_registers_port_swap.port_swap */
+#define NIG_REG_STRAP_OVERRIDE 0x10398
+/* [WB 64] Addresses for TimeSync related registers in the timesync
+ * generator sub-module. */
+#define NIG_REG_TIMESYNC_GEN_REG 0x18800
+/* [RW 1] output enable for RX_XCM0 IF */
+#define NIG_REG_XCM0_OUT_EN 0x100f0
+/* [RW 1] output enable for RX_XCM1 IF */
+#define NIG_REG_XCM1_OUT_EN 0x100f4
+/* [R 1] control to xgxs - remote PHY in-band MDIO */
+#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
+/* [R 5] control to xgxs - CL45 DEVAD */
+#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
+/* [R 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
+#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
+/* [R 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
+#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
+/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
+#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
+/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
+#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
+/* [R 2] selection for XGXS lane of port 0 in NIG_MUX block */
+#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
+/* [R 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
+#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
+/* [RW 1] Interrupt mask register #0 read/write */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_MASK 0xcc
+/* [R 1] Interrupt register #0 read */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS 0xc0
+/* [RC 1] Interrupt register #0 read clear */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS_CLR 0xc4
+/* [R 31] Removed for E3 B0 -The upper bound of the weight of COS0 in the
+ * ETS command arbiter. */
+#define PBF_REG_COS0_UPPER_BOUND 0x15c05c
+/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
+ * of port 0. */
+#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
+/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
+ * of port 1. */
+#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
+/* [R 31] Removed for E3 B0 - The weight of COS0 in the ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT 0x15c054
+/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
+/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
+/* [R 31] Removed for E3 B0 -The upper bound of the weight of COS1 in the
+ * ETS command arbiter. */
+#define PBF_REG_COS1_UPPER_BOUND 0x15c060
+/* [R 31] Removed for E3 B0 - The weight of COS1 in the ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT 0x15c058
+/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
+/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
+/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
+#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
+/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
+#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
+/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
+#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
+/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
+#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
+/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
+#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
+/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_CREDIT_LB_Q 0x140338
+/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_CREDIT_Q0 0x14033c
+/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_CREDIT_Q1 0x140340
+/* [R 11] Current credit for queue 2 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_CREDIT_Q2 0x140344
+/* [R 11] Current credit for queue 3 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_CREDIT_Q3 0x140348
+/* [R 11] Current credit for queue 4 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_CREDIT_Q4 0x14034c
+/* [R 11] Current credit for queue 5 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_CREDIT_Q5 0x140350
+/* [R 1] Removed for E3 B0 - Disable processing further tasks from port 0
+ * (after ending the current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
+/* [R 1] Removed for E3 B0 - Disable processing further tasks from port 1
+ * (after ending the current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bc
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1cc
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0
+#define PBF_REG_DISABLE_PF 0x1402e8
+#define PBF_REG_DISABLE_VF 0x1402ec
+/* [RW 18] For port 0: For each client that is subject to WFQ (the
+ * corresponding bit is 1); indicates to which of the credit registers this
+ * client is mapped. For clients which are not credit blocked; their mapping
+ * is dont care. */
+#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
+/* [RW 9] For port 1: For each client that is subject to WFQ (the
+ * corresponding bit is 1); indicates to which of the credit registers this
+ * client is mapped. For clients which are not credit blocked; their mapping
+ * is dont care. */
+#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
+/* [RW 6] For port 0: Bit per client to indicate if the client competes in
+ * the strict priority arbiter directly (corresponding bit = 1); or first
+ * goes to the RR arbiter (corresponding bit = 0); and then competes in the
+ * lowest priority in the strict-priority arbiter. */
+#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
+/* [RW 3] For port 1: Bit per client to indicate if the client competes in
+ * the strict priority arbiter directly (corresponding bit = 1); or first
+ * goes to the RR arbiter (corresponding bit = 0); and then competes in the
+ * lowest priority in the strict-priority arbiter. */
+#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
+/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
+ * WFQ credit blocking (corresponding bit = 1). */
+#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
+/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
+ * WFQ credit blocking (corresponding bit = 1). */
+#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
+/* [RW 16] For port 0: The number of strict priority arbitration slots
+ * between 2 RR arbitration slots. A value of 0 means no strict priority
+ * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
+ * arbiter. */
+#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
+/* [RW 16] For port 1: The number of strict priority arbitration slots
+ * between 2 RR arbitration slots. A value of 0 means no strict priority
+ * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
+ * arbiter. */
+#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
+/* [RW 18] For port 0: Indicates which client is connected to each priority
+ * in the strict-priority arbiter. Priority 0 is the highest priority, and
+ * priority 5 is the lowest; to which the RR output is connected to (this is
+ * not configurable). */
+#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
+/* [RW 9] For port 1: Indicates which client is connected to each priority
+ * in the strict-priority arbiter. Priority 0 is the highest priority, and
+ * priority 5 is the lowest; to which the RR output is connected to (this is
+ * not configurable). */
+#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
+/* [R 1] Removed for E3 B0 - Indicates that ETS is performed between the
+ * COSes in the command arbiter. If reset strict priority w/ anti-starvation
+ * will be performed w/o WFQ. */
+#define PBF_REG_ETS_ENABLED 0x15c050
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header. */
+#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
+#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
+/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
+ * priority in the command arbiter. */
+#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
+/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_INIT_CRD_LB_Q 0x15c248
+/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_INIT_CRD_Q0 0x15c230
+/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_INIT_CRD_Q1 0x15c234
+/* [RW 11] Initial credit for queue 2 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_INIT_CRD_Q2 0x15c238
+/* [RW 11] Initial credit for queue 3 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_INIT_CRD_Q3 0x15c23c
+/* [RW 11] Initial credit for queue 4 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_INIT_CRD_Q4 0x15c240
+/* [RW 11] Initial credit for queue 5 in the tx port buffers in 16 byte
+ * lines. */
+#define PBF_REG_INIT_CRD_Q5 0x15c244
+/* [R 1] Removed for E3 B0 - Init bit for port 0. When set the initial
+ * credit of port 0 is copied to the credit register. Should be set and then
+ * reset after the configuration of the port has ended. */
+#define PBF_REG_INIT_P0 0x140004
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * the LB queue. Reset upon init. */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * queue 0. Reset upon init. */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * queue 1. Reset upon init. */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
+/* [RW 1] Enable for mac interface 0. */
+#define PBF_REG_MAC_IF0_ENABLE 0x140030
+/* [RW 6] Bit-map indicating which headers must appear in the packet */
+#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
+/* [R 16] Removed for E3 B0 - The number of strict priority arbitration
+ * slots between 2 RR arbitration slots. A value of 0 means no strict
+ * priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a
+ * RR arbiter. */
+#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
+/* [R 11] Removed for E3 B0 - Port 0 threshold used by arbiter in 16 byte
+ * lines used when pause not suppoterd. */
+#define PBF_REG_P0_ARB_THRSH 0x1400e4
+/* [R 11] Removed for E3 B0 - Current credit for port 0 in the tx port
+ * buffers in 16 byte lines. */
+#define PBF_REG_P0_CREDIT 0x140200
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines. */
+#define PBF_REG_P0_INIT_CRD 0x1400d0
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 0. Reset upon init. */
+#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
+/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
+#define PBF_REG_P0_PAUSE_ENABLE 0x140014
+/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
+#define PBF_REG_P0_TASK_CNT 0x140204
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 0. Reset upon init. */
+#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
+#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
+/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
+ * buffers in 16 byte lines. */
+#define PBF_REG_P1_CREDIT 0x140208
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines. */
+#define PBF_REG_P1_INIT_CRD 0x1400d4
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 1. Reset upon init. */
+#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
+/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
+#define PBF_REG_P1_TASK_CNT 0x14020c
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 1. Reset upon init. */
+#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
+#define PBF_REG_P1_TQ_OCCUPANCY 0x140300
+/* [R 11] Removed for E3 B0 - Current credit for port 4 in the tx port
+ * buffers in 16 byte lines. */
+#define PBF_REG_P4_CREDIT 0x140210
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines. */
+#define PBF_REG_P4_INIT_CRD 0x1400e0
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 4. Reset upon init. */
+#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
+/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
+#define PBF_REG_P4_TASK_CNT 0x140214
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 4. Reset upon init. */
+#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
+#define PBF_REG_P4_TQ_OCCUPANCY 0x140304
+/* [RW 7] Interrupt mask register #0 read/write */
+#define PBF_REG_PBF_INT_MASK 0x1401d4
+/* [R 7] Interrupt register #0 read */
+#define PBF_REG_PBF_INT_STS 0x1401c8
+/* [RC 7] Interrupt register #0 read clear */
+#define PBF_REG_PBF_INT_STS_CLR 0x1401cc
+/* [RW 28] Parity mask register #0 read/write */
+#define PBF_REG_PBF_PRTY_MASK 0x1401e4
+/* [R 28] Parity register #0 read */
+#define PBF_REG_PBF_PRTY_STS 0x1401d8
+/* [RC 28] Parity register #0 read clear */
+#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
+/* [RW 16] The Ethernet type value for L2 tag 0 */
+#define PBF_REG_TAG_ETHERTYPE_0 0x15c090
+/* [RW 4] The length of the info field for L2 tag 0. The length is between
+ * 2B and 14B; in 2B granularity */
+#define PBF_REG_TAG_LEN_0 0x15c09c
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_LB_Q 0x140370
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q0 0x140374
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q1 0x140378
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q2 0x14037c
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q3 0x140380
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q4 0x140384
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q5 0x140388
+/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
+ * queue. Reset upon init. */
+#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
+/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
+ * queue 0. Reset upon init. */
+#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
+/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
+ * Reset upon init. */
+#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
+/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
+ * queue. */
+#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
+/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
+#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
+/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
+#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
+/* [RW 16] One of 8 values that should be compared to type in Ethernet
+ * parsing. If there is a match; the field after Ethernet is the first VLAN.
+ * Reset value is 0x8100 which is the standard VLAN type. Note that when
+ * checking second VLAN; type is compared only to 0x8100. */
+#define PBF_REG_VLAN_TYPE_0 0x15c06c
+/* [RW 2] Interrupt mask register #0 read/write */
+#define PB_REG_PB_INT_MASK 0x28
+/* [R 2] Interrupt register #0 read */
+#define PB_REG_PB_INT_STS 0x1c
+/* [RC 2] Interrupt register #0 read clear */
+#define PB_REG_PB_INT_STS_CLR 0x20
+/* [RW 4] Parity mask register #0 read/write */
+#define PB_REG_PB_PRTY_MASK 0x38
+/* [R 4] Parity register #0 read */
+#define PB_REG_PB_PRTY_STS 0x2c
+/* [RC 4] Parity register #0 read clear */
+#define PB_REG_PB_PRTY_STS_CLR 0x30
+#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
+/* [R 8] Config space A attention dirty bits. Each bit indicates that the
+ * corresponding PF generates config space A attention. Set by PXP. Reset by
+ * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
+ * from both paths. */
+#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
+/* [R 8] Config space B attention dirty bits. Each bit indicates that the
+ * corresponding PF generates config space B attention. Set by PXP. Reset by
+ * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
+ * from both paths. */
+#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
+/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
+ * that the FLR register of the corresponding PF was set. Set by PXP. Reset
+ * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
+ * from both paths. */
+#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
+/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
+ * to a bit in this register in order to clear the corresponding bit in
+ * flr_request_pf_7_0 register. Note: register contains bits from both
+ * paths. */
+#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
+/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
+#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
+/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
+#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
+/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
+#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
+/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
+#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
+/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
+ * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
+ * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
+ * arrived with a correctable error. Bit 3 - Configuration RW arrived with
+ * an uncorrectable error. Bit 4 - Completion with Configuration Request
+ * Retry Status. Bit 5 - Expansion ROM access received with a write request.
+ * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
+ * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
+ * and pcie_rx_last not asserted. */
+#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
+/* [W 7] Writing 1 to each bit in this register clears a corresponding error
+ * details register and enables logging new error details. Bit 0 - clears
+ * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears
+ * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS
+ * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32
+ * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -
+ * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears
+ * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6
+ * - clears TCPL_IN_TWO_RCBS_DETAILS. */
+#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c
+/* [RW 11] Interrupt mask register #0 read/write */
+#define PGLUE_B_REG_PGLUE_B_INT_MASK 0x92a4
+/* [R 11] Interrupt register #0 read */
+#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
+/* [RC 11] Interrupt register #0 read clear */
+#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
+/* [RW 2] Parity mask register #0 read/write */
+#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
+/* [R 2] Parity register #0 read */
+#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
+/* [RC 2] Parity register #0 read clear */
+#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
+/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
+ * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
+ * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
+ * completer abort. 3 - Illegal value for this field. [12] valid - indicates
+ * if there was a completion error since the last time this register was
+ * cleared. */
+#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
+/* [R 18] Details of first ATS Translation Completion request received with
+ * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
+ * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
+ * unsupported request. 2 - completer abort. 3 - Illegal value for this
+ * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
+ * completion error since the last time this register was cleared. */
+#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
+/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
+ * a bit in this register in order to clear the corresponding bit in
+ * shadow_bme_pf_7_0 register. MCP should never use this unless a
+ * work-around is needed. Note: register contains bits from both paths. */
+#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
+/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
+ * VF enable register of the corresponding PF is written to 0 and was
+ * previously 1. Set by PXP. Reset by MCP writing 1 to
+ * sr_iov_disabled_request_clr. Note: register contains bits from both
+ * paths. */
+#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
+/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
+ * completion did not return yet. 1 - tag is unused. Same functionality as
+ * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
+#define PGLUE_B_REG_TAGS_63_32 0x9244
+/* [R 32] Address [31:0] of first read request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
+/* [R 32] Address [63:32] of first read request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
+/* [R 31] Details of first read request not submitted due to error. [4:0]
+ * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
+ * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
+ * VFID. */
+#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
+/* [R 26] Details of first read request not submitted due to error. [15:0]
+ * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
+ * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
+ * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
+ * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
+ * indicates if there was a request not submitted due to error since the
+ * last time this register was cleared. */
+#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
+/* [R 32] Address [31:0] of first write request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
+/* [R 32] Address [63:32] of first write request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
+/* [R 31] Details of first write request not submitted due to error. [4:0]
+ * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
+ * - VFID. */
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
+/* [R 26] Details of first write request not submitted due to error. [15:0]
+ * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
+ * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
+ * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
+ * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
+ * indicates if there was a request not submitted due to error since the
+ * last time this register was cleared. */
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
+/* [R 26] Details of first target VF request accessing VF GRC space that
+ * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
+ * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
+ * request accessing VF GRC space that failed permission check since the
+ * last time this register was cleared. Permission checks are: function
+ * permission; R/W permission; address range permission. */
+#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
+/* [R 31] Details of first target VF request with length violation (too many
+ * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
+ * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
+ * valid - indicates if there was a request with length violation since the
+ * last time this register was cleared. Length violations: length of more
+ * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
+ * length is more than 1 DW. */
+#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
+/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
+ * that there was a completion with uncorrectable error for the
+ * corresponding PF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_pf_7_0_clr. */
+#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
+/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
+ * to a bit in this register in order to clear the corresponding bit in
+ * flr_request_pf_7_0 register. */
+#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
+/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_127_96_clr. */
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
+/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
+ * writes 1 to a bit in this register in order to clear the corresponding
+ * bit in was_error_vf_127_96 register. */
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
+/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_31_0_clr. */
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
+/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_31_0 register. */
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
+/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_63_32_clr. */
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
+/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_63_32 register. */
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
+/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_95_64_clr. */
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
+/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_95_64 register. */
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
+#define PRS_REG_A_PRSU_20 0x40134
+/* [R 8] debug only: CFC load request current credit. Transaction based. */
+#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
+/* [R 8] debug only: CFC search request current credit. Transaction based. */
+#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
+/* [RW 6] The initial credit for the search message to the CFC interface.
+ * Credit is transaction based. */
+#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
+/* [RW 24] CID for port 0 if no match */
+#define PRS_REG_CID_PORT_0 0x400fc
+/* [RW 1] Indicates if in outer vlan mode. 0=non-outer-vlan mode; 1=outer
+ * vlan mode. */
+#define PRS_REG_E1HOV_MODE 0x401c8
+/* [R 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header. */
+#define PRS_REG_HDRS_AFTER_BASIC 0x40238
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header for port 0 packets. */
+#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
+#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
+/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
+#define PRS_REG_HDRS_AFTER_TAG_0 0x40248
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
+ * port 0 packets */
+#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
+#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
+/* [R 6] Bit-map indicating which headers must appear in the packet */
+#define PRS_REG_MUST_HAVE_HDRS 0x40254
+/* [RW 6] Bit-map indicating which headers must appear in the packet for
+ * port 0 packets */
+#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
+#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
+#define PRS_REG_NIC_MODE 0x40138
+/* [ST 24] The number of input packets */
+#define PRS_REG_NUM_OF_PACKETS 0x40124
+/* [R 2] debug only: Number of pending requests for CAC on port 0. */
+#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
+/* [R 2] debug only: Number of pending requests for header parsing. */
+#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
+/* [RW 1] Interrupt mask register #0 read/write */
+#define PRS_REG_PRS_INT_MASK 0x40194
+/* [R 1] Interrupt register #0 read */
+#define PRS_REG_PRS_INT_STS 0x40188
+/* [RC 1] Interrupt register #0 read clear */
+#define PRS_REG_PRS_INT_STS_CLR 0x4018c
+/* [RW 8] Parity mask register #0 read/write */
+#define PRS_REG_PRS_PRTY_MASK 0x401a4
+/* [R 8] Parity register #0 read */
+#define PRS_REG_PRS_PRTY_STS 0x40198
+/* [RC 8] Parity register #0 read clear */
+#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
+/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
+ * serail number was released by SDM but cannot be used because a previous
+ * serial number was not released. */
+#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
+/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
+ * serail number was released by SDM but cannot be used because a previous
+ * serial number was not released. */
+#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
+/* [R 4] debug only: SRC current credit. Transaction based. */
+#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
+/* [RW 16] The Ethernet type value for L2 tag 0 */
+#define PRS_REG_TAG_ETHERTYPE_0 0x401d4
+/* [RW 4] The length of the info field for L2 tag 0. The length is between
+ * 2B and 14B; in 2B granularity */
+#define PRS_REG_TAG_LEN_0 0x4022c
+/* [R 8] debug only: TCM current credit. Cycle based. */
+#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
+/* [R 8] debug only: TSDM current credit. Transaction based. */
+#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
+/* [RW 16] One of 8 values that should be compared to type in Ethernet
+ * parsing. If there is a match; the field after Ethernet is the first VLAN.
+ * Reset value is 0x8100 which is the standard VLAN type. Note that when
+ * checking second VLAN; type is compared only to 0x8100. */
+#define PRS_REG_VLAN_TYPE_0 0x401a8
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
+#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
+#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
+/* [R 7] Debug only: Number of used entries in the data FIFO */
+#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
+/* [R 7] Debug only: Number of used entries in the header FIFO */
+#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
+#define PXP2_REG_PGL_ADDR_88_F0 0x120534
+/* [R 32] GRC address for configuration access to PCIE config address 0x88.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register */
+#define PXP2_REG_PGL_ADDR_88_F1 0x120544
+#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
+/* [R 32] GRC address for configuration access to PCIE config address 0x8c.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register */
+#define PXP2_REG_PGL_ADDR_8C_F1 0x120548
+#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
+/* [R 32] GRC address for configuration access to PCIE config address 0x90.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register */
+#define PXP2_REG_PGL_ADDR_90_F1 0x12054c
+#define PXP2_REG_PGL_ADDR_94_F0 0x120540
+/* [R 32] GRC address for configuration access to PCIE config address 0x94.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register */
+#define PXP2_REG_PGL_ADDR_94_F1 0x120550
+/* [RW 32] third dword data of expansion rom request. this register is
+ * special. reading from it provides a vector outstanding read requests. if
+ * a bit is zero it means that a read request on the corresponding tag did
+ * not finish yet (not all completions have arrived for it) */
+#define PXP2_REG_PGL_EXP_ROM2 0x120808
+/* [RW 16] this field allows one function to pretend being another function
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated. Bits [15] - force. Bits [14] - path
+ * ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits
+ * [2:0] - PFID. */
+#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
+/* [RW 16] this field allows one function to pretend being another function
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated. Bits [15] - force. Bits [14] - path
+ * ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits
+ * [2:0] - PFID. */
+#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
+/* [R 1] this bit indicates that a read request was blocked because of
+ * bus_master_en was deasserted */
+#define PXP2_REG_PGL_READ_BLOCKED 0x120568
+#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
+/* [R 21] debug only */
+#define PXP2_REG_PGL_TXW_CDTS 0x12052c
+/* [R 1] this bit indicates that a write request was blocked because of
+ * bus_master_en was deasserted */
+#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
+#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
+#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
+#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
+#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
+#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
+#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
+#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
+#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
+#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
+#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
+#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
+#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
+#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
+#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
+#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
+#define PXP2_REG_PSWRQ_BW_L28 0x120318
+#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
+#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
+#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
+#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
+#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
+#define PXP2_REG_PSWRQ_BW_RD 0x120324
+#define PXP2_REG_PSWRQ_BW_UB1 0x120238
+#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
+#define PXP2_REG_PSWRQ_BW_UB11 0x120260
+#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
+#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
+#define PXP2_REG_PSWRQ_BW_UB3 0x120240
+#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
+#define PXP2_REG_PSWRQ_BW_UB7 0x120250
+#define PXP2_REG_PSWRQ_BW_UB8 0x120254
+#define PXP2_REG_PSWRQ_BW_UB9 0x120258
+#define PXP2_REG_PSWRQ_BW_WR 0x120328
+#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
+#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
+#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
+#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
+#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define PXP2_REG_PXP2_INT_MASK_0 0x120578
+#define PXP2_REG_PXP2_INT_MASK_1 0x120614
+/* [R 32] Interrupt register #0 read */
+#define PXP2_REG_PXP2_INT_STS_0 0x12056c
+#define PXP2_REG_PXP2_INT_STS_1 0x120608
+/* [RC 32] Interrupt register #0 read clear */
+#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
+#define PXP2_REG_PXP2_INT_STS_CLR_1 0x12060c
+/* [RW 32] Parity mask register #0 read/write */
+#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
+#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
+/* [R 32] Parity register #0 read */
+#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
+#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
+/* [RC 32] Parity register #0 read clear */
+#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
+#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
+/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
+ * indication about backpressure) */
+#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
+/* [R 8] Debug only: The blocks counter - number of unused block ids */
+#define PXP2_REG_RD_BLK_CNT 0x120418
+/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
+ * Must be bigger than 6. Normally should not be changed. */
+#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
+/* [RW 2] CDU byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
+/* [R 29] Details of first request with error on receive side: [15:0] - Echo
+ * ID. [28:16] - sub-request length plus start_offset_2_0 minus 1. */
+#define PXP2_REG_RD_CPL_ERR_DETAILS 0x120778
+/* [R 10] Details of first request with error on receive side: [4:0] - VQ
+ * ID. [8:5] - client ID. [9] - valid - indicates if there was a completion
+ * error since the last time this register was read. */
+#define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077c
+/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
+#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
+/* [R 1] PSWRD internal memories initialization is done */
+#define PXP2_REG_RD_INIT_DONE 0x120370
+/* [R 1] Debug only: Indication if delivery ports are idle */
+#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
+#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
+/* [RW 2] QM byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
+/* [RW 2] SRC byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
+/* [R 7] Debug only: The SR counter - number of unused sub request ids */
+#define PXP2_REG_RD_SR_CNT 0x120414
+/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
+ * be bigger than 1. Normally should not be changed. */
+#define PXP2_REG_RD_SR_NUM_CFG 0x120408
+/* [RW 1] Signals the PSWRD block to start initializing internal memories */
+#define PXP2_REG_RD_START_INIT 0x12036c
+/* [RW 2] TM byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
+/* [RW 10] Bandwidth addition to VQ0 write requests */
+#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
+/* [RW 10] Bandwidth addition to VQ12 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
+/* [RW 10] Bandwidth addition to VQ13 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
+/* [RW 10] Bandwidth addition to VQ14 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
+/* [RW 10] Bandwidth addition to VQ15 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
+/* [RW 10] Bandwidth addition to VQ16 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
+/* [RW 10] Bandwidth addition to VQ17 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
+/* [RW 10] Bandwidth addition to VQ18 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
+/* [RW 10] Bandwidth addition to VQ19 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
+/* [RW 10] Bandwidth addition to VQ20 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
+/* [RW 10] Bandwidth addition to VQ22 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
+/* [RW 10] Bandwidth addition to VQ23 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
+/* [RW 10] Bandwidth addition to VQ24 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
+/* [RW 10] Bandwidth addition to VQ25 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
+/* [RW 10] Bandwidth addition to VQ26 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
+/* [RW 10] Bandwidth addition to VQ27 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
+/* [RW 10] Bandwidth addition to VQ4 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
+/* [RW 10] Bandwidth addition to VQ5 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
+/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
+#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
+/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
+#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
+/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
+#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
+/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
+#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
+/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
+#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
+/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
+#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
+/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
+#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
+/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
+#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
+/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
+#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
+/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
+#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
+/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
+#define PXP2_REG_RQ_BW_RD_L22 0x120300
+/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
+#define PXP2_REG_RQ_BW_RD_L23 0x120304
+/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
+#define PXP2_REG_RQ_BW_RD_L24 0x120308
+/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
+#define PXP2_REG_RQ_BW_RD_L25 0x12030c
+/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
+#define PXP2_REG_RQ_BW_RD_L26 0x120310
+/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
+#define PXP2_REG_RQ_BW_RD_L27 0x120314
+/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
+#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
+/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
+#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
+/* [RW 7] Bandwidth upper bound for VQ0 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
+/* [RW 7] Bandwidth upper bound for VQ12 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
+/* [RW 7] Bandwidth upper bound for VQ13 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
+/* [RW 7] Bandwidth upper bound for VQ14 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
+/* [RW 7] Bandwidth upper bound for VQ15 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
+/* [RW 7] Bandwidth upper bound for VQ16 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
+/* [RW 7] Bandwidth upper bound for VQ17 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
+/* [RW 7] Bandwidth upper bound for VQ18 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
+/* [RW 7] Bandwidth upper bound for VQ19 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
+/* [RW 7] Bandwidth upper bound for VQ20 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
+/* [RW 7] Bandwidth upper bound for VQ22 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
+/* [RW 7] Bandwidth upper bound for VQ23 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
+/* [RW 7] Bandwidth upper bound for VQ24 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
+/* [RW 7] Bandwidth upper bound for VQ25 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
+/* [RW 7] Bandwidth upper bound for VQ26 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
+/* [RW 7] Bandwidth upper bound for VQ27 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
+/* [RW 7] Bandwidth upper bound for VQ4 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
+/* [RW 7] Bandwidth upper bound for VQ5 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
+/* [RW 10] Bandwidth addition to VQ29 write requests */
+#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
+/* [RW 10] Bandwidth addition to VQ30 write requests */
+#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
+/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
+#define PXP2_REG_RQ_BW_WR_L29 0x12031c
+/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
+#define PXP2_REG_RQ_BW_WR_L30 0x120320
+/* [RW 7] Bandwidth upper bound for VQ29 */
+#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
+/* [RW 7] Bandwidth upper bound for VQ30 */
+#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
+/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
+#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
+/* [RW 2] Endian mode for cdu */
+#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
+#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
+#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
+/* [RW 4] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M */
+#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
+/* [R 1] 1' indicates that the requester has finished its internal
+ * configuration */
+#define PXP2_REG_RQ_CFG_DONE 0x1201b4
+/* [RW 2] Endian mode for debug */
+#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
+/* [RW 1] When '1'; requests will enter input buffers but wont get out
+ * towards the glue */
+#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
+/* [RW 4] Determines alignment of write SRs when a request is split into
+ * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
+ * aligned. 4 - 512B aligned. */
+#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
+/* [RW 4] Determines alignment of read SRs when a request is split into
+ * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
+ * aligned. 4 - 512B aligned. */
+#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
+/* [RW 1] when set the new alignment method (E2) will be applied; when reset
+ * the original alignment method (E1 E1H) will be applied */
+#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
+/* [R 32] Status signals in pswrq_garb module */
+#define PXP2_REG_RQ_GARB 0x120748
+/* [RW 2] Endian mode for hc */
+#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
+/* [WB 53] Onchip address table */
+#define PXP2_REG_RQ_ONCHIP_AT 0x122000
+/* [WB 53] Onchip address table - B0 */
+#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
+/* [RW 13] Pending read limiter threshold; in Dwords */
+#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
+/* [RW 2] Endian mode for qm */
+#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
+#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
+#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
+/* [RW 4] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M */
+#define PXP2_REG_RQ_QM_P_SIZE 0x120050
+/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
+#define PXP2_REG_RQ_RBC_DONE 0x1201b0
+/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
+ * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
+#define PXP2_REG_RQ_RD_MBS0 0x120160
+/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
+ * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
+#define PXP2_REG_RQ_RD_MBS1 0x120168
+/* [RW 2] Endian mode for src */
+#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
+#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
+#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
+/* [RW 4] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M */
+#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
+/* [RW 2] Endian mode for tm */
+#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
+#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
+#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
+/* [RW 4] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M */
+#define PXP2_REG_RQ_TM_P_SIZE 0x120034
+/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
+#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
+/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
+#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
+/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
+#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
+/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
+#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
+/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
+#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
+/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
+#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
+/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
+#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
+/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
+#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
+/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
+#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
+/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
+#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
+/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
+#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
+/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
+#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
+/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
+#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
+/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
+#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
+/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
+#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
+/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
+#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
+/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
+#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
+/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
+#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
+/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
+#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
+/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
+#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
+/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
+#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
+/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
+#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
+/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
+#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
+/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
+#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
+/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
+#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
+/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
+#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
+/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
+#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
+/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
+#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
+/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
+#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
+/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
+#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
+/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
+#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
+/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
+#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
+/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
+#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
+/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
+#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
+/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
+ * 001:256B; 010: 512B; */
+#define PXP2_REG_RQ_WR_MBS0 0x12015c
+/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
+ * 001:256B; 010: 512B; */
+#define PXP2_REG_RQ_WR_MBS1 0x120164
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_CDU_MPS 0x1205f0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_CSDM_MPS 0x1205d0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_DBG_MPS 0x1205e8
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_DMAE_MPS 0x1205ec
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_HC_MPS 0x1205c8
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_QM_MPS 0x1205dc
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_SRC_MPS 0x1205e4
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_TM_MPS 0x1205e0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_TSDM_MPS 0x1205d4
+/* [RW 9] a. When pxp2.wr_th_mode_usdmdp=0 (E1.5-65 mode) should be
+ * initialized to (MPS/32); b. When pxp2.wr_th_mode_usdmdp=1 (E1.5-90;
+ * enhanced mode) and pxp2.wr_usdmdp_outst_req is different than default (3)
+ * should be initialized to (pxp2.wr_usdmdp_outst_req x MPS/32); when
+ * pxp2.wr_usdmdp_outst_req is 3 the reset value is the correct
+ * configuration */
+#define PXP2_REG_WR_USDMDP_TH 0x120348
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_USDM_MPS 0x1205cc
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value. */
+#define PXP2_REG_WR_XSDM_MPS 0x1205d8
+/* [R 1] debug only: Indication if PSWHST arbiter is idle */
+#define PXP_REG_HST_ARB_IS_IDLE 0x103004
+/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
+ * this client is waiting for the arbiter. */
+#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
+/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
+ * block. Should be used for close the gates. */
+#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
+/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
+ * should update accoring to 'hst_discard_doorbells' register when the state
+ * machine is idle */
+#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
+/* [RW 1] When 1; new internal writes arriving to the block are discarded.
+ * Should be used for close the gates. */
+#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
+/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
+ * means this PSWHST is discarding inputs from this client. Each bit should
+ * update accoring to 'hst_discard_internal_writes' register when the state
+ * machine is idle. */
+#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
+/* [R 1] 1 - An incorrect access is logged. The valid bit is reset when the
+ * relevant interrupt register is read (PXP_REG_INT_STS_CLR_1) */
+#define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030cc
+/* [R 1] 1- permission violation data is logged. The valid bit is reset when
+ * the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1) */
+#define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0
+/* [R 15] The FID of the first access to a disabled VF; the format is
+ * [14:12] - pfid; [11:6] - vfid; [5] - vf_valid; [4:1] - client (0 USDM; 1
+ * CSDM; 2 XSDM; 3 TSDM; 4 HC; 5 GRC; 6 DQ; 7 RESERVED SPACE; 8 ATC); [0] -
+ * w_nr(0-read req; 1- write req). The data is written only when the valid
+ * bit is reset. and it is stays stable until it is reset by the read from
+ * interrupt_clr register */
+#define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b8
+/* [R 1] 1 - An error request is logged and wasn't handled yet. The valid
+ * bit is reset when the relevant interrupt register is read
+ * (PXP_REG_INT_STS_CLR_1) */
+#define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bc
+/* [RW 7] Indirect access to the permission table. The fields are : {Valid;
+ * VFID[5:0]} */
+#define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400
+/* [RW 32] Interrupt mask register #0 read/write */
+#define PXP_REG_PXP_INT_MASK_0 0x103074
+#define PXP_REG_PXP_INT_MASK_1 0x103084
+/* [R 32] Interrupt register #0 read */
+#define PXP_REG_PXP_INT_STS_0 0x103068
+#define PXP_REG_PXP_INT_STS_1 0x103078
+/* [RC 32] Interrupt register #0 read clear */
+#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
+#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
+/* [RW 27] Parity mask register #0 read/write */
+#define PXP_REG_PXP_PRTY_MASK 0x103094
+/* [R 27] Parity register #0 read */
+#define PXP_REG_PXP_PRTY_STS 0x103088
+/* [RC 27] Parity register #0 read clear */
+#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
+/* [RW 32] The base logical address (in bytes) of each physical queue. The
+ * index I represents the physical queue number. The 12 lsbs are ignore and
+ * considered zero so practically there are only 20 bits in this register;
+ * queues 63-0 */
+#define QM_REG_BASEADDR 0x168900
+/* [R 32] NOT USED */
+#define QM_REG_BASEADDR_EXT_A 0x16e100
+/* [R 18] The credit value for byte credit 0. The value is 2s complement
+ * value (i.e. msb is used for the sign). */
+#define QM_REG_BYTECRD0 0x16e6fc
+/* [R 18] The credit value for byte credit 1. The value is 2s complement
+ * value (i.e. msb is used for the sign). */
+#define QM_REG_BYTECRD1 0x16e700
+/* [R 18] The credit value for byte credit 2. The value is 2s complement
+ * value (i.e. msb is used for the sign). */
+#define QM_REG_BYTECRD2 0x16e704
+/* [R 18] The credit value for byte credit 3. The value is 2s complement
+ * value (i.e. msb is used for the sign). */
+#define QM_REG_BYTECRD3 0x16e7ac
+/* [R 18] The credit value for byte credit 4. The value is 2s complement
+ * value (i.e. msb is used for the sign). */
+#define QM_REG_BYTECRD4 0x16e7b0
+/* [R 18] The credit value for byte credit 5. The value is 2s complement
+ * value (i.e. msb is used for the sign). */
+#define QM_REG_BYTECRD5 0x16e7b4
+/* [R 18] The credit value for byte credit 6. The value is 2s complement
+ * value (i.e. msb is used for the sign). */
+#define QM_REG_BYTECRD6 0x16e7b8
+/* [R 32] NOT USED - removed for E3 B0 */
+#define QM_REG_BYTECRDCMDQ_0 0x16e6e8
+/* [RC 32] byte credit update error register; b2-b0: byte credit id (pbf
+ * error); b3 - reserved (zero filled); b6-b4: byte credit id (storm
+ * increment error); b7 - reserved (zero filled); b10-b8: byte credit id
+ * (storm decrement error); b11 - reserved (zero filled); b12: pbf error
+ * valid; b13: storm increment error valid; b14: storm decrement error
+ * valid; b15: reserved; b22-b16: byte credit warning (warning=decremented
+ * below zero). mask bit per voq counter; b31-b23: reserved; NOTE: VOQ id-s
+ * represent HW */
+#define QM_REG_BYTECRDERRREG 0x16e708
+/* [RW 17] The initial byte credit value for all counters */
+#define QM_REG_BYTECRDINITVAL 0x168238
+/* [RW 20] The number of connections divided by 16 which dictates the size
+ * of each queue which belongs to even function number. */
+#define QM_REG_CONNNUM_0 0x168020
+/* [R 6] Keep the fill level of the fifo from write client 4 */
+#define QM_REG_CQM_WRC_FIFOLVL 0x168018
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ0 */
+#define QM_REG_FWVOQ0TOHWVOQ 0x16e7bc
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ1 */
+#define QM_REG_FWVOQ1TOHWVOQ 0x16e7c0
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ2 */
+#define QM_REG_FWVOQ2TOHWVOQ 0x16e7c4
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ3 */
+#define QM_REG_FWVOQ3TOHWVOQ 0x16e7c8
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ4 */
+#define QM_REG_FWVOQ4TOHWVOQ 0x16e7cc
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ5 */
+#define QM_REG_FWVOQ5TOHWVOQ 0x16e7d0
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ6 */
+#define QM_REG_FWVOQ6TOHWVOQ 0x16e7d4
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ7 */
+#define QM_REG_FWVOQ7TOHWVOQ 0x16e7d8
+/* [RC 1] A flag to indicate that overflow error occurred in one of the
+ * queues. */
+#define QM_REG_OVFERROR 0x16805c
+/* [RC 6] the Q were the qverflow occurs */
+#define QM_REG_OVFQNUM 0x168058
+/* [R 16] Pause state for physical queues 15-0 */
+#define QM_REG_PAUSESTATE0 0x168410
+/* [R 16] Pause state for physical queues 31-16 */
+#define QM_REG_PAUSESTATE1 0x168414
+/* [R 16] Pause state for physical queues 47-32 */
+#define QM_REG_PAUSESTATE2 0x16e684
+/* [R 16] Pause state for physical queues 63-48 */
+#define QM_REG_PAUSESTATE3 0x16e688
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE4 0x16e68c
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE5 0x16e690
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE6 0x16e694
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE7 0x16e698
+#define QM_REG_PF_EN 0x16e70c
+/* [R 24] The number of tasks stored in the QM for the PF. only even
+ * functions are valid in E2 (odd I registers will be hard wired to 0) */
+#define QM_REG_PF_USG_CNT_0 0x16e040
+/* [R 16] NOT USED */
+#define QM_REG_PORT0BYTECRD 0x168300
+/* [R 16] NOT USED */
+#define QM_REG_PORT1BYTECRD 0x168304
+/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
+ * ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
+ * bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
+#define QM_REG_PTRTBL 0x168a00
+/* [R 54] NOT USED */
+#define QM_REG_PTRTBL_EXT_A 0x16e200
+/* [RW 14] Interrupt mask register #0 read/write */
+#define QM_REG_QM_INT_MASK 0x168444
+/* [R 14] Interrupt register #0 read */
+#define QM_REG_QM_INT_STS 0x168438
+/* [RC 14] Interrupt register #0 read clear */
+#define QM_REG_QM_INT_STS_CLR 0x16843c
+/* [RW 12] Parity mask register #0 read/write */
+#define QM_REG_QM_PRTY_MASK 0x168454
+/* [R 12] Parity register #0 read */
+#define QM_REG_QM_PRTY_STS 0x168448
+/* [RC 12] Parity register #0 read clear */
+#define QM_REG_QM_PRTY_STS_CLR 0x16844c
+/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
+#define QM_REG_QSTATUS_HIGH 0x16802c
+/* [R 32] NOT USED */
+#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
+/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
+#define QM_REG_QSTATUS_LOW 0x168028
+/* [R 32] NOT USED */
+#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
+/* [R 24] The number of tasks queued for each queue; queues 63-0 */
+#define QM_REG_QTASKCTR_0 0x168308
+/* [R 24] NOT USED */
+#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
+/* [RW 4] Queue tied to VOQ */
+#define QM_REG_QVOQIDX_0 0x1680f4
+/* [RW 1] Initialization bit command */
+#define QM_REG_SOFT_RESET 0x168428
+/* [R 6] Keep the fill level of the fifo from write client 3 */
+#define QM_REG_TQM_WRC_FIFOLVL 0x168010
+/* [R 6] Keep the fill level of the fifo from write client 2 */
+#define QM_REG_UQM_WRC_FIFOLVL 0x168008
+/* [RC 32] VOQ credit update error register; b3-b0: voq id (pbf error);
+ * b7-b4: voq id (storm increment error); b11-b8: voq id (storm decrement
+ * error); b12: pbf error valid; b13: storm increment error valid; b14:
+ * storm decrement error valid; b15: reserved; b27-b16: voq warning
+ * (warning=decremented below zero). mask bit per voq counter; b31-b28:
+ * reserved; NOTE: VOQ id-s represent HW VOQ id */
+#define QM_REG_VOQCRDERRREG 0x168408
+/* [R 17] The credit value for each VOQ. The value is 2s complement value
+ * (i.e. msb is used for the sign). */
+#define QM_REG_VOQCREDIT_0 0x1682d0
+#define QM_REG_VOQCREDIT_1 0x1682d4
+#define QM_REG_VOQCREDIT_2 0x1682d8
+#define QM_REG_VOQCREDIT_3 0x1682dc
+#define QM_REG_VOQCREDIT_4 0x1682e0
+#define QM_REG_VOQCREDIT_5 0x1682e4
+#define QM_REG_VOQCREDIT_6 0x1682e8
+/* [RW 16] The init and maximum credit for each VoQ */
+#define QM_REG_VOQINITCREDIT_0 0x168060
+#define QM_REG_VOQINITCREDIT_1 0x168064
+#define QM_REG_VOQINITCREDIT_2 0x168068
+#define QM_REG_VOQINITCREDIT_3 0x16806c
+#define QM_REG_VOQINITCREDIT_4 0x168070
+#define QM_REG_VOQINITCREDIT_5 0x168074
+#define QM_REG_VOQINITCREDIT_6 0x168078
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_0_LSB 0x168240
+/* [R 6] Keep the fill level of the fifo from write client 1 */
+#define QM_REG_XQM_WRC_FIFOLVL 0x168000
+/* [W 1] reset to parity interrupt */
+#define SEM_FAST_REG_PARITY_RST 0x18840
+/* [RW 1] Interrupt mask register #0 read/write */
+#define SEM_FAST_REG_SEM_FAST_INT_MASK 0x1fff0
+/* [R 1] Interrupt register #0 read */
+#define SEM_FAST_REG_SEM_FAST_INT_STS 0x1fffc
+/* [RC 1] Interrupt register #0 read clear */
+#define SEM_FAST_REG_SEM_FAST_INT_STS_CLR 0x1fff8
+/* [RW 1] Parity mask register #0 read/write */
+#define SEM_FAST_REG_SEM_FAST_PRTY_MASK 0x1ffe0
+/* [R 1] Parity register #0 read */
+#define SEM_FAST_REG_SEM_FAST_PRTY_STS 0x1ffec
+/* [RC 1] Parity register #0 read clear */
+#define SEM_FAST_REG_SEM_FAST_PRTY_STS_CLR 0x1ffe8
+#define SRC_REG_COUNTFREE0 0x40500
+#define SRC_REG_FIRSTFREE0 0x40510
+#define SRC_REG_KEYRSS0_0 0x40408
+#define SRC_REG_KEYRSS0_7 0x40424
+#define SRC_REG_KEYSEARCH_0 0x40458
+#define SRC_REG_KEYSEARCH_1 0x4045c
+#define SRC_REG_KEYSEARCH_2 0x40460
+#define SRC_REG_KEYSEARCH_3 0x40464
+#define SRC_REG_KEYSEARCH_4 0x40468
+#define SRC_REG_KEYSEARCH_5 0x4046c
+#define SRC_REG_KEYSEARCH_6 0x40470
+#define SRC_REG_KEYSEARCH_7 0x40474
+#define SRC_REG_KEYSEARCH_8 0x40478
+#define SRC_REG_KEYSEARCH_9 0x4047c
+#define SRC_REG_LASTFREE0 0x40530
+#define SRC_REG_NUMBER_HASH_BITS0 0x40400
+/* [RW 1] Reset internal state machines. */
+#define SRC_REG_SOFT_RST 0x4049c
+/* [RW 3] Interrupt mask register #0 read/write */
+#define SRC_REG_SRC_INT_MASK 0x404b8
+/* [R 3] Interrupt register #0 read */
+#define SRC_REG_SRC_INT_STS 0x404ac
+/* [RC 3] Interrupt register #0 read clear */
+#define SRC_REG_SRC_INT_STS_CLR 0x404b0
+/* [RW 3] Parity mask register #0 read/write */
+#define SRC_REG_SRC_PRTY_MASK 0x404c8
+/* [R 3] Parity register #0 read */
+#define SRC_REG_SRC_PRTY_STS 0x404bc
+/* [RC 3] Parity register #0 read clear */
+#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
+/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
+#define TCM_REG_CAM_OCCUP 0x5017c
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up. */
+#define TCM_REG_CFC_INIT_CRD 0x50204
+/* [RC 1] Message length mismatch (relative to last indication) at the In#9
+ * interface. */
+#define TCM_REG_CSEM_LENGTH_MIS 0x50174
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up. */
+#define TCM_REG_FIC0_INIT_CRD 0x5020c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up. */
+#define TCM_REG_FIC1_INIT_CRD 0x50210
+/* [RC 1] Message length mismatch (relative to last indication) at the In#7
+ * interface. */
+#define TCM_REG_PBF_LENGTH_MIS 0x5016c
+/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity. */
+#define TCM_REG_PRS_IFEN 0x50020
+/* [RC 1] Message length mismatch (relative to last indication) at the In#6
+ * interface. */
+#define TCM_REG_PRS_LENGTH_MIS 0x50168
+/* [RC 1] Message length mismatch (relative to last indication) at the STORM
+ * interface. */
+#define TCM_REG_STORM_LENGTH_MIS 0x50160
+/* [RW 11] Interrupt mask register #0 read/write */
+#define TCM_REG_TCM_INT_MASK 0x501dc
+/* [R 11] Interrupt register #0 read */
+#define TCM_REG_TCM_INT_STS 0x501d0
+/* [RC 11] Interrupt register #0 read clear */
+#define TCM_REG_TCM_INT_STS_CLR 0x501d4
+/* [RW 27] Parity mask register #0 read/write */
+#define TCM_REG_TCM_PRTY_MASK 0x501ec
+/* [R 27] Parity register #0 read */
+#define TCM_REG_TCM_PRTY_STS 0x501e0
+/* [RC 27] Parity register #0 read clear */
+#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up. */
+#define TCM_REG_TQM_INIT_CRD 0x5021c
+/* [RC 1] Message length mismatch (relative to last indication) at the SDM
+ * interface. */
+#define TCM_REG_TSDM_LENGTH_MIS 0x50164
+/* [RC 1] Message length mismatch (relative to last indication) at the In#8
+ * interface. */
+#define TCM_REG_USEM_LENGTH_MIS 0x50170
+/* [RW 21] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - length of the message; 15:6] - message
+ * pointer; 20:16] - next pointer. */
+#define TCM_REG_XX_DESCR_TABLE 0x50280
+#define TCM_REG_XX_DESCR_TABLE_SIZE 29
+/* [R 6] Use to read the value of XX protection Free counter. */
+#define TCM_REG_XX_FREE 0x50178
+#define TM_REG_EN_LINEAR0_TIMER 0x164014
+/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
+#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
+/* [ST 16] Linear0 Number of scans counter. */
+#define TM_REG_LIN0_NUM_SCANS 0x1640a0
+#define TM_REG_LIN0_SCAN_ON 0x1640d0
+/* [RW 24] Linear0 array scan timeout. */
+#define TM_REG_LIN0_SCAN_TIME 0x16403c
+#define TM_REG_LIN0_VNIC_UC 0x164128
+/* [RW 1] Interrupt mask register #0 read/write */
+#define TM_REG_TM_INT_MASK 0x1640fc
+/* [R 1] Interrupt register #0 read */
+#define TM_REG_TM_INT_STS 0x1640f0
+/* [RC 1] Interrupt register #0 read clear */
+#define TM_REG_TM_INT_STS_CLR 0x1640f4
+/* [RW 7] Parity mask register #0 read/write */
+#define TM_REG_TM_PRTY_MASK 0x16410c
+/* [R 7] Parity register #0 read */
+#define TM_REG_TM_PRTY_STS 0x164100
+/* [RC 7] Parity register #0 read clear */
+#define TM_REG_TM_PRTY_STS_CLR 0x164104
+#define TSDM_REG_ENABLE_IN1 0x42238
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
+#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
+/* [R 32] Interrupt register #0 read */
+#define TSDM_REG_TSDM_INT_STS_0 0x42290
+#define TSDM_REG_TSDM_INT_STS_1 0x422a0
+/* [RC 32] Interrupt register #0 read clear */
+#define TSDM_REG_TSDM_INT_STS_CLR_0 0x42294
+#define TSDM_REG_TSDM_INT_STS_CLR_1 0x422a4
+/* [RW 11] Parity mask register #0 read/write */
+#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
+/* [R 11] Parity register #0 read */
+#define TSDM_REG_TSDM_PRTY_STS 0x422b0
+/* [RC 11] Parity register #0 read clear */
+#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each
+ * SEM_FAST register offset. */
+#define TSEM_REG_FAST_MEMORY 0x1a0000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work */
+#define TSEM_REG_INT_TABLE 0x180400
+/* [WB 128] Debug only. Passive buffer memory */
+#define TSEM_REG_PASSIVE_BUFFER 0x181000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define TSEM_REG_PRAM 0x1c0000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define TSEM_REG_TSEM_INT_MASK_0 0x180100
+#define TSEM_REG_TSEM_INT_MASK_1 0x180110
+/* [R 32] Interrupt register #0 read */
+#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
+#define TSEM_REG_TSEM_INT_STS_1 0x180104
+/* [RC 32] Interrupt register #0 read clear */
+#define TSEM_REG_TSEM_INT_STS_CLR_0 0x1800f8
+#define TSEM_REG_TSEM_INT_STS_CLR_1 0x180108
+/* [RW 32] Parity mask register #0 read/write */
+#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
+#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
+/* [R 32] Parity register #0 read */
+#define TSEM_REG_TSEM_PRTY_STS_0 0x180114
+#define TSEM_REG_TSEM_PRTY_STS_1 0x180124
+/* [RC 32] Parity register #0 read clear */
+#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
+#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
+#define TSEM_REG_VFPF_ERR_NUM 0x180380
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define UCM_REG_CAM_OCCUP 0xe0170
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up. */
+#define UCM_REG_CFC_INIT_CRD 0xe0204
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the csem interface is detected. */
+#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the dorq interface is detected. */
+#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up. */
+#define UCM_REG_FIC0_INIT_CRD 0xe020c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up. */
+#define UCM_REG_FIC1_INIT_CRD 0xe0210
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the STORM interface is detected. */
+#define UCM_REG_STORM_LENGTH_MIS 0xe0154
+/* [RW 4] Timers output initial credit. Max credit available - 15.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 4 at start-up. */
+#define UCM_REG_TM_INIT_CRD 0xe021c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the tsem interface is detected. */
+#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
+/* [RW 11] Interrupt mask register #0 read/write */
+#define UCM_REG_UCM_INT_MASK 0xe01d4
+/* [R 11] Interrupt register #0 read */
+#define UCM_REG_UCM_INT_STS 0xe01c8
+/* [RC 11] Interrupt register #0 read clear */
+#define UCM_REG_UCM_INT_STS_CLR 0xe01cc
+/* [RW 27] Parity mask register #0 read/write */
+#define UCM_REG_UCM_PRTY_MASK 0xe01e4
+/* [R 27] Parity register #0 read */
+#define UCM_REG_UCM_PRTY_STS 0xe01d8
+/* [RC 27] Parity register #0 read clear */
+#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up. */
+#define UCM_REG_UQM_INIT_CRD 0xe0220
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the SDM interface is detected. */
+#define UCM_REG_USDM_LENGTH_MIS 0xe0158
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the xsem interface isdetected. */
+#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
+/* [RW 20] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are:[5:0] - message length; 14:6] - message
+ * pointer; 19:15] - next pointer. */
+#define UCM_REG_XX_DESCR_TABLE 0xe0280
+#define UCM_REG_XX_DESCR_TABLE_SIZE 27
+/* [R 6] Use to read the XX protection Free counter. */
+#define UCM_REG_XX_FREE 0xe016c
+#define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10)
+#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)
+#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
+#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
+#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
+#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)
+#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
+#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
+#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
+#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
+#define UMAC_REG_COMMAND_CONFIG 0x8
+/* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE
+ * state from LPI state when it receives packet for transmission. The
+ * decrement unit is 1 micro-second. */
+#define UMAC_REG_EEE_WAKE_TIMER 0x6c
+/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
+ * to bit 17 of the MAC address etc. */
+#define UMAC_REG_MAC_ADDR0 0xc
+/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
+ * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */
+#define UMAC_REG_MAC_ADDR1 0x10
+/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
+ * logic to check frames. */
+#define UMAC_REG_MAXFR 0x14
+#define UMAC_REG_UMAC_EEE_CTRL 0x64
+#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3)
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
+/* [R 1] parser fifo empty in sdm_sync block */
+#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
+/* [RW 32] Interrupt mask register #0 read/write */
+#define USDM_REG_USDM_INT_MASK_0 0xc42a0
+#define USDM_REG_USDM_INT_MASK_1 0xc42b0
+/* [R 32] Interrupt register #0 read */
+#define USDM_REG_USDM_INT_STS_0 0xc4294
+#define USDM_REG_USDM_INT_STS_1 0xc42a4
+/* [RC 32] Interrupt register #0 read clear */
+#define USDM_REG_USDM_INT_STS_CLR_0 0xc4298
+#define USDM_REG_USDM_INT_STS_CLR_1 0xc42a8
+/* [RW 11] Parity mask register #0 read/write */
+#define USDM_REG_USDM_PRTY_MASK 0xc42c0
+/* [R 11] Parity register #0 read */
+#define USDM_REG_USDM_PRTY_STS 0xc42b4
+/* [RC 11] Parity register #0 read clear */
+#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each
+ * SEM_FAST register offset. */
+#define USEM_REG_FAST_MEMORY 0x320000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work */
+#define USEM_REG_INT_TABLE 0x300400
+/* [WB 128] Debug only. Passive buffer memory */
+#define USEM_REG_PASSIVE_BUFFER 0x302000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define USEM_REG_PRAM 0x340000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define USEM_REG_USEM_INT_MASK_0 0x300110
+#define USEM_REG_USEM_INT_MASK_1 0x300120
+/* [R 32] Interrupt register #0 read */
+#define USEM_REG_USEM_INT_STS_0 0x300104
+#define USEM_REG_USEM_INT_STS_1 0x300114
+/* [RC 32] Interrupt register #0 read clear */
+#define USEM_REG_USEM_INT_STS_CLR_0 0x300108
+#define USEM_REG_USEM_INT_STS_CLR_1 0x300118
+/* [RW 32] Parity mask register #0 read/write */
+#define USEM_REG_USEM_PRTY_MASK_0 0x300130
+#define USEM_REG_USEM_PRTY_MASK_1 0x300140
+/* [R 32] Parity register #0 read */
+#define USEM_REG_USEM_PRTY_STS_0 0x300124
+#define USEM_REG_USEM_PRTY_STS_1 0x300134
+/* [RC 32] Parity register #0 read clear */
+#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
+#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
+#define USEM_REG_VFPF_ERR_NUM 0x300380
+#define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
+#define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
+#define VFC_REG_MEMORIES_RST 0x1943c
+/* [RW 1] Interrupt mask register #0 read/write */
+#define VFC_REG_VFC_INT_MASK 0x194f0
+/* [R 1] Interrupt register #0 read */
+#define VFC_REG_VFC_INT_STS 0x194fc
+/* [RC 1] Interrupt register #0 read clear */
+#define VFC_REG_VFC_INT_STS_CLR 0x194f8
+/* [RW 1] Parity mask register #0 read/write */
+#define VFC_REG_VFC_PRTY_MASK 0x194e0
+/* [R 1] Parity register #0 read */
+#define VFC_REG_VFC_PRTY_STS 0x194ec
+/* [RC 1] Parity register #0 read clear */
+#define VFC_REG_VFC_PRTY_STS_CLR 0x194e8
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define XCM_REG_CAM_OCCUP 0x20244
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up. */
+#define XCM_REG_CFC_INIT_CRD 0x20404
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the csem interface. */
+#define XCM_REG_CSEM_LENGTH_MIS 0x20228
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the dorq interface. */
+#define XCM_REG_DORQ_LENGTH_MIS 0x20230
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up. */
+#define XCM_REG_FIC0_INIT_CRD 0x2040c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up. */
+#define XCM_REG_FIC1_INIT_CRD 0x20410
+#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the nig0 interface. */
+#define XCM_REG_NIG0_LENGTH_MIS 0x20238
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the nig1 interface. */
+#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the pbf interface. */
+#define XCM_REG_PBF_LENGTH_MIS 0x20234
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the STORM interface. */
+#define XCM_REG_STORM_LENGTH_MIS 0x2021c
+/* [RW 4] Timers output initial credit. Max credit available - 15.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 4 at start-up. */
+#define XCM_REG_TM_INIT_CRD 0x2041c
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the tsem interface. */
+#define XCM_REG_TSEM_LENGTH_MIS 0x20224
+/* [RC 1] Message length mismatch (relative to last indication) at the usem
+ * interface. */
+#define XCM_REG_USEM_LENGTH_MIS 0x2022c
+#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
+#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
+/* [RW 14] Interrupt mask register #0 read/write */
+#define XCM_REG_XCM_INT_MASK 0x202b4
+/* [R 14] Interrupt register #0 read */
+#define XCM_REG_XCM_INT_STS 0x202a8
+/* [RC 14] Interrupt register #0 read clear */
+#define XCM_REG_XCM_INT_STS_CLR 0x202ac
+/* [RW 30] Parity mask register #0 read/write */
+#define XCM_REG_XCM_PRTY_MASK 0x202c4
+/* [R 30] Parity register #0 read */
+#define XCM_REG_XCM_PRTY_STS 0x202b8
+/* [RC 30] Parity register #0 read clear */
+#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up. */
+#define XCM_REG_XQM_INIT_CRD 0x20420
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the SDM interface. */
+#define XCM_REG_XSDM_LENGTH_MIS 0x20220
+/* [RW 17] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - message length; 11:6] - message
+ * pointer; 16:12] - next pointer. */
+#define XCM_REG_XX_DESCR_TABLE 0x20480
+#define XCM_REG_XX_DESCR_TABLE_SIZE 32
+/* [R 6] Used to read the XX protection Free counter. */
+#define XCM_REG_XX_FREE 0x20240
+#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
+#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
+#define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2)
+#define XMAC_CTRL_REG_RX_EN (0x1<<1)
+#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
+#define XMAC_CTRL_REG_TX_EN (0x1<<0)
+#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7)
+#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
+#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
+#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1)
+#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
+#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
+#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
+#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
+#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
+#define XMAC_REG_CTRL 0
+/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
+ * packets transmitted by the MAC */
+#define XMAC_REG_CTRL_SA_HI 0x2c
+/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
+ * packets transmitted by the MAC */
+#define XMAC_REG_CTRL_SA_LO 0x28
+#define XMAC_REG_EEE_CTRL 0xd8
+#define XMAC_REG_EEE_TIMERS_HI 0xe4
+#define XMAC_REG_PAUSE_CTRL 0x68
+#define XMAC_REG_PFC_CTRL 0x70
+#define XMAC_REG_PFC_CTRL_HI 0x74
+#define XMAC_REG_RX_LSS_CTRL 0x50
+#define XMAC_REG_RX_LSS_STATUS 0x58
+/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
+ * CRC in strip mode */
+#define XMAC_REG_RX_MAX_SIZE 0x40
+#define XMAC_REG_TX_CTRL 0x20
+#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0)
+#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1)
+/* [W 17] Generate an operation after completion; bit-16 is
+ * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
+ * bits 4:0 are the T124Param[4:0] */
+#define XSDM_REG_OPERATION_GEN 0x1664c4
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
+#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
+/* [R 32] Interrupt register #0 read */
+#define XSDM_REG_XSDM_INT_STS_0 0x166290
+#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
+/* [RC 32] Interrupt register #0 read clear */
+#define XSDM_REG_XSDM_INT_STS_CLR_0 0x166294
+#define XSDM_REG_XSDM_INT_STS_CLR_1 0x1662a4
+/* [RW 11] Parity mask register #0 read/write */
+#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
+/* [R 11] Parity register #0 read */
+#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
+/* [RC 11] Parity register #0 read clear */
+#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each
+ * SEM_FAST register offset. */
+#define XSEM_REG_FAST_MEMORY 0x2a0000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work */
+#define XSEM_REG_INT_TABLE 0x280400
+/* [WB 128] Debug only. Passive buffer memory */
+#define XSEM_REG_PASSIVE_BUFFER 0x282000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define XSEM_REG_PRAM 0x2c0000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
+#define XSEM_REG_VFPF_ERR_NUM 0x280380
+/* [RW 32] Interrupt mask register #0 read/write */
+#define XSEM_REG_XSEM_INT_MASK_0 0x280110
+#define XSEM_REG_XSEM_INT_MASK_1 0x280120
+/* [R 32] Interrupt register #0 read */
+#define XSEM_REG_XSEM_INT_STS_0 0x280104
+#define XSEM_REG_XSEM_INT_STS_1 0x280114
+/* [RC 32] Interrupt register #0 read clear */
+#define XSEM_REG_XSEM_INT_STS_CLR_0 0x280108
+#define XSEM_REG_XSEM_INT_STS_CLR_1 0x280118
+/* [RW 32] Parity mask register #0 read/write */
+#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
+#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
+/* [R 32] Parity register #0 read */
+#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
+#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
+/* [RC 32] Parity register #0 read clear */
+#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
+#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
+#define MCPR_ACCESS_LOCK_LOCK (1L<<31)
+#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
+#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
+#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
+#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
+#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
+#define MCPR_NVM_COMMAND_DOIT (1L<<4)
+#define MCPR_NVM_COMMAND_DONE (1L<<3)
+#define MCPR_NVM_COMMAND_FIRST (1L<<7)
+#define MCPR_NVM_COMMAND_LAST (1L<<8)
+#define MCPR_NVM_COMMAND_WR (1L<<5)
+#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
+#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
+#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
+#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
+#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
+#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
+#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
+#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
+#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
+#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
+#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
+#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
+#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
+#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
+#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
+#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
+#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
+#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
+#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
+#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
+#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
+#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
+#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
+#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
+#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
+#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
+#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
+#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
+#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
+#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
+#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
+#define EMAC_LED_100MB_OVERRIDE (1L<<2)
+#define EMAC_LED_10MB_OVERRIDE (1L<<3)
+#define EMAC_LED_OVERRIDE (1L<<0)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
+#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
+#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
+#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
+#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
+#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
+#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
+#define EMAC_MDIO_STATUS_10MB (1L<<1)
+#define EMAC_MODE_25G_MODE (1L<<5)
+#define EMAC_MODE_HALF_DUPLEX (1L<<1)
+#define EMAC_MODE_PORT_GMII (2L<<2)
+#define EMAC_MODE_PORT_MII (1L<<2)
+#define EMAC_MODE_PORT_MII_10M (3L<<2)
+#define EMAC_MODE_RESET (1L<<0)
+#define EMAC_REG_EMAC_LED 0xc
+#define EMAC_REG_EMAC_MAC_MATCH 0x10
+#define EMAC_REG_EMAC_MDIO_COMM 0xac
+#define EMAC_REG_EMAC_MDIO_MODE 0xb4
+#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
+#define EMAC_REG_EMAC_MODE 0x0
+#define EMAC_REG_EMAC_RX_MODE 0xc8
+#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
+#define EMAC_REG_EMAC_RX_STAT_AC 0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_TX_MODE 0xbc
+#define EMAC_REG_EMAC_TX_STAT_AC 0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_REG_RX_PFC_MODE 0x320
+#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
+#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
+#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
+#define EMAC_REG_RX_PFC_PARAM 0x324
+#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
+#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
+#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
+#define EMAC_RX_MODE_FLOW_EN (1L<<2)
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
+#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
+#define EMAC_RX_MODE_RESET (1L<<0)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
+#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
+#define EMAC_TX_MODE_FLOW_EN (1L<<4)
+#define EMAC_TX_MODE_RESET (1L<<0)
+#define MISC_REGISTERS_GPIO_0 0
+#define MISC_REGISTERS_GPIO_1 1
+#define MISC_REGISTERS_GPIO_2 2
+#define MISC_REGISTERS_GPIO_3 3
+#define MISC_REGISTERS_GPIO_CLR_POS 16
+#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
+#define MISC_REGISTERS_GPIO_FLOAT_POS 24
+#define MISC_REGISTERS_GPIO_HIGH 1
+#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
+#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
+#define MISC_REGISTERS_GPIO_INT_SET_POS 16
+#define MISC_REGISTERS_GPIO_LOW 0
+#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
+#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
+#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
+#define MISC_REGISTERS_GPIO_SET_POS 8
+#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
+#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
+#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
+#define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1<<17)
+#define MISC_REGISTERS_RESET_REG_1_SET 0x584
+#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
+#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
+#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
+#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19)
+#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR (0x1<<16)
+#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_2_SET 0x594
+#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
+#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21)
+#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
+#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
+#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
+#define MISC_SPIO_CLR_POS 16
+#define MISC_SPIO_FLOAT (0xffL<<24)
+#define MISC_SPIO_FLOAT_POS 24
+#define MISC_SPIO_INPUT_HI_Z 2
+#define MISC_SPIO_INT_OLD_SET_POS 16
+#define MISC_SPIO_OUTPUT_HIGH 1
+#define MISC_SPIO_OUTPUT_LOW 0
+#define MISC_SPIO_SET_POS 8
+#define MISC_SPIO_SPIO4 0x10
+#define MISC_SPIO_SPIO5 0x20
+#define HW_LOCK_MAX_RESOURCE_VALUE 31
+#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13
+#define HW_LOCK_RESOURCE_DRV_FLAGS 10
+#define HW_LOCK_RESOURCE_GPIO 1
+#define HW_LOCK_RESOURCE_MDIO 0
+#define HW_LOCK_RESOURCE_NVRAM 12
+#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
+#define HW_LOCK_RESOURCE_RECOVERY_REG 11
+#define HW_LOCK_RESOURCE_RESET 5
+#define HW_LOCK_RESOURCE_SPIO 2
+#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
+#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
+#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
+#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
+#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
+#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
+#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
+#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
+#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
+#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
+#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
+#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
+#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
+#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
+#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
+#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
+#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
+#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
+#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
+#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
+#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
+#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
+#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
+#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
+#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
+#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
+#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
+#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
+#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
+#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
+#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
#define RESERVED_GENERAL_ATTENTION_BIT_0 0
#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
@@ -2175,8 +4061,6 @@
#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
#define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32))
-
-
/*
* This file defines GRC base address for every block.
* This file is included by chipsim, asm microcode and cpp microcode.
@@ -2706,7 +4590,7 @@
#define ME_REG_VF_VALID (1<<8)
#define ME_REG_VF_NUM_SHIFT 9
#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
-#define VF_ID(x) ((x & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT)
+#define VF_ID(x) 0 /* TODO: remove def */
#define ME_REG_VF_ERR (0x1<<3)
#define ME_REG_ABS_PF_NUM_SHIFT 16
#define ME_REG_ABS_PF_NUM \
@@ -2819,6 +4703,20 @@
#define PCI_MSIX_TABLE_ENABLE_MASK 0x8000
+#if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID))
+#define PCI_CAP_LIST_ID_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT))
+#define PCI_CAP_LIST_NEXT_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_STATUS))
+#define PCI_STATUS_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST))
+#define PCI_STATUS_CAP_LIST_DEF
+#endif
+
+
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
@@ -3263,6 +5161,9 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
+#define MDIO_AN_REG_848xx_ID_MSB 0xffe2
+#define BNX2X84858_PHY_ID 0x600d
+#define MDIO_AN_REG_848xx_ID_LSB 0xffe3
#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
@@ -3271,6 +5172,7 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
+#define MDIO_AN_REG_8481_INTERRUPT_MASK 0xfffb
#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
/* BNX2X84823 only */
@@ -3299,6 +5201,8 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
+/* BNX2X84858 only */
+#define MDIO_PMA_REG_84858_ALLOW_GPHY_ACT 0x8000
/* BNX2X84833 only */
#define MDIO_84833_TOP_CFG_FW_REV 0x400f
@@ -3306,32 +5210,32 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
#define MDIO_84833_SUPER_ISOLATE 0x8000
-/* These are mailbox register set used by 84833. */
-#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
-#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
-#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
-#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
-#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
-#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
-#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
-#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
-#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
-#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
-#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
-#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
-#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
-#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
-#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
-#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
-#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
-#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
-
-/* Mailbox command set used by 84833. */
-#define PHY84833_CMD_SET_PAIR_SWAP 0x8001
-#define PHY84833_CMD_GET_EEE_MODE 0x8008
-#define PHY84833_CMD_SET_EEE_MODE 0x8009
-#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
-/* Mailbox status set used by 84833. */
+/* These are mailbox register set used by 84833/84858. */
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
+#define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
+#define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
+#define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
+#define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
+#define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
+#define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
+#define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
+
+/* Mailbox command set used by 84833/84858 */
+#define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
+#define PHY848xx_CMD_GET_EEE_MODE 0x8008
+#define PHY848xx_CMD_SET_EEE_MODE 0x8009
+#define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031
+/* Mailbox status set used by 84833 only */
#define PHY84833_STATUS_CMD_RECEIVED 0x0001
#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
@@ -3341,6 +5245,17 @@ Theotherbitsarereservedandshouldbezero*/
#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
+/* Mailbox Process */
+#define PHY84833_MB_PROCESS1 1
+#define PHY84833_MB_PROCESS2 2
+#define PHY84833_MB_PROCESS3 3
+
+/* Mailbox status set used by 84858 only */
+#define PHY84858_STATUS_CMD_RECEIVED 0x0001
+#define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
+#define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
+#define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
+#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
/* Warpcore clause 45 addressing */
@@ -3367,6 +5282,8 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
@@ -3382,7 +5299,9 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
+#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
+#define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
#define MDIO_WC_REG_XGXS_STATUS3 0x8129
#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
@@ -3432,7 +5351,10 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
+#define AUTODET_EN (1<<4)
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
+#define EN_PARALLEL_DET 1
+#define FILTER_FORCE_LINK (1<<2)
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
@@ -3501,10 +5423,15 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_REG_GPHY_CL45_REG_READ 0xc000
#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
+#define MDIO_REG_GPHY_BASET_EXT_CTRL 0x10
+#define MDIO_REG_GPHY_TX_HIGH_LATENCY 0x1
#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
#define MDIO_REG_GPHY_EXP_ACCESS 0x17
#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
+#define MDIO_REG_GPHY_SHADOW_ACCESS 0x18
+#define MDIO_REG_GPHY_SHADOW_AUX_CTRL (0x0)
+#define MDIO_REG_GPHY_SHADOW_MISC_CTRL (0x7)
#define MDIO_REG_GPHY_AUX_STATUS 0x19
#define MDIO_REG_INTR_STATUS 0x1a
#define MDIO_REG_INTR_MASK 0x1b
@@ -3516,7 +5443,6 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
-
#define IGU_FUNC_BASE 0x0400
#define IGU_ADDR_MSIX 0x0000
@@ -3585,7 +5511,7 @@ Theotherbitsarereservedandshouldbezero*/
#define IGU_SEG_IDX_ATTN 2
#define IGU_SEG_IDX_DEFAULT 1
-/* Fields of IGU PF CONFIGRATION REGISTER */
+/* Fields of IGU PF CONFIGURATION REGISTER */
#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
@@ -3593,7 +5519,7 @@ Theotherbitsarereservedandshouldbezero*/
#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
-/* Fields of IGU VF CONFIGRATION REGISTER */
+/* Fields of IGU VF CONFIGURATION REGISTER */
#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
@@ -3640,4 +5566,62 @@ Theotherbitsarereservedandshouldbezero*/
(0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
+/******************************************************************************
+ * Description:
+ * Calculates crc 8 on a word value: polynomial 0-1-2-8
+ * Code was translated from Verilog.
+ * Return:
+ *****************************************************************************/
+static inline uint8_t calc_crc8(uint32_t data, uint8_t crc)
+{
+ uint8_t D[32];
+ uint8_t NewCRC[8];
+ uint8_t C[8];
+ uint8_t crc_res;
+ uint8_t i;
+
+ /* split the data into 31 bits */
+ for (i = 0; i < 32; i++) {
+ D[i] = (uint8_t)(data & 1);
+ data = data >> 1;
+ }
+
+ /* split the crc into 8 bits */
+ for (i = 0; i < 8; i++) {
+ C[i] = crc & 1;
+ crc = crc >> 1;
+ }
+
+ NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
+ D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
+ C[6] ^ C[7];
+ NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
+ D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
+ D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
+ NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
+ D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
+ C[0] ^ C[1] ^ C[4] ^ C[5];
+ NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
+ D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
+ C[1] ^ C[2] ^ C[5] ^ C[6];
+ NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
+ D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
+ C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
+ NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
+ D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
+ C[3] ^ C[4] ^ C[7];
+ NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
+ D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5];
+ NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
+ D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6];
+
+ crc_res = 0;
+ for (i = 0; i < 8; i++) {
+ crc_res |= (NewCRC[i] << i);
+ }
+
+ return crc_res;
+}
+
+
#endif /* ECORE_REG_H */
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH 1/5] net/bnx2x: update and reorganize HW registers
2019-09-06 7:25 ` [dpdk-dev] [PATCH 1/5] net/bnx2x: update and reorganize HW registers Rasesh Mody
@ 2019-09-12 12:17 ` Jerin Jacob
2019-09-19 21:28 ` [dpdk-dev] [EXT] " Rasesh Mody
2019-09-23 10:47 ` [dpdk-dev] " Jerin Jacob
1 sibling, 1 reply; 29+ messages in thread
From: Jerin Jacob @ 2019-09-12 12:17 UTC (permalink / raw)
To: Rasesh Mody; +Cc: dev, ferruh.yigit, Jerin Jacob, GR-Everest-DPDK-Dev
On Fri, Sep 6, 2019 at 12:57 PM Rasesh Mody <rmody@marvell.com> wrote:
>
> Update and reorganize HW registers in preparation to update the firmware
> to version 7.13.11.
> Move HW_INTERRUT_ASSERT_SET_0 out from ecore_reg.h to bnx2x.h.
>
> Signed-off-by: Rasesh Mody <rmody@marvell.com>
> ---
> drivers/net/bnx2x/bnx2x.c | 3 +-
> drivers/net/bnx2x/bnx2x.h | 67 +
> drivers/net/bnx2x/ecore_reg.h | 6246 ++++++++++++++++++++++-----------
> 3 files changed, 4183 insertions(+), 2133 deletions(-)
>
+/******************************************************************************
> + * Description:
> + * Calculates crc 8 on a word value: polynomial 0-1-2-8
> + * Code was translated from Verilog.
Not relevant comment.
> + * Return:
> + *****************************************************************************/
> +static inline uint8_t calc_crc8(uint32_t data, uint8_t crc)
> +{
If is used in slow-path code then move to .c file.
If it is standard crc function then please think about reusing dpdk;s CRC lib.
> + uint8_t D[32];
> + uint8_t NewCRC[8];
> + uint8_t C[8];
> + uint8_t crc_res;
> + uint8_t i;
> +
> + /* split the data into 31 bits */
> + for (i = 0; i < 32; i++) {
> + D[i] = (uint8_t)(data & 1);
> + data = data >> 1;
> + }
> +
> + /* split the crc into 8 bits */
> + for (i = 0; i < 8; i++) {
> + C[i] = crc & 1;
> + crc = crc >> 1;
> + }
> +
> + NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
> + D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
> + C[6] ^ C[7];
> + NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
> + D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
> + D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
> + NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
> + D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
> + C[0] ^ C[1] ^ C[4] ^ C[5];
> + NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
> + D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
> + C[1] ^ C[2] ^ C[5] ^ C[6];
> + NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
> + D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
> + C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
> + NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
> + D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
> + C[3] ^ C[4] ^ C[7];
> + NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
> + D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5];
> + NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
> + D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6];
> +
> + crc_res = 0;
> + for (i = 0; i < 8; i++) {
> + crc_res |= (NewCRC[i] << i);
> + }
> +
> + return crc_res;
> +}
> +
> +
> #endif /* ECORE_REG_H */
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [EXT] Re: [PATCH 1/5] net/bnx2x: update and reorganize HW registers
2019-09-12 12:17 ` Jerin Jacob
@ 2019-09-19 21:28 ` Rasesh Mody
0 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-19 21:28 UTC (permalink / raw)
To: Jerin Jacob
Cc: dev, ferruh.yigit, Jerin Jacob Kollanukkaran, GR-Everest-DPDK-Dev
Hi Jerin,
>From: Jerin Jacob <jerinjacobk@gmail.com>
>Sent: Thursday, September 12, 2019 5:18 AM
>
>----------------------------------------------------------------------
>On Fri, Sep 6, 2019 at 12:57 PM Rasesh Mody <rmody@marvell.com> wrote:
>>
>> Update and reorganize HW registers in preparation to update the
>> firmware to version 7.13.11.
>> Move HW_INTERRUT_ASSERT_SET_0 out from ecore_reg.h to bnx2x.h.
>>
>> Signed-off-by: Rasesh Mody <rmody@marvell.com>
>> ---
>> drivers/net/bnx2x/bnx2x.c | 3 +-
>> drivers/net/bnx2x/bnx2x.h | 67 +
>> drivers/net/bnx2x/ecore_reg.h | 6246
>> ++++++++++++++++++++++-----------
>> 3 files changed, 4183 insertions(+), 2133 deletions(-)
>>
>
>+/*********************************************************
>*********************
>> + * Description:
>> + * Calculates crc 8 on a word value: polynomial 0-1-2-8
>> + * Code was translated from Verilog.
>
>Not relevant comment.
>
>> + * Return:
>> +
>>
>+**********************************************************
>***********
>> +********/ static inline uint8_t calc_crc8(uint32_t data, uint8_t crc)
>> +{
>
>If is used in slow-path code then move to .c file.
>If it is standard crc function then please think about reusing dpdk;s CRC lib.
>
Removed calc_crc8() from this patch in v2 series, we use ecore_calc_crc8().
It's non-standard crc function, unavailable in dpdk's CRC lib.
Thanks!
-Rasesh
>
>> + uint8_t D[32];
>> + uint8_t NewCRC[8];
>> + uint8_t C[8];
>> + uint8_t crc_res;
>> + uint8_t i;
>> +
>> + /* split the data into 31 bits */
>> + for (i = 0; i < 32; i++) {
>> + D[i] = (uint8_t)(data & 1);
>> + data = data >> 1;
>> + }
>> +
>> + /* split the crc into 8 bits */
>> + for (i = 0; i < 8; i++) {
>> + C[i] = crc & 1;
>> + crc = crc >> 1;
>> + }
>> +
>> + NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
>> + D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
>> + C[6] ^ C[7];
>> + NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
>> + D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
>> + D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
>> + NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
>> + D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
>> + C[0] ^ C[1] ^ C[4] ^ C[5];
>> + NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
>> + D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
>> + C[1] ^ C[2] ^ C[5] ^ C[6];
>> + NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
>> + D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
>> + C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
>> + NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
>> + D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
>> + C[3] ^ C[4] ^ C[7];
>> + NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
>> + D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5];
>> + NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
>> + D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
>> + C[6];
>> +
>> + crc_res = 0;
>> + for (i = 0; i < 8; i++) {
>> + crc_res |= (NewCRC[i] << i);
>> + }
>> +
>> + return crc_res;
>> +}
>> +
>> +
>> #endif /* ECORE_REG_H */
>> --
>> 2.18.0
>>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [dpdk-dev] [PATCH 1/5] net/bnx2x: update and reorganize HW registers
2019-09-06 7:25 ` [dpdk-dev] [PATCH 1/5] net/bnx2x: update and reorganize HW registers Rasesh Mody
2019-09-12 12:17 ` Jerin Jacob
@ 2019-09-23 10:47 ` Jerin Jacob
1 sibling, 0 replies; 29+ messages in thread
From: Jerin Jacob @ 2019-09-23 10:47 UTC (permalink / raw)
To: Rasesh Mody; +Cc: dev, Ferruh Yigit, Jerin Jacob, GR-Everest-DPDK-Dev
On Fri, Sep 6, 2019 at 12:57 PM Rasesh Mody <rmody@marvell.com> wrote:
>
> Update and reorganize HW registers in preparation to update the firmware
> to version 7.13.11.
> Move HW_INTERRUT_ASSERT_SET_0 out from ecore_reg.h to bnx2x.h.
>
> Signed-off-by: Rasesh Mody <rmody@marvell.com>
> ---
> drivers/net/bnx2x/bnx2x.c | 3 +-
> drivers/net/bnx2x/bnx2x.h | 67 +
> drivers/net/bnx2x/ecore_reg.h | 6246 ++++++++++++++++++++++-----------
> 3 files changed, 4183 insertions(+), 2133 deletions(-)
Series applied to dpdk-next-net-mrvl/master. Thanks.
Note:
There are checkpatch errors with base code. I guess, we can not do
much about it.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [dpdk-dev] [PATCH 2/5] net/bnx2x: update HSI code
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
2019-09-06 7:25 ` [dpdk-dev] [PATCH 1/5] net/bnx2x: update and reorganize HW registers Rasesh Mody
@ 2019-09-06 7:25 ` Rasesh Mody
2019-09-06 7:25 ` [dpdk-dev] [PATCH 3/5] net/bnx2x: update to latest FW 7.13.11 Rasesh Mody
` (12 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-06 7:25 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, ferruh.yigit, jerinj, GR-Everest-DPDK-Dev
Update hardware software common base driver code in preparation to
update the firmware to version 7.13.11.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/bnx2x/bnx2x.c | 19 +-
drivers/net/bnx2x/bnx2x.h | 23 +-
drivers/net/bnx2x/bnx2x_osal.h | 27 +
drivers/net/bnx2x/bnx2x_rxtx.c | 10 +-
drivers/net/bnx2x/ecore_hsi.h | 3507 ++++++++++++++++++--------------
drivers/net/bnx2x/ecore_sp.c | 11 +-
6 files changed, 1989 insertions(+), 1608 deletions(-)
create mode 100644 drivers/net/bnx2x/bnx2x_osal.h
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 47972cd73..a83a7103e 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -2182,8 +2182,10 @@ int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
- tx_start_bd->addr =
- rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
+ tx_start_bd->addr_lo =
+ rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
+ tx_start_bd->addr_hi =
+ rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
tx_start_bd->general_data =
@@ -5015,13 +5017,13 @@ static void
bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
- union ustorm_eth_rx_producers rx_prods;
+ struct ustorm_eth_rx_producers rx_prods = { 0 };
uint32_t i;
/* update producers */
- rx_prods.prod.bd_prod = rx_bd_prod;
- rx_prods.prod.cqe_prod = rx_cq_prod;
- rx_prods.prod.reserved = 0;
+ rx_prods.bd_prod = rx_bd_prod;
+ rx_prods.cqe_prod = rx_cq_prod;
+ rx_prods.reserved = 0;
/*
* Make sure that the BD and SGE data is updated before updating the
@@ -5034,9 +5036,8 @@ bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
wmb();
for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
- REG_WR(sc,
- (fp->ustorm_rx_prods_offset + (i * 4)),
- rx_prods.raw_data[i]);
+ REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
+ ((uint32_t *)&rx_prods)[i]);
}
wmb(); /* keep prod updates ordered */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 1ea8b55c9..054d95424 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -19,18 +19,7 @@
#include <rte_bus_pci.h>
#include <rte_io.h>
-#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
-#ifndef __LITTLE_ENDIAN
-#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
-#endif
-#undef __BIG_ENDIAN
-#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
-#ifndef __BIG_ENDIAN
-#define __BIG_ENDIAN RTE_BIG_ENDIAN
-#endif
-#undef __LITTLE_ENDIAN
-#endif
-
+#include "bnx2x_osal.h"
#include "bnx2x_ethdev.h"
#include "ecore_mfw_req.h"
#include "ecore_fw_defs.h"
@@ -1911,16 +1900,18 @@ bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
{
uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
COMMAND_REG_INT_ACK);
- union igu_ack_register igu_ack;
+ struct igu_ack_register igu_ack;
+ uint32_t *val = NULL;
- igu_ack.sb.status_block_index = index;
- igu_ack.sb.sb_id_and_flags =
+ igu_ack.status_block_index = index;
+ igu_ack.sb_id_and_flags =
((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
(storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
- REG_WR(sc, hc_addr, igu_ack.raw_data);
+ val = (uint32_t *)&igu_ack;
+ REG_WR(sc, hc_addr, *val);
/* Make sure that ACK is written */
mb();
diff --git a/drivers/net/bnx2x/bnx2x_osal.h b/drivers/net/bnx2x/bnx2x_osal.h
new file mode 100644
index 000000000..b701853e1
--- /dev/null
+++ b/drivers/net/bnx2x/bnx2x_osal.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2019 Cavium Inc.
+ *
+ * All rights reserved.
+ * www.cavium.com
+ */
+
+#ifndef BNX2X_OSAL_H
+#define BNX2X_OSAL_H
+
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
+#endif
+#undef __BIG_ENDIAN
+#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN RTE_BIG_ENDIAN
+#endif
+#undef __LITTLE_ENDIAN
+#endif
+
+#define __le16 uint16_t
+#define __le32 uint32_t
+#define __le64 uint64_t
+
+#endif /* BNX2X_OSAL_H */
diff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c
index e5a2b25b5..ae97dfee3 100644
--- a/drivers/net/bnx2x/bnx2x_rxtx.c
+++ b/drivers/net/bnx2x/bnx2x_rxtx.c
@@ -321,12 +321,14 @@ static inline void
bnx2x_upd_rx_prod_fast(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
- union ustorm_eth_rx_producers rx_prods;
+ struct ustorm_eth_rx_producers rx_prods = { 0 };
+ uint32_t *val = NULL;
- rx_prods.prod.bd_prod = rx_bd_prod;
- rx_prods.prod.cqe_prod = rx_cq_prod;
+ rx_prods.bd_prod = rx_bd_prod;
+ rx_prods.cqe_prod = rx_cq_prod;
- REG_WR(sc, fp->ustorm_rx_prods_offset, rx_prods.raw_data[0]);
+ val = (uint32_t *)&rx_prods;
+ REG_WR(sc, fp->ustorm_rx_prods_offset, val[0]);
}
static uint16_t
diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index 74189eed6..e1077da1d 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -13,29 +13,32 @@
#ifndef ECORE_HSI_H
#define ECORE_HSI_H
-#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
+#include "ecore_fw_defs.h"
+#include "ecore_mfw_req.h"
+#include "bnx2x_osal.h"
+
+#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
struct license_key {
- uint32_t reserved[6];
+ uint32_t reserved[6];
- uint32_t max_iscsi_conn;
-#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
-#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
-#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
-#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
+ uint32_t max_iscsi_conn;
+#define ECORE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
+#define ECORE_MAX_ISCSI_TRGT_CONN_SHIFT 0
+#define ECORE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
+#define ECORE_MAX_ISCSI_INIT_CONN_SHIFT 16
- uint32_t reserved_a;
+ uint32_t reserved_a;
- uint32_t max_fcoe_conn;
-#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
-#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
-#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
-#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
+ uint32_t max_fcoe_conn;
+#define ECORE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
+#define ECORE_MAX_FCOE_TRGT_CONN_SHIFT 0
+#define ECORE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
+#define ECORE_MAX_FCOE_INIT_CONN_SHIFT 16
- uint32_t reserved_b[4];
+ uint32_t reserved_b[4];
};
-typedef struct license_key license_key_t;
/****************************************************************************
@@ -270,6 +273,13 @@ struct shared_hw_cfg { /* NVRAM Offset */
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
+ /* This field extends the mf mode chosen in nvm cfg #73 (as we ran
+ out of bits) */
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
+
uint32_t ump_nc_si_config; /* 0x120 */
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
@@ -332,6 +342,7 @@ struct shared_hw_cfg { /* NVRAM Offset */
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
+ #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000
};
@@ -499,7 +510,6 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
*/
#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
-
/* Set non-default values for TXFIR in SFP mode. */
#define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
@@ -672,7 +682,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002
- #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
+ #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020
@@ -738,6 +748,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8722 0x00000f00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54616 0x00001000
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84834 0x00001100
+ #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84858 0x00001200
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
@@ -795,7 +806,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722 0x00000f00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616 0x00001000
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834 0x00001100
- #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858 0x00001200
+ #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858 0x00001200
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
@@ -874,6 +885,9 @@ struct shared_feat_cfg { /* NVRAM Offset */
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
/* Act as if the FCoE license is invalid */
#define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000
@@ -958,6 +972,12 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00
+ #define PORT_FEAT_CFG_DCBX_SEL_MASK 0x00003000
+ #define PORT_FEAT_CFG_DCBX_SEL_SHIFT 12
+ #define PORT_FEAT_CFG_DCBX_SEL_CEE 0x00000000
+ #define PORT_FEAT_CFG_DCBX_SEL_IEEE 0x00001000
+ #define PORT_FEAT_CFG_DCBX_SEL_AUTO 0x00002000
+
#define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
#define PORT_FEATURE_EN_SIZE_SHIFT 24
#define PORT_FEATURE_WOL_ENABLED 0x01000000
@@ -1040,14 +1060,24 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000
#define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000
- uint32_t Reserved0; /* 0x460 */
+ /* Secondary MBA configuration,
+ * see mba_config for the fileds defination.
+ */
+ uint32_t mba_config2;
uint32_t mba_vlan_cfg;
#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF
#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
+ #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000
+ #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000
+ #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000
+
+ /* Secondary MBA configuration,
+ * see mba_vlan_cfg for the fileds defination.
+ */
+ uint32_t mba_vlan_cfg2;
- uint32_t Reserved1;
uint32_t smbus_config;
#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
@@ -1088,8 +1118,8 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000
#define PORT_FEATURE_LINK_SPEED_SHIFT 16
#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
- #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
- #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
+ #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000
+ #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000
#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
@@ -1130,7 +1160,7 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
- uint32_t Reserved2[16]; /* 0x488 */
+ uint32_t Reserved2[16]; /* 0x48C */
};
/****************************************************************************
@@ -1241,6 +1271,15 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0
+ /* Sensor interface - Disabled / BSC / In the future - SMBUS */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000
+
+ /* On Board Sensor Address */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18
/* MFW flavor to be used */
uint32_t mfw_cfg; /* 0x4008 */
@@ -1255,6 +1294,32 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100
+ /* Prevent OCBB feature */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200
+
+ /* Enable DCi support */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400
+
+ /* Reserved bits: 75 */
+
+ /* PLDM support over MCTP */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_MASK 0x00001000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_SHIFT 12
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_ENABLED 0x00001000
+
+ /* Option to Disable embedded LLDP, 0 - Off, 1 - On */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_MASK 0x00002000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_SHIFT 13
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_OFF 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_ON 0x00002000
+
/* Hide DCBX feature in CCM/BACS menus */
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16
@@ -1291,6 +1356,25 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200
+ /* Overide PCIE revision ID when enabled the,
+ revision ID will set to B1=='0x11' */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400
+
+ /* Bypass slicer offset tuning */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800
+ /* Control Revision ID */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000
/* Threshold in celcius for max continuous operation */
uint32_t temperature_report; /* 0x4014 */
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F
@@ -1341,6 +1425,14 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000
+ /* Override Rx signal detect threshold when enabled the threshold
+ * will be set staticaly
+ */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000
+
/* Debug signet rx threshold */
uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007
@@ -1434,6 +1526,31 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16
#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000
#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24
+
+ /* Manufacture kit version */
+ uint32_t manufacture_ver; /* 0x403C */
+
+ /* Manufacture timestamp */
+ uint32_t manufacture_data; /* 0x4040 */
+
+ /* Number of ISCSI/FCOE cfg images */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000
+
+ /* MCP crash dump trigger */
+ uint32_t mcp_crash_dump; /* 0x4044 */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001
+
+ /* MBI version */
+ uint32_t mbi_version; /* 0x4048 */
+
+ /* MBI date */
+ uint32_t mbi_date; /* 0x404C */
};
@@ -1449,6 +1566,7 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
+#define E1_FUNC_MAX 2
#define E1H_FUNC_MAX 8
#define E2_FUNC_MAX 4 /* per path */
@@ -1575,6 +1693,10 @@ struct drv_func_mb {
#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
+ #define DRV_MSG_CODE_OEM_OK 0x00010000
+ #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
/*
* The optic module verification command requires bootcode
@@ -1629,8 +1751,15 @@ struct drv_func_mb {
#define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000
#define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000
+ #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000
+
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
+ #define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000
+
+ #define DRV_MSG_CODE_UPDATE_DRIVER_STATE 0xC2000000
+ #define REQ_BC_VER_4_UPDATE_DRIVER_STATE 0x00070f35
+
uint32_t drv_mb_param;
#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
@@ -1642,6 +1771,22 @@ struct drv_func_mb {
#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
#define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001
+ #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002
+ #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003
+ #define DRV_MSG_CODE_VLAN_TABLE_IMAGE_REQ 0x00000004
+
+ #define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001
+ #define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002
+ #define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003
+ #define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004
+ #define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005
+ #define DRV_MSG_CODE_CONFIG_CHANGE_RST2DFT 0x00000006
+
+ #define DRV_MSG_CODE_DRIVER_STATE_UNKNOWN 0x00000001
+ #define DRV_MSG_CODE_DRIVER_STATE_NOT_LOADED 0x00000002
+ #define DRV_MSG_CODE_DRIVER_STATE_LOADING 0x00000003
+ #define DRV_MSG_CODE_DRIVER_STATE_DISABLED 0x00000004
+ #define DRV_MSG_CODE_DRIVER_STATE_ACTIVE 0x00000005
uint32_t fw_mb_header;
#define FW_MSG_CODE_MASK 0xffff0000
@@ -1708,6 +1853,13 @@ struct drv_func_mb {
#define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000
#define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000
+ #define FW_MSG_CODE_OEM_ACK 0x00010000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000
+
+ #define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000
+
+ #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0xC3000000
+
#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
uint32_t fw_mb_param;
@@ -1745,6 +1897,13 @@ struct drv_func_mb {
#define DRV_STATUS_SET_MF_BW 0x00000004
#define DRV_STATUS_LINK_EVENT 0x00000008
+ #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
+ #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
+ #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
+ #define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040
+
+ #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
+
#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
@@ -1958,7 +2117,7 @@ struct shmem_region { /* SharedMem Offset (size) */
struct shm_dev_info dev_info; /* 0x8 (0x438) */
- license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
+ struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
/* FW information (for internal FW use) */
uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */
@@ -1976,7 +2135,7 @@ struct shmem_region { /* SharedMem Offset (size) */
struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
#endif /* BMAPI */
-}; /* 57711 = 0x7E4 | 57712 = 0x734 */
+}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
/****************************************************************************
* Shared Memory 2 Region *
@@ -1995,7 +2154,7 @@ struct shmem_region { /* SharedMem Offset (size) */
/****************************************************************************/
struct fw_flr_ack {
uint32_t pf_ack;
- uint32_t vf_ack[1];
+ uint32_t vf_ack;
uint32_t iov_dis_ack;
};
@@ -2134,17 +2293,30 @@ struct dcbx_app_priority_entry {
uint8_t pri_bitmap;
uint8_t appBitfield;
#define DCBX_APP_ENTRY_VALID 0x01
- #define DCBX_APP_ENTRY_SF_MASK 0x30
+ #define DCBX_APP_ENTRY_SF_MASK 0xF0
#define DCBX_APP_ENTRY_SF_SHIFT 4
#define DCBX_APP_SF_ETH_TYPE 0x10
- #define DCBX_APP_SF_PORT 0x20
+ #define DCBX_APP_SF_PORT 0x20 /* TCP */
+ #define DCBX_APP_SF_UDP 0x40 /* UDP */
+ #define DCBX_APP_SF_DEFAULT 0x80
+ #define DCBX_APP_PRI_0 0x01
+ #define DCBX_APP_PRI_1 0x02
+ #define DCBX_APP_PRI_2 0x04
+ #define DCBX_APP_PRI_3 0x08
+ #define DCBX_APP_PRI_4 0x10
+ #define DCBX_APP_PRI_5 0x20
+ #define DCBX_APP_PRI_6 0x40
+ #define DCBX_APP_PRI_7 0x80
#elif defined(__LITTLE_ENDIAN)
uint8_t appBitfield;
#define DCBX_APP_ENTRY_VALID 0x01
- #define DCBX_APP_ENTRY_SF_MASK 0x30
+ #define DCBX_APP_ENTRY_SF_MASK 0xF0
#define DCBX_APP_ENTRY_SF_SHIFT 4
+ #define DCBX_APP_ENTRY_VALID 0x01
#define DCBX_APP_SF_ETH_TYPE 0x10
- #define DCBX_APP_SF_PORT 0x20
+ #define DCBX_APP_SF_PORT 0x20 /* TCP */
+ #define DCBX_APP_SF_UDP 0x40 /* UDP */
+ #define DCBX_APP_SF_DEFAULT 0x80
uint8_t pri_bitmap;
uint16_t app_id;
#endif
@@ -2343,6 +2515,85 @@ struct shmem_lfa {
};
+/*
+Used to suppoert NSCI get OS driver version
+On driver load the version value will be set
+On driver unload driver value of 0x0 will be set
+*/
+struct os_drv_ver{
+ #define DRV_VER_NOT_LOADED 0
+ /*personalites orrder is importent */
+ #define DRV_PERS_ETHERNET 0
+ #define DRV_PERS_ISCSI 1
+ #define DRV_PERS_FCOE 2
+ /*shmem2 struct is constatnt can't add more personalites here*/
+ #define MAX_DRV_PERS 3
+ uint32_t versions[MAX_DRV_PERS];
+};
+
+#define OEM_I2C_UUID_STR_ADDR 0x9f
+#define OEM_I2C_CARD_SKU_STR_ADDR 0x3c
+#define OEM_I2C_CARD_FN_STR_ADDR 0x48
+#define OEM_I2C_CARD_NAME_STR_ADDR 0x10e
+
+#define OEM_I2C_UUID_STR_LEN 16
+#define OEM_I2C_CARD_SKU_STR_LEN 12
+#define OEM_I2C_CARD_FN_STR_LEN 12
+#define OEM_I2C_CARD_NAME_STR_LEN 128
+#define OEM_I2C_CARD_VERSION_STR_LEN 36
+
+struct oem_i2c_data_t {
+ uint32_t size;
+ uint8_t uuid[OEM_I2C_UUID_STR_LEN];
+ uint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN];
+ uint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN];
+ uint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN];
+ uint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN];
+};
+
+enum curr_cfg_method_e {
+ CURR_CFG_MET_NONE = 0, /* default config */
+ CURR_CFG_MET_OS = 1,
+ CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */
+ CURR_CFG_MET_HP_OTHER = 3,
+ CURR_CFG_MET_VC_CLP = 4, /* C-Class SM-CLP */
+ CURR_CFG_MET_HP_CNU = 5, /* Converged Network Utility */
+ CURR_CFG_MET_HP_DCI = 6, /* DCi (BD) changes */
+};
+
+#define FC_NPIV_WWPN_SIZE 8
+#define FC_NPIV_WWNN_SIZE 8
+struct bdn_npiv_settings {
+ uint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE];
+ uint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE];
+};
+
+struct bdn_fc_npiv_cfg {
+ /* hdr used internally by the MFW */
+ uint32_t hdr;
+ uint32_t num_of_npiv;
+};
+
+#define MAX_NUMBER_NPIV 64
+struct bdn_fc_npiv_tbl {
+ struct bdn_fc_npiv_cfg fc_npiv_cfg;
+ struct bdn_npiv_settings settings[MAX_NUMBER_NPIV];
+};
+
+struct mdump_driver_info {
+ uint32_t epoc;
+ uint32_t drv_ver;
+ uint32_t fw_ver;
+
+ uint32_t valid_dump;
+ #define FIRST_DUMP_VALID (1 << 0)
+ #define SECOND_DUMP_VALID (1 << 1)
+
+ uint32_t flags;
+ #define ENABLE_ALL_TRIGGERS (0x7fffffff)
+ #define TRIGGER_MDUMP_ONCE (1 << 31)
+};
+
struct shmem2_region {
uint32_t size; /* 0x0000 */
@@ -2426,18 +2677,18 @@ struct shmem2_region {
uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
- uint32_t swim_base_addr; /* 0x0108 */
- uint32_t swim_funcs;
- uint32_t swim_main_cb;
+ uint32_t swim_base_addr; /* 0x00a8 */
+ uint32_t swim_funcs; /* 0x00ac */
+ uint32_t swim_main_cb; /* 0x00b0 */
/*
* bitmap notifying which VIF profiles stored in nvram are enabled by
* switch
*/
- uint32_t afex_profiles_enabled[2];
+ uint32_t afex_profiles_enabled[2]; /* 0x00b4 */
/* generic flags controlled by the driver */
- uint32_t drv_flags;
+ uint32_t drv_flags; /* 0x00bc */
#define DRV_FLAGS_DCB_CONFIGURED 0x0
#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
#define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
@@ -2459,45 +2710,47 @@ struct shmem2_region {
(_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
/* pointer to extended dev_info shared data copied from nvm image */
- uint32_t extended_dev_info_shared_addr;
- uint32_t ncsi_oem_data_addr;
+ uint32_t extended_dev_info_shared_addr; /* 0x00c0 */
+ uint32_t ncsi_oem_data_addr; /* 0x00c4 */
- uint32_t sensor_data_addr;
- uint32_t buffer_block_addr;
- uint32_t sensor_data_req_update_interval;
- uint32_t temperature_in_half_celsius;
- uint32_t glob_struct_in_host;
+ uint32_t sensor_data_addr; /* 0x00c8 */
+ uint32_t buffer_block_addr; /* 0x00cc */
+ uint32_t sensor_data_req_update_interval; /* 0x00d0 */
+ uint32_t temperature_in_half_celsius; /* 0x00d4 */
+ uint32_t glob_struct_in_host; /* 0x00d8 */
- uint32_t dcbx_neg_res_ext_offset;
+ uint32_t dcbx_neg_res_ext_offset; /* 0x00dc */
#define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
- uint32_t drv_capabilities_flag[E2_FUNC_MAX];
+ uint32_t drv_capabilities_flag[E2_FUNC_MAX]; /* 0x00e0 */
#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
+ #define DRV_FLAGS_MTU_MASK 0xffff0000
+ #define DRV_FLAGS_MTU_SHIFT 16
- uint32_t extended_dev_info_shared_cfg_size;
+ uint32_t extended_dev_info_shared_cfg_size; /* 0x00f0 */
- uint32_t dcbx_en[PORT_MAX];
+ uint32_t dcbx_en[PORT_MAX]; /* 0x00f4 */
/* The offset points to the multi threaded meta structure */
- uint32_t multi_thread_data_offset;
+ uint32_t multi_thread_data_offset; /* 0x00fc */
/* address of DMAable host address holding values from the drivers */
- uint32_t drv_info_host_addr_lo;
- uint32_t drv_info_host_addr_hi;
+ uint32_t drv_info_host_addr_lo; /* 0x0100 */
+ uint32_t drv_info_host_addr_hi; /* 0x0104 */
/* general values written by the MFW (such as current version) */
- uint32_t drv_info_control;
+ uint32_t drv_info_control; /* 0x0108 */
#define DRV_INFO_CONTROL_VER_MASK 0x000000ff
#define DRV_INFO_CONTROL_VER_SHIFT 0
#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
- uint32_t ibft_host_addr; /* initialized by option ROM */
+ uint32_t ibft_host_addr; /* initialized by option ROM */ /* 0x010c */
- struct eee_remote_vals eee_remote_vals[PORT_MAX];
- uint32_t pf_allocation[E2_FUNC_MAX];
+ struct eee_remote_vals eee_remote_vals[PORT_MAX]; /* 0x0110 */
+ uint32_t pf_allocation[E2_FUNC_MAX]; /* 0x0120 */
#define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
#define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0
@@ -2515,13 +2768,13 @@ struct shmem2_region {
* bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
* value. When 1'b1 those bits contains a value times 16 microseconds.
*/
- uint32_t eee_status[PORT_MAX];
+ uint32_t eee_status[PORT_MAX]; /* 0x0130 */
#define SHMEM_EEE_TIMER_MASK 0x0000ffff
#define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
#define SHMEM_EEE_SUPPORTED_SHIFT 16
#define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
#define SHMEM_EEE_100M_ADV (1<<0)
- #define SHMEM_EEE_1G_ADV (1U<<1)
+ #define SHMEM_EEE_1G_ADV (1<<1)
#define SHMEM_EEE_10G_ADV (1<<2)
#define SHMEM_EEE_ADV_STATUS_SHIFT 20
#define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
@@ -2531,26 +2784,143 @@ struct shmem2_region {
#define SHMEM_EEE_ACTIVE_BIT 0x40000000
#define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
- uint32_t sizeof_port_stats;
+ uint32_t sizeof_port_stats; /* 0x0138 */
/* Link Flap Avoidance */
- uint32_t lfa_host_addr[PORT_MAX];
+ uint32_t lfa_host_addr[PORT_MAX]; /* 0x013c */
/* External PHY temperature in deg C. */
- uint32_t extphy_temps_in_celsius;
+ uint32_t extphy_temps_in_celsius; /* 0x0144 */
#define EXTPHY1_TEMP_MASK 0x0000ffff
#define EXTPHY1_TEMP_SHIFT 0
+ #define ON_BOARD_TEMP_MASK 0xffff0000
+ #define ON_BOARD_TEMP_SHIFT 16
uint32_t ocdata_info_addr; /* Offset 0x148 */
uint32_t drv_func_info_addr; /* Offset 0x14C */
uint32_t drv_func_info_size; /* Offset 0x150 */
uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */
- #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
- #define LINK_ATTR_84858 0x00000002
- #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
- #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
+ #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
+ #define LINK_ATTR_84858 0x00000002
+ #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
+ #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
+ #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
+ #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
+ #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
+
+ uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */
+ uint32_t fcode_ver; /* Offset 0x15c */
+ uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
+ #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */
+ /* driver version for each personality*/
+ struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
+
+ /* Flag to the driver that PF's drv_info_host_addr buffer was read */
+ uint32_t mfw_drv_indication; /* Offset 0x19c */
+
+ /* We use inidcation for each PF (0..3) */
+ #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << _pf_)
+
+ union { /* For various OEMs */ /* Offset 0x1a0 */
+ uint8_t storage_boot_prog[E2_FUNC_MAX];
+ #define STORAGE_BOOT_PROG_MASK 0x000000FF
+ #define STORAGE_BOOT_PROG_NONE 0x00000000
+ #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
+ #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
+ #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
+ #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
+ #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
+ #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
+ #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
+ #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
+ #define STORAGE_BOOT_PROG_COMPLETED 0x00000080
+
+ uint32_t oem_i2c_data_addr;
+ };
+
+ /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
+ /* For PCP values 0-3 use the map lower */
+ /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
+ * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
+ */
+ uint32_t c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */
+
+ /* For PCP values 4-7 use the map upper */
+ /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
+ * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
+ */
+ uint32_t c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */
+
+ /* For PCP default value get the MSB byte of the map default */
+ uint32_t c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */
+
+ /* FC_NPIV table offset in NVRAM */
+ uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */
+
+ /* Shows last method that changed configuration of this device */
+ enum curr_cfg_method_e curr_cfg; /* 0x1dc */
+
+ /* Storm FW version, shold be kept in the format 0xMMmmbbdd:
+ * MM - Major, mm - Minor, bb - Build ,dd - Drop
+ */
+ uint32_t netproc_fw_ver; /* 0x1e0 */
+
+ /* Option ROM SMASH CLP version */
+ uint32_t clp_ver; /* 0x1e4 */
+
+ uint32_t pcie_bus_num; /* 0x1e8 */
+
+ uint32_t sriov_switch_mode; /* 0x1ec */
+ #define SRIOV_SWITCH_MODE_NONE 0x0
+ #define SRIOV_SWITCH_MODE_VEB 0x1
+ #define SRIOV_SWITCH_MODE_VEPA 0x2
+
+ uint8_t rsrv2[E2_FUNC_MAX]; /* 0x1f0 */
- uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
+ uint32_t img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */
+
+ uint32_t mtu_size[E2_FUNC_MAX]; /* 0x1f8 */
+
+ uint32_t os_driver_state[E2_FUNC_MAX]; /* 0x208 */
+ #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */
+ #define OS_DRIVER_STATE_LOADING 1 /* transition state */
+ #define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */
+ #define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */
+
+ /* mini dump driver info */
+ struct mdump_driver_info drv_info; /* 0x218 */
+
+ /* written by mfw, read by driver, eg. feature capability support */
+ uint32_t mfw_flags; /* 0x22c */
+ #define DISABLE_EMBEDDED_LLDP_SUPPORT 0x00000001
+};
+
+#define VLAN_BITMAP_SIZE 512
+#define VLAN_PF_NUM_MAX 8
+
+struct pf_vlan_table {
+ uint16_t pvid;
+ uint8_t pcp;
+ uint8_t rsvd;
+ uint8_t trunk_vlan_bitmap[VLAN_BITMAP_SIZE];
+ uint32_t rsvd1[4];
+};
+
+struct vlan_table_s {
+ uint32_t version;
+ #define VLAN_TABLE_IMAGE_VERSION_1 1
+ uint8_t vlan_mode[NVM_PATH_MAX][PORT_MAX];
+ #define VLAN_MODE_NORMAL 0
+ #define VLAN_MODE_FILTER 1
+ #define VLAN_MODE_QINQ 2
+ struct pf_vlan_table pf_vlans[VLAN_PF_NUM_MAX];
+ uint32_t rsvd2[8];
+};
+
+/* The VLAN table Image is stored in Big Endian format */
+struct nvm_vlan_table_image {
+ struct vlan_table_s vlan_table;
+ uint32_t crc;
};
@@ -3228,31 +3598,29 @@ struct port_info {
#define BNX2X_5710_FW_MAJOR_VERSION 7
-#define BNX2X_5710_FW_MINOR_VERSION 2
-#define BNX2X_5710_FW_REVISION_VERSION 51
+#define BNX2X_5710_FW_MINOR_VERSION 13
+#define BNX2X_5710_FW_REVISION_VERSION 11
#define BNX2X_5710_FW_ENGINEERING_VERSION 0
#define BNX2X_5710_FW_COMPILE_FLAGS 1
/*
- * attention bits $$KEEP_ENDIANNESS$$
+ * attention bits
*/
-struct atten_sp_status_block
-{
- uint32_t attn_bits /* 16 bit of attention signal lines */;
- uint32_t attn_bits_ack /* 16 bit of attention signal ack */;
- uint8_t status_block_id /* status block id */;
- uint8_t reserved0 /* resreved for padding */;
- uint16_t attn_bits_index /* attention bits running index */;
- uint32_t reserved1 /* resreved for padding */;
+struct atten_sp_status_block {
+ __le32 attn_bits;
+ __le32 attn_bits_ack;
+ uint8_t status_block_id;
+ uint8_t reserved0;
+ __le16 attn_bits_index;
+ __le32 reserved1;
};
/*
* The eth aggregative context of Cstorm
*/
-struct cstorm_eth_ag_context
-{
+struct cstorm_eth_ag_context {
uint32_t __reserved0[10];
};
@@ -3260,101 +3628,100 @@ struct cstorm_eth_ag_context
/*
* dmae command structure
*/
-struct dmae_command
-{
+struct dmae_command {
uint32_t opcode;
-#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */
+#define DMAE_COMMAND_SRC (0x1<<0)
#define DMAE_COMMAND_SRC_SHIFT 0
-#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
+#define DMAE_COMMAND_DST (0x3<<1)
#define DMAE_COMMAND_DST_SHIFT 1
-#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */
+#define DMAE_COMMAND_C_DST (0x1<<3)
#define DMAE_COMMAND_C_DST_SHIFT 3
-#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */
+#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
-#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
-#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
-#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */
+#define DMAE_COMMAND_ENDIANITY (0x3<<9)
#define DMAE_COMMAND_ENDIANITY_SHIFT 9
-#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */
+#define DMAE_COMMAND_PORT (0x1<<11)
#define DMAE_COMMAND_PORT_SHIFT 11
-#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */
+#define DMAE_COMMAND_CRC_RESET (0x1<<12)
#define DMAE_COMMAND_CRC_RESET_SHIFT 12
-#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */
+#define DMAE_COMMAND_SRC_RESET (0x1<<13)
#define DMAE_COMMAND_SRC_RESET_SHIFT 13
-#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */
+#define DMAE_COMMAND_DST_RESET (0x1<<14)
#define DMAE_COMMAND_DST_RESET_SHIFT 14
-#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */
+#define DMAE_COMMAND_E1HVN (0x3<<15)
#define DMAE_COMMAND_E1HVN_SHIFT 15
-#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */
+#define DMAE_COMMAND_DST_VN (0x3<<17)
#define DMAE_COMMAND_DST_VN_SHIFT 17
-#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */
+#define DMAE_COMMAND_C_FUNC (0x1<<19)
#define DMAE_COMMAND_C_FUNC_SHIFT 19
-#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */
+#define DMAE_COMMAND_ERR_POLICY (0x3<<20)
#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
-#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */
+#define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
#define DMAE_COMMAND_RESERVED0_SHIFT 22
- uint32_t src_addr_lo /* source address low/grc address */;
- uint32_t src_addr_hi /* source address hi */;
- uint32_t dst_addr_lo /* dest address low/grc address */;
- uint32_t dst_addr_hi /* dest address hi */;
+ uint32_t src_addr_lo;
+ uint32_t src_addr_hi;
+ uint32_t dst_addr_lo;
+ uint32_t dst_addr_hi;
#if defined(__BIG_ENDIAN)
uint16_t opcode_iov;
-#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
+#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
#define DMAE_COMMAND_SRC_VFID_SHIFT 0
-#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
+#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
-#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED1 (0x1<<7)
#define DMAE_COMMAND_RESERVED1_SHIFT 7
-#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
+#define DMAE_COMMAND_DST_VFID (0x3F<<8)
#define DMAE_COMMAND_DST_VFID_SHIFT 8
-#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
+#define DMAE_COMMAND_DST_VFPF (0x1<<14)
#define DMAE_COMMAND_DST_VFPF_SHIFT 14
-#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED2 (0x1<<15)
#define DMAE_COMMAND_RESERVED2_SHIFT 15
- uint16_t len /* copy length */;
+ uint16_t len;
#elif defined(__LITTLE_ENDIAN)
- uint16_t len /* copy length */;
+ uint16_t len;
uint16_t opcode_iov;
-#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
+#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
#define DMAE_COMMAND_SRC_VFID_SHIFT 0
-#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
+#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
-#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED1 (0x1<<7)
#define DMAE_COMMAND_RESERVED1_SHIFT 7
-#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
+#define DMAE_COMMAND_DST_VFID (0x3F<<8)
#define DMAE_COMMAND_DST_VFID_SHIFT 8
-#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
+#define DMAE_COMMAND_DST_VFPF (0x1<<14)
#define DMAE_COMMAND_DST_VFPF_SHIFT 14
-#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED2 (0x1<<15)
#define DMAE_COMMAND_RESERVED2_SHIFT 15
#endif
- uint32_t comp_addr_lo /* completion address low/grc address */;
- uint32_t comp_addr_hi /* completion address hi */;
- uint32_t comp_val /* value to write to completion address */;
- uint32_t crc32 /* crc32 result */;
- uint32_t crc32_c /* crc32_c result */;
+ uint32_t comp_addr_lo;
+ uint32_t comp_addr_hi;
+ uint32_t comp_val;
+ uint32_t crc32;
+ uint32_t crc32_c;
#if defined(__BIG_ENDIAN)
- uint16_t crc16_c /* crc16_c result */;
- uint16_t crc16 /* crc16 result */;
+ uint16_t crc16_c;
+ uint16_t crc16;
#elif defined(__LITTLE_ENDIAN)
- uint16_t crc16 /* crc16 result */;
- uint16_t crc16_c /* crc16_c result */;
+ uint16_t crc16;
+ uint16_t crc16_c;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3;
- uint16_t crc_t10 /* crc_t10 result */;
+ uint16_t crc_t10;
#elif defined(__LITTLE_ENDIAN)
- uint16_t crc_t10 /* crc_t10 result */;
+ uint16_t crc_t10;
uint16_t reserved3;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t xsum8 /* checksum8 result */;
- uint16_t xsum16 /* checksum16 result */;
+ uint16_t xsum8;
+ uint16_t xsum16;
#elif defined(__LITTLE_ENDIAN)
- uint16_t xsum16 /* checksum16 result */;
- uint16_t xsum8 /* checksum8 result */;
+ uint16_t xsum16;
+ uint16_t xsum8;
#endif
};
@@ -3362,162 +3729,149 @@ struct dmae_command
/*
* common data for all protocols
*/
-struct doorbell_hdr
-{
+struct doorbell_hdr {
uint8_t header;
-#define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */
+#define DOORBELL_HDR_RX (0x1<<0)
#define DOORBELL_HDR_RX_SHIFT 0
-#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */
+#define DOORBELL_HDR_DB_TYPE (0x1<<1)
#define DOORBELL_HDR_DB_TYPE_SHIFT 1
-#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */
+#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
-#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */
+#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
};
/*
* Ethernet doorbell
*/
-struct eth_tx_doorbell
-{
+struct eth_tx_doorbell {
#if defined(__BIG_ENDIAN)
- uint16_t npackets /* number of data bytes that were added in the doorbell */;
+ uint16_t npackets;
uint8_t params;
-#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
-#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
-#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
+#define ETH_TX_DOORBELL_SPARE (0x1<<7)
#define ETH_TX_DOORBELL_SPARE_SHIFT 7
struct doorbell_hdr hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr hdr;
uint8_t params;
-#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
-#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
-#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
+#define ETH_TX_DOORBELL_SPARE (0x1<<7)
#define ETH_TX_DOORBELL_SPARE_SHIFT 7
- uint16_t npackets /* number of data bytes that were added in the doorbell */;
+ uint16_t npackets;
#endif
};
/*
- * 3 lines. status block $$KEEP_ENDIANNESS$$
+ * 3 lines. status block
*/
-struct hc_status_block_e1x
-{
- uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */;
- uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
- uint32_t rsrv[11];
+struct hc_status_block_e1x {
+ __le16 index_values[HC_SB_MAX_INDICES_E1X];
+ __le16 running_index[HC_SB_MAX_SM];
+ __le32 rsrv[11];
};
/*
* host status block
*/
-struct host_hc_status_block_e1x
-{
- struct hc_status_block_e1x sb /* fast path indices */;
+struct host_hc_status_block_e1x {
+ struct hc_status_block_e1x sb;
};
/*
- * 3 lines. status block $$KEEP_ENDIANNESS$$
+ * 3 lines. status block
*/
-struct hc_status_block_e2
-{
- uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */;
- uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
- uint32_t reserved[11];
+struct hc_status_block_e2 {
+ __le16 index_values[HC_SB_MAX_INDICES_E2];
+ __le16 running_index[HC_SB_MAX_SM];
+ __le32 reserved[11];
};
/*
* host status block
*/
-struct host_hc_status_block_e2
-{
- struct hc_status_block_e2 sb /* fast path indices */;
+struct host_hc_status_block_e2 {
+ struct hc_status_block_e2 sb;
};
/*
- * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$
+ * 5 lines. slow-path status block
*/
-struct hc_sp_status_block
-{
- uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */;
- uint16_t running_index /* Status Block running index */;
- uint16_t rsrv;
+struct hc_sp_status_block {
+ __le16 index_values[HC_SP_SB_MAX_INDICES];
+ __le16 running_index;
+ __le16 rsrv;
uint32_t rsrv1;
};
/*
* host status block
*/
-struct host_sp_status_block
-{
- struct atten_sp_status_block atten_status_block /* attention bits section */;
- struct hc_sp_status_block sp_sb /* slow path indices */;
+struct host_sp_status_block {
+ struct atten_sp_status_block atten_status_block;
+ struct hc_sp_status_block sp_sb;
};
/*
* IGU driver acknowledgment register
*/
-union igu_ack_register
-{
- struct {
+struct igu_ack_register {
#if defined(__BIG_ENDIAN)
- uint16_t sb_id_and_flags;
-#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
+ uint16_t sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
-#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
-#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
-#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
-#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
- uint16_t status_block_index /* status block index acknowledgement */;
+ uint16_t status_block_index;
#elif defined(__LITTLE_ENDIAN)
- uint16_t status_block_index /* status block index acknowledgement */;
- uint16_t sb_id_and_flags;
-#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
+ uint16_t status_block_index;
+ uint16_t sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
-#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
-#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
-#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
-#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
#endif
- } sb;
- uint32_t raw_data;
};
/*
* IGU driver acknowledgement register
*/
-struct igu_backward_compatible
-{
+struct igu_backward_compatible {
uint32_t sb_id_and_flags;
-#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
-#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
-#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
-#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
-#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
-#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
uint32_t reserved_2;
};
@@ -3526,26 +3880,25 @@ struct igu_backward_compatible
/*
* IGU driver acknowledgement register
*/
-struct igu_regular
-{
+struct igu_regular {
uint32_t sb_id_and_flags;
-#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
#define IGU_REGULAR_SB_INDEX_SHIFT 0
-#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_RESERVED0 (0x1<<20)
#define IGU_REGULAR_RESERVED0_SHIFT 20
-#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */
+#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
-#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_BUPDATE (0x1<<24)
#define IGU_REGULAR_BUPDATE_SHIFT 24
-#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */
+#define IGU_REGULAR_ENABLE_INT (0x3<<25)
#define IGU_REGULAR_ENABLE_INT_SHIFT 25
-#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_RESERVED_1 (0x1<<27)
#define IGU_REGULAR_RESERVED_1_SHIFT 27
-#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
-#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
-#define IGU_REGULAR_BCLEANUP (0x1U<<31) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_BCLEANUP (0x1<<31)
#define IGU_REGULAR_BCLEANUP_SHIFT 31
uint32_t reserved_2;
};
@@ -3553,8 +3906,7 @@ struct igu_regular
/*
* IGU driver acknowledgement register
*/
-union igu_consprod_reg
-{
+union igu_consprod_reg {
struct igu_regular regular;
struct igu_backward_compatible backward_compatible;
};
@@ -3563,8 +3915,7 @@ union igu_consprod_reg
/*
* Igu control commands
*/
-enum igu_ctrl_cmd
-{
+enum igu_ctrl_cmd {
IGU_CTRL_CMD_TYPE_RD,
IGU_CTRL_CMD_TYPE_WR,
MAX_IGU_CTRL_CMD};
@@ -3573,18 +3924,17 @@ enum igu_ctrl_cmd
/*
* Control register for the IGU command register
*/
-struct igu_ctrl_reg
-{
+struct igu_ctrl_reg {
uint32_t ctrl_data;
-#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */
+#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
#define IGU_CTRL_REG_ADDRESS_SHIFT 0
-#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */
+#define IGU_CTRL_REG_FID (0x7F<<12)
#define IGU_CTRL_REG_FID_SHIFT 12
-#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */
+#define IGU_CTRL_REG_RESERVED (0x1<<19)
#define IGU_CTRL_REG_RESERVED_SHIFT 19
-#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */
+#define IGU_CTRL_REG_TYPE (0x1<<20)
#define IGU_CTRL_REG_TYPE_SHIFT 20
-#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */
+#define IGU_CTRL_REG_UNUSED (0x7FF<<21)
#define IGU_CTRL_REG_UNUSED_SHIFT 21
};
@@ -3592,8 +3942,7 @@ struct igu_ctrl_reg
/*
* Igu interrupt command
*/
-enum igu_int_cmd
-{
+enum igu_int_cmd {
IGU_INT_ENABLE,
IGU_INT_DISABLE,
IGU_INT_NOP,
@@ -3604,8 +3953,7 @@ enum igu_int_cmd
/*
* Igu segments
*/
-enum igu_seg_access
-{
+enum igu_seg_access {
IGU_SEG_ACCESS_NORM,
IGU_SEG_ACCESS_DEF,
IGU_SEG_ACCESS_ATTN,
@@ -3615,34 +3963,33 @@ enum igu_seg_access
/*
* Parser parsing flags field
*/
-struct parsing_flags
-{
- uint16_t flags;
-#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */
+struct parsing_flags {
+ __le16 flags;
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
-#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */
+#define PARSING_FLAGS_VLAN (0x1<<1)
#define PARSING_FLAGS_VLAN_SHIFT 1
-#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */
+#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
-#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
-#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */
+#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
-#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */
+#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
-#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */
+#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
-#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */
+#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
-#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
-#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
-#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */
+#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
-#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */
+#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
-#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */
+#define PARSING_FLAGS_RESERVED0 (0x3<<14)
#define PARSING_FLAGS_RESERVED0_SHIFT 14
};
@@ -3650,8 +3997,7 @@ struct parsing_flags
/*
* Parsing flags for TCP ACK type
*/
-enum prs_flags_ack_type
-{
+enum prs_flags_ack_type {
PRS_FLAG_PUREACK_PIGGY,
PRS_FLAG_PUREACK_PURE,
MAX_PRS_FLAGS_ACK_TYPE};
@@ -3660,8 +4006,7 @@ enum prs_flags_ack_type
/*
* Parsing flags for Ethernet address type
*/
-enum prs_flags_eth_addr_type
-{
+enum prs_flags_eth_addr_type {
PRS_FLAG_ETHTYPE_NON_UNICAST,
PRS_FLAG_ETHTYPE_UNICAST,
MAX_PRS_FLAGS_ETH_ADDR_TYPE};
@@ -3670,8 +4015,7 @@ enum prs_flags_eth_addr_type
/*
* Parsing flags for over-ethernet protocol
*/
-enum prs_flags_over_eth
-{
+enum prs_flags_over_eth {
PRS_FLAG_OVERETH_UNKNOWN,
PRS_FLAG_OVERETH_IPV4,
PRS_FLAG_OVERETH_IPV6,
@@ -3682,8 +4026,7 @@ enum prs_flags_over_eth
/*
* Parsing flags for over-IP protocol
*/
-enum prs_flags_over_ip
-{
+enum prs_flags_over_ip {
PRS_FLAG_OVERIP_UNKNOWN,
PRS_FLAG_OVERIP_TCP,
PRS_FLAG_OVERIP_UDP,
@@ -3693,18 +4036,17 @@ enum prs_flags_over_ip
/*
* SDM operation gen command (generate aggregative interrupt)
*/
-struct sdm_op_gen
-{
- uint32_t command;
-#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */
+struct sdm_op_gen {
+ __le32 command;
+#define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
-#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */
+#define SDM_OP_GEN_COMP_TYPE (0x7<<5)
#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
-#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */
+#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
-#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */
+#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
-#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */
+#define SDM_OP_GEN_RESERVED (0x7FFF<<17)
#define SDM_OP_GEN_RESERVED_SHIFT 17
};
@@ -3712,17 +4054,16 @@ struct sdm_op_gen
/*
* Timers connection context
*/
-struct timers_block_context
-{
- uint32_t __reserved_0 /* data of client 0 of the timers block*/;
- uint32_t __reserved_1 /* data of client 1 of the timers block*/;
- uint32_t __reserved_2 /* data of client 2 of the timers block*/;
+struct timers_block_context {
+ uint32_t __reserved_0;
+ uint32_t __reserved_1;
+ uint32_t __reserved_2;
uint32_t flags;
-#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */
+#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
-#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */
+#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
-#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */
+#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
};
@@ -3730,8 +4071,7 @@ struct timers_block_context
/*
* The eth aggregative context of Tstorm
*/
-struct tstorm_eth_ag_context
-{
+struct tstorm_eth_ag_context {
uint32_t __reserved0[14];
};
@@ -3739,17 +4079,16 @@ struct tstorm_eth_ag_context
/*
* The eth aggregative context of Ustorm
*/
-struct ustorm_eth_ag_context
-{
+struct ustorm_eth_ag_context {
uint32_t __reserved0;
#if defined(__BIG_ENDIAN)
- uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
+ uint8_t cdu_usage;
uint8_t __reserved2;
uint16_t __reserved1;
#elif defined(__LITTLE_ENDIAN)
uint16_t __reserved1;
uint8_t __reserved2;
- uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
+ uint8_t cdu_usage;
#endif
uint32_t __reserved3[6];
};
@@ -3758,17 +4097,16 @@ struct ustorm_eth_ag_context
/*
* The eth aggregative context of Xstorm
*/
-struct xstorm_eth_ag_context
-{
+struct xstorm_eth_ag_context {
uint32_t reserved0;
#if defined(__BIG_ENDIAN)
- uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
+ uint8_t cdu_reserved;
uint8_t reserved2;
uint16_t reserved1;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved1;
uint8_t reserved2;
- uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
+ uint8_t cdu_reserved;
#endif
uint32_t reserved3[30];
};
@@ -3777,16 +4115,15 @@ struct xstorm_eth_ag_context
/*
* doorbell message sent to the chip
*/
-struct doorbell
-{
+struct doorbell {
#if defined(__BIG_ENDIAN)
- uint16_t zero_fill2 /* driver must zero this field! */;
- uint8_t zero_fill1 /* driver must zero this field! */;
+ uint16_t zero_fill2;
+ uint8_t zero_fill1;
struct doorbell_hdr header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr header;
- uint8_t zero_fill1 /* driver must zero this field! */;
- uint16_t zero_fill2 /* driver must zero this field! */;
+ uint8_t zero_fill1;
+ uint16_t zero_fill2;
#endif
};
@@ -3794,527 +4131,563 @@ struct doorbell
/*
* doorbell message sent to the chip
*/
-struct doorbell_set_prod
-{
+struct doorbell_set_prod {
#if defined(__BIG_ENDIAN)
- uint16_t prod /* Producer index to be set */;
- uint8_t zero_fill1 /* driver must zero this field! */;
+ uint16_t prod;
+ uint8_t zero_fill1;
struct doorbell_hdr header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr header;
- uint8_t zero_fill1 /* driver must zero this field! */;
- uint16_t prod /* Producer index to be set */;
+ uint8_t zero_fill1;
+ uint16_t prod;
#endif
};
-struct regpair
-{
- uint32_t lo /* low word for reg-pair */;
- uint32_t hi /* high word for reg-pair */;
+struct regpair {
+ __le32 lo;
+ __le32 hi;
};
-struct regpair_native
-{
- uint32_t lo /* low word for reg-pair */;
- uint32_t hi /* high word for reg-pair */;
+struct regpair_native {
+ uint32_t lo;
+ uint32_t hi;
};
/*
* Classify rule opcodes in E2/E3
*/
-enum classify_rule
-{
- CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */,
- CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */,
- CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */,
+enum classify_rule {
+ CLASSIFY_RULE_OPCODE_MAC,
+ CLASSIFY_RULE_OPCODE_VLAN,
+ CLASSIFY_RULE_OPCODE_PAIR,
+ CLASSIFY_RULE_OPCODE_IMAC_VNI,
MAX_CLASSIFY_RULE};
/*
* Classify rule types in E2/E3
*/
-enum classify_rule_action_type
-{
+enum classify_rule_action_type {
CLASSIFY_RULE_REMOVE,
CLASSIFY_RULE_ADD,
MAX_CLASSIFY_RULE_ACTION_TYPE};
/*
- * client init ramrod data $$KEEP_ENDIANNESS$$
+ * client init ramrod data
*/
-struct client_init_general_data
-{
- uint8_t client_id /* client_id */;
- uint8_t statistics_counter_id /* statistics counter id */;
- uint8_t statistics_en_flg /* statistics en flg */;
- uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */;
- uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
- uint8_t sp_client_id /* the slow path rings client Id. */;
- uint16_t mtu /* Host MTU from client config */;
- uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */;
- uint8_t func_id /* PCI function ID (0-71) */;
- uint8_t cos /* The connection cos, if applicable */;
+struct client_init_general_data {
+ uint8_t client_id;
+ uint8_t statistics_counter_id;
+ uint8_t statistics_en_flg;
+ uint8_t is_fcoe_flg;
+ uint8_t activate_flg;
+ uint8_t sp_client_id;
+ __le16 mtu;
+ uint8_t statistics_zero_flg;
+ uint8_t func_id;
+ uint8_t cos;
uint8_t traffic_type;
- uint32_t reserved0;
+ uint8_t fp_hsi_ver;
+ uint8_t reserved0[3];
};
/*
- * client init rx data $$KEEP_ENDIANNESS$$
+ * client init rx data
*/
-struct client_init_rx_data
-{
+struct client_init_rx_data {
uint8_t tpa_en;
-#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
-#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
-#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */
+#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
-#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */
-#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
- uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */;
- uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */;
- uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */;
- uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */;
- uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
- uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */;
- uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */;
- uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */;
- uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;
- uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */;
- uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */;
- uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */;
- uint8_t status_block_id /* rx status block id */;
- uint8_t rx_sb_index_number /* status block indices */;
- uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
- uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
- uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
- uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */;
- uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
- uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */;
- uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */;
- struct regpair bd_page_base /* BD page base address at the host */;
- struct regpair sge_page_base /* SGE page base address at the host */;
- struct regpair cqe_page_base /* Completion queue base address */;
+#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE (0x1<<3)
+#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE_SHIFT 3
+#define CLIENT_INIT_RX_DATA_RESERVED5 (0xF<<4)
+#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 4
+ uint8_t vmqueue_mode_en_flg;
+ uint8_t extra_data_over_sgl_en_flg;
+ uint8_t cache_line_alignment_log_size;
+ uint8_t enable_dynamic_hc;
+ uint8_t max_sges_for_packet;
+ uint8_t client_qzone_id;
+ uint8_t drop_ip_cs_err_flg;
+ uint8_t drop_tcp_cs_err_flg;
+ uint8_t drop_ttl0_flg;
+ uint8_t drop_udp_cs_err_flg;
+ uint8_t inner_vlan_removal_enable_flg;
+ uint8_t outer_vlan_removal_enable_flg;
+ uint8_t status_block_id;
+ uint8_t rx_sb_index_number;
+ uint8_t dont_verify_rings_pause_thr_flg;
+ uint8_t max_tpa_queues;
+ uint8_t silent_vlan_removal_flg;
+ __le16 max_bytes_on_bd;
+ __le16 sge_buff_size;
+ uint8_t approx_mcast_engine_id;
+ uint8_t rss_engine_id;
+ struct regpair bd_page_base;
+ struct regpair sge_page_base;
+ struct regpair cqe_page_base;
uint8_t is_leading_rss;
uint8_t is_approx_mcast;
- uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
- uint16_t state;
-#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */
+ __le16 max_agg_size;
+ __le16 state;
+#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
-#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
-#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
-#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */
+#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
-#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
-#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
-#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */
+#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
-#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */
+#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
- uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */;
- uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */;
- uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */;
- uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */;
- uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
- uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
- uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket with will be genratet when this ring is full. for regular flow control set this to 1 */;
- uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
- uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
- uint32_t reserved6[2];
-};
-
-/*
- * client init tx data $$KEEP_ENDIANNESS$$
- */
-struct client_init_tx_data
-{
- uint8_t enforce_security_flg /* if set, security checks will be made for this connection */;
- uint8_t tx_status_block_id /* the number of status block to update */;
- uint8_t tx_sb_index_number /* the index to use inside the status block */;
- uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */;
- uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */;
- uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */;
- uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
- struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */;
- uint16_t state;
-#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */
+ __le16 cqe_pause_thr_low;
+ __le16 cqe_pause_thr_high;
+ __le16 bd_pause_thr_low;
+ __le16 bd_pause_thr_high;
+ __le16 sge_pause_thr_low;
+ __le16 sge_pause_thr_high;
+ __le16 rx_cos_mask;
+ __le16 silent_vlan_value;
+ __le16 silent_vlan_mask;
+ uint8_t handle_ptp_pkts_flg;
+ uint8_t reserved6[3];
+ __le32 reserved7;
+};
+
+/*
+ * client init tx data
+ */
+struct client_init_tx_data {
+ uint8_t enforce_security_flg;
+ uint8_t tx_status_block_id;
+ uint8_t tx_sb_index_number;
+ uint8_t tss_leading_client_id;
+ uint8_t tx_switching_flg;
+ uint8_t anti_spoofing_flg;
+ __le16 default_vlan;
+ struct regpair tx_bd_page_base;
+ __le16 state;
+#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
-#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
-#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
-#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */
+#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
-#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */
+#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
- uint8_t default_vlan_flg /* is default vlan valid for this client. */;
- uint8_t force_default_pri_flg /* if set, force default priority */;
- uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */;
- uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */;
- uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */;
- uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */;
+ uint8_t default_vlan_flg;
+ uint8_t force_default_pri_flg;
+ uint8_t tunnel_lso_inc_ip_id;
+ uint8_t refuse_outband_vlan_flg;
+ uint8_t tunnel_non_lso_pcsum_location;
+ uint8_t tunnel_non_lso_outer_ip_csum_location;
};
/*
- * client init ramrod data $$KEEP_ENDIANNESS$$
+ * client init ramrod data
*/
-struct client_init_ramrod_data
-{
- struct client_init_general_data general /* client init general data */;
- struct client_init_rx_data rx /* client init rx data */;
- struct client_init_tx_data tx /* client init tx data */;
+struct client_init_ramrod_data {
+ struct client_init_general_data general;
+ struct client_init_rx_data rx;
+ struct client_init_tx_data tx;
};
/*
- * client update ramrod data $$KEEP_ENDIANNESS$$
+ * client update ramrod data
*/
-struct client_update_ramrod_data
-{
- uint8_t client_id /* the client to update */;
- uint8_t func_id /* PCI function ID this client belongs to (0-71) */;
- uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */;
- uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */;
- uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */;
- uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */;
- uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */;
- uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */;
- uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
- uint8_t activate_change_flg /* If set, activate_flg will be checked */;
- uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
+struct client_update_ramrod_data {
+ uint8_t client_id;
+ uint8_t func_id;
+ uint8_t inner_vlan_removal_enable_flg;
+ uint8_t inner_vlan_removal_change_flg;
+ uint8_t outer_vlan_removal_enable_flg;
+ uint8_t outer_vlan_removal_change_flg;
+ uint8_t anti_spoofing_enable_flg;
+ uint8_t anti_spoofing_change_flg;
+ uint8_t activate_flg;
+ uint8_t activate_change_flg;
+ __le16 default_vlan;
uint8_t default_vlan_enable_flg;
uint8_t default_vlan_change_flg;
- uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
- uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
- uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
+ __le16 silent_vlan_value;
+ __le16 silent_vlan_mask;
+ uint8_t silent_vlan_removal_flg;
uint8_t silent_vlan_change_flg;
- uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */;
- uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */;
- uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */;
- uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */;
- uint32_t reserved1;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+ uint8_t refuse_outband_vlan_flg;
+ uint8_t refuse_outband_vlan_change_flg;
+ uint8_t tx_switching_flg;
+ uint8_t tx_switching_change_flg;
+ uint8_t handle_ptp_pkts_flg;
+ uint8_t handle_ptp_pkts_change_flg;
+ __le16 reserved1;
+ __le32 echo;
};
/*
* The eth storm context of Cstorm
*/
-struct cstorm_eth_st_context
-{
+struct cstorm_eth_st_context {
uint32_t __reserved0[4];
};
-struct double_regpair
-{
- uint32_t regpair0_lo /* low word for reg-pair0 */;
- uint32_t regpair0_hi /* high word for reg-pair0 */;
- uint32_t regpair1_lo /* low word for reg-pair1 */;
- uint32_t regpair1_hi /* high word for reg-pair1 */;
+struct double_regpair {
+ uint32_t regpair0_lo;
+ uint32_t regpair0_hi;
+ uint32_t regpair1_lo;
+ uint32_t regpair1_hi;
};
/*
- * Ethernet address types used in ethernet tx BDs
+ * 2nd parse bd type used in ethernet tx BDs
+ */
+enum eth_2nd_parse_bd_type {
+ ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
+ MAX_ETH_2ND_PARSE_BD_TYPE};
+
+
+/*
+ * Ethernet address typesm used in ethernet tx BDs
*/
-enum eth_addr_type
-{
+enum eth_addr_type {
UNKNOWN_ADDRESS,
UNICAST_ADDRESS,
MULTICAST_ADDRESS,
BROADCAST_ADDRESS,
- MAX_ETH_ADDR_TYPE
-};
+ MAX_ETH_ADDR_TYPE};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct eth_classify_cmd_header
-{
+struct eth_classify_cmd_header {
uint8_t cmd_general_data;
-#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
-#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
-#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */
+#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
-#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */
+#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
-#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */
+#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
- uint8_t func_id /* the function id */;
+ uint8_t func_id;
uint8_t client_id;
uint8_t reserved1;
};
/*
- * header for eth classification config ramrod $$KEEP_ENDIANNESS$$
+ * header for eth classification config ramrod
*/
-struct eth_classify_header
-{
- uint8_t rule_cnt /* number of rules in classification config ramrod */;
- uint8_t reserved0;
- uint16_t reserved1;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+struct eth_classify_header {
+ uint8_t rule_cnt;
+ uint8_t warning_on_error;
+ __le16 reserved1;
+ __le32 echo;
};
/*
- * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a Inner-MAC/VNI classification rule
*/
-struct eth_classify_mac_cmd
-{
+struct eth_classify_imac_vni_cmd {
struct eth_classify_cmd_header header;
- uint16_t reserved0;
- uint16_t inner_mac;
- uint16_t mac_lsb;
- uint16_t mac_mid;
- uint16_t mac_msb;
- uint16_t reserved1;
+ __le32 vni;
+ __le16 imac_lsb;
+ __le16 imac_mid;
+ __le16 imac_msb;
+ __le16 reserved1;
};
/*
- * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a MAC classification rule
*/
-struct eth_classify_pair_cmd
-{
+struct eth_classify_mac_cmd {
struct eth_classify_cmd_header header;
- uint16_t reserved0;
- uint16_t inner_mac;
- uint16_t mac_lsb;
- uint16_t mac_mid;
- uint16_t mac_msb;
- uint16_t vlan;
+ __le16 reserved0;
+ __le16 inner_mac;
+ __le16 mac_lsb;
+ __le16 mac_mid;
+ __le16 mac_msb;
+ __le16 reserved1;
};
/*
- * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a MAC-VLAN pair classification rule
*/
-struct eth_classify_vlan_cmd
-{
+struct eth_classify_pair_cmd {
struct eth_classify_cmd_header header;
- uint32_t reserved0;
- uint32_t reserved1;
- uint16_t reserved2;
- uint16_t vlan;
+ __le16 reserved0;
+ __le16 inner_mac;
+ __le16 mac_lsb;
+ __le16 mac_mid;
+ __le16 mac_msb;
+ __le16 vlan;
+};
+
+
+/*
+ * Command for adding/removing a VLAN classification rule
+ */
+struct eth_classify_vlan_cmd {
+ struct eth_classify_cmd_header header;
+ __le32 reserved0;
+ __le32 reserved1;
+ __le16 reserved2;
+ __le16 vlan;
};
/*
- * union for eth classification rule $$KEEP_ENDIANNESS$$
+ * union for eth classification rule
*/
-union eth_classify_rule_cmd
-{
+union eth_classify_rule_cmd {
struct eth_classify_mac_cmd mac;
struct eth_classify_vlan_cmd vlan;
struct eth_classify_pair_cmd pair;
+ struct eth_classify_imac_vni_cmd imac_vni;
};
/*
- * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
+ * parameters for eth classification configuration ramrod
*/
-struct eth_classify_rules_ramrod_data
-{
+struct eth_classify_rules_ramrod_data {
struct eth_classify_header header;
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
};
/*
- * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$
+ * The data contain client ID need to the ramrod
*/
-struct eth_common_ramrod_data
-{
- uint32_t client_id /* id of this client. (5 bits are used) */;
- uint32_t reserved1;
+struct eth_common_ramrod_data {
+ __le32 client_id;
+ __le32 reserved1;
};
/*
* The eth storm context of Ustorm
*/
-struct ustorm_eth_st_context
-{
+struct ustorm_eth_st_context {
uint32_t reserved0[52];
};
/*
* The eth storm context of Tstorm
*/
-struct tstorm_eth_st_context
-{
+struct tstorm_eth_st_context {
uint32_t __reserved0[28];
};
/*
* The eth storm context of Xstorm
*/
-struct xstorm_eth_st_context
-{
+struct xstorm_eth_st_context {
uint32_t reserved0[60];
};
/*
* Ethernet connection context
*/
-struct eth_context
-{
- struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */;
- struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */;
- struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */;
- struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */;
- struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */;
- struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */;
- struct timers_block_context timers_context /* Timers block context */;
- struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */;
- struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */;
+struct eth_context {
+ struct ustorm_eth_st_context ustorm_st_context;
+ struct tstorm_eth_st_context tstorm_st_context;
+ struct xstorm_eth_ag_context xstorm_ag_context;
+ struct tstorm_eth_ag_context tstorm_ag_context;
+ struct cstorm_eth_ag_context cstorm_ag_context;
+ struct ustorm_eth_ag_context ustorm_ag_context;
+ struct timers_block_context timers_context;
+ struct xstorm_eth_st_context xstorm_st_context;
+ struct cstorm_eth_st_context cstorm_st_context;
};
/*
* union for sgl and raw data.
*/
-union eth_sgl_or_raw_data
-{
- uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */;
- uint32_t raw_data[4] /* raw data from Tstorm to the driver. */;
+union eth_sgl_or_raw_data {
+ __le16 sgl[8];
+ uint32_t raw_data[4];
};
/*
- * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$
+ * eth FP end aggregation CQE parameters struct
*/
-struct eth_end_agg_rx_cqe
-{
+struct eth_end_agg_rx_cqe {
uint8_t type_error_flags;
-#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
+#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
-#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
+#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
-#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */
+#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
uint8_t reserved1;
- uint8_t queue_index /* The aggregation queue index of this packet */;
+ uint8_t queue_index;
uint8_t reserved2;
- uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */;
- uint16_t num_of_coalesced_segs /* Num of coalesced segments. */;
- uint16_t pkt_len /* Packet length */;
- uint8_t pure_ack_count /* Number of pure acks coalesced. */;
+ __le32 timestamp_delta;
+ __le16 num_of_coalesced_segs;
+ __le16 pkt_len;
+ uint8_t pure_ack_count;
uint8_t reserved3;
- uint16_t reserved4;
- union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
- uint32_t reserved5[8];
+ __le16 reserved4;
+ union eth_sgl_or_raw_data sgl_or_raw_data;
+ __le32 padding[8];
};
+/*
+ * Ethernet error code
+ */
+enum eth_error_code {
+ ETH_OK=0x00,
+ ETH_RAMROD_DATA_READ_ERROR=0x01,
+ ETH_FILTERS_FUNC_NOT_ENABLED,
+ ETH_FILTERS_MAC_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_MAC_DEL_FAIL_NOF,
+ ETH_FILTERS_PAIR_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_PAIR_DEL_FAIL_NOF,
+ ETH_FILTERS_VLAN_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_VLAN_ADD_FAIL_DUP_TT,
+ ETH_FILTERS_VLAN_DEL_FAIL_NOF,
+ ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT,
+ ETH_FILTERS_VLAN_DEL_FAIL_NO_VLAN,
+ ETH_FILTERS_IMAC_VNI_ADD_UNALLOWED_IN_TX,
+ ETH_FILTERS_IMAC_VNI_DEL_UNALLOWED_IN_TX,
+ ETH_FILTERS_IMAC_VNI_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_IMAC_VNI_DEL_FAIL_NOF,
+ MAX_ETH_ERROR_CODE};
/*
- * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$
+ * regular eth FP CQE parameters struct
*/
-struct eth_fast_path_rx_cqe
-{
+struct eth_fast_path_rx_cqe {
uint8_t type_error_flags;
-#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
+#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
+#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
-#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
-#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
-#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
-#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */
-#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
+#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
uint8_t status_flags;
-#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
-#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
-#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
-#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
-#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
- uint8_t queue_index /* The aggregation queue index of this packet */;
- uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */;
- uint32_t rss_hash_result /* RSS toeplitz hash result */;
- uint16_t vlan_tag /* Ethernet VLAN tag field */;
- uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;
- uint16_t len_on_bd /* Number of bytes placed on the BD */;
+ uint8_t queue_index;
+ uint8_t placement_offset;
+ __le32 rss_hash_result;
+ __le16 vlan_tag;
+ __le16 pkt_len_or_gro_seg_len;
+ __le16 len_on_bd;
struct parsing_flags pars_flags;
- union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
- uint32_t reserved1[8];
+ union eth_sgl_or_raw_data sgl_or_raw_data;
+ uint8_t tunn_type;
+ uint8_t tunn_inner_hdrs_offset;
+ __le16 reserved1;
+ __le32 tunn_tenant_id;
+ __le32 padding[5];
+ __le32 marker;
};
/*
- * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$
+ * Command for setting classification flags for a client
*/
-struct eth_filter_rules_cmd
-{
+struct eth_filter_rules_cmd {
uint8_t cmd_general_data;
-#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
-#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
-#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */
+#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
- uint8_t func_id /* the function id */;
- uint8_t client_id /* the client id */;
+ uint8_t func_id;
+ uint8_t client_id;
uint8_t reserved1;
- uint16_t state;
-#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */
+ __le16 state;
+#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
-#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
-#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
-#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */
+#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
-#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
-#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
-#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */
+#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
-#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */
+#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
- uint16_t reserved3;
+ __le16 reserved3;
struct regpair reserved4;
};
/*
- * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$
+ * parameters for eth classification filters ramrod
*/
-struct eth_filter_rules_ramrod_data
-{
+struct eth_filter_rules_ramrod_data {
struct eth_classify_header header;
struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
};
/*
- * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
+ * Hsi version
+ */
+enum eth_fp_hsi_ver {
+ ETH_FP_HSI_VER_0,
+ ETH_FP_HSI_VER_1,
+ ETH_FP_HSI_VER_2,
+ MAX_ETH_FP_HSI_VER};
+
+
+/*
+ * parameters for eth classification configuration ramrod
*/
-struct eth_general_rules_ramrod_data
-{
+struct eth_general_rules_ramrod_data {
struct eth_classify_header header;
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
};
@@ -4323,38 +4696,36 @@ struct eth_general_rules_ramrod_data
/*
* The data for Halt ramrod
*/
-struct eth_halt_ramrod_data
-{
- uint32_t client_id /* id of this client. (5 bits are used) */;
- uint32_t reserved0;
+struct eth_halt_ramrod_data {
+ __le32 client_id;
+ __le32 reserved0;
};
/*
* destination and source mac address.
*/
-struct eth_mac_addresses
-{
+struct eth_mac_addresses {
#if defined(__BIG_ENDIAN)
- uint16_t dst_mid /* destination mac address 16 middle bits */;
- uint16_t dst_lo /* destination mac address 16 low bits */;
+ __le16 dst_mid;
+ __le16 dst_lo;
#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_lo /* destination mac address 16 low bits */;
- uint16_t dst_mid /* destination mac address 16 middle bits */;
+ __le16 dst_lo;
+ __le16 dst_mid;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t src_lo /* source mac address 16 low bits */;
- uint16_t dst_hi /* destination mac address 16 high bits */;
+ __le16 src_lo;
+ __le16 dst_hi;
#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_hi /* destination mac address 16 high bits */;
- uint16_t src_lo /* source mac address 16 low bits */;
+ __le16 dst_hi;
+ __le16 src_lo;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t src_hi /* source mac address 16 high bits */;
- uint16_t src_mid /* source mac address 16 middle bits */;
+ __le16 src_hi;
+ __le16 src_mid;
#elif defined(__LITTLE_ENDIAN)
- uint16_t src_mid /* source mac address 16 middle bits */;
- uint16_t src_hi /* source mac address 16 high bits */;
+ __le16 src_mid;
+ __le16 src_hi;
#endif
};
@@ -4362,78 +4733,54 @@ struct eth_mac_addresses
/*
* tunneling related data.
*/
-struct eth_tunnel_data
-{
-#if defined(__BIG_ENDIAN)
- uint16_t dst_mid /* destination mac address 16 middle bits */;
- uint16_t dst_lo /* destination mac address 16 low bits */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_lo /* destination mac address 16 low bits */;
- uint16_t dst_mid /* destination mac address 16 middle bits */;
-#endif
-#if defined(__BIG_ENDIAN)
- uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
- uint16_t dst_hi /* destination mac address 16 high bits */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_hi /* destination mac address 16 high bits */;
- uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
-#endif
-#if defined(__BIG_ENDIAN)
+struct eth_tunnel_data {
+ __le16 dst_lo;
+ __le16 dst_mid;
+ __le16 dst_hi;
+ __le16 fw_ip_hdr_csum;
+ __le16 pseudo_csum;
+ uint8_t ip_hdr_start_inner_w;
uint8_t flags;
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
-#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
+#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)
+#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
+#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
- uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
- uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
- uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
- uint8_t flags;
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
-#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
-#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
-#endif
};
/*
* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1).
*/
-union eth_mac_addr_or_tunnel_data
-{
- struct eth_mac_addresses mac_addr /* destination and source mac addresses. */;
- struct eth_tunnel_data tunnel_data /* tunneling related data. */;
+union eth_mac_addr_or_tunnel_data {
+ struct eth_mac_addresses mac_addr;
+ struct eth_tunnel_data tunnel_data;
};
/*
- * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$
+ * Command for setting multicast classification for a client
*/
-struct eth_multicast_rules_cmd
-{
+struct eth_multicast_rules_cmd {
uint8_t cmd_general_data;
-#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
-#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
-#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */
+#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
-#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */
+#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
- uint8_t func_id /* the function id */;
- uint8_t bin_id /* the bin to add this function to (0-255) */;
- uint8_t engine_id /* the approximate multicast engine id */;
- uint32_t reserved2;
+ uint8_t func_id;
+ uint8_t bin_id;
+ uint8_t engine_id;
+ __le32 reserved2;
struct regpair reserved3;
};
/*
- * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$
+ * parameters for multicast classification ramrod
*/
-struct eth_multicast_rules_ramrod_data
-{
+struct eth_multicast_rules_ramrod_data {
struct eth_classify_header header;
struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
};
@@ -4442,17 +4789,15 @@ struct eth_multicast_rules_ramrod_data
/*
* Place holder for ramrods protocol specific data
*/
-struct ramrod_data
-{
- uint32_t data_lo;
- uint32_t data_hi;
+struct ramrod_data {
+ __le32 data_lo;
+ __le32 data_hi;
};
/*
* union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
*/
-union eth_ramrod_data
-{
+union eth_ramrod_data {
struct ramrod_data general;
};
@@ -4460,8 +4805,7 @@ union eth_ramrod_data
/*
* RSS toeplitz hash type, as reported in CQE
*/
-enum eth_rss_hash_type
-{
+enum eth_rss_hash_type {
DEFAULT_HASH_TYPE,
IPV4_HASH_TYPE,
TCP_IPV4_HASH_TYPE,
@@ -4476,100 +4820,100 @@ enum eth_rss_hash_type
/*
* Ethernet RSS mode
*/
-enum eth_rss_mode
-{
+enum eth_rss_mode {
ETH_RSS_MODE_DISABLED,
- ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */,
- ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
- ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */,
- ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */,
- ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */,
+ ETH_RSS_MODE_REGULAR,
+ ETH_RSS_MODE_ESX51,
+ ETH_RSS_MODE_VLAN_PRI,
+ ETH_RSS_MODE_E1HOV_PRI,
+ ETH_RSS_MODE_IP_DSCP,
MAX_ETH_RSS_MODE};
/*
- * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$
+ * parameters for RSS update ramrod (E2)
*/
-struct eth_rss_update_ramrod_data
-{
+struct eth_rss_update_ramrod_data {
uint8_t rss_engine_id;
- uint8_t capabilities;
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */
+ uint8_t rss_mode;
+ __le16 capabilities;
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */
-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
- uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
- uint8_t rss_mode /* The RSS mode for this function */;
- uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
- uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
- uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */;
- uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */;
- uint32_t echo;
- uint32_t reserved3;
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
+#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)
+#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)
+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
+ uint8_t rss_result_mask;
+ uint8_t reserved3;
+ __le16 reserved4;
+ uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
+ __le32 rss_key[T_ETH_RSS_KEY];
+ __le32 echo;
+ __le32 reserved5;
};
/*
* The eth Rx Buffer Descriptor
*/
-struct eth_rx_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
+struct eth_rx_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
};
/*
- * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$
+ * Eth Rx Cqe structure- general structure for ramrods
*/
-struct common_ramrod_eth_rx_cqe
-{
+struct common_ramrod_eth_rx_cqe {
uint8_t ramrod_type;
-#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
-#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */
+#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
-#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
- uint8_t conn_type /* only 3 bits are used */;
- uint16_t reserved1 /* protocol specific data */;
- uint32_t conn_and_cmd_data;
-#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
+ uint8_t conn_type;
+ __le16 reserved1;
+ __le32 conn_and_cmd_data;
+#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
-#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
- struct ramrod_data protocol_data /* protocol specific data */;
- uint32_t echo;
- uint32_t reserved2[11];
+ struct ramrod_data protocol_data;
+ __le32 echo;
+ __le32 reserved2[11];
};
/*
* Rx Last CQE in page (in ETH)
*/
-struct eth_rx_cqe_next_page
-{
- uint32_t addr_lo /* Next page low pointer */;
- uint32_t addr_hi /* Next page high pointer */;
- uint32_t reserved[14];
+struct eth_rx_cqe_next_page {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le32 reserved[14];
};
/*
* union for all eth rx cqe types (fix their sizes)
*/
-union eth_rx_cqe
-{
+union eth_rx_cqe {
struct eth_fast_path_rx_cqe fast_path_cqe;
struct common_ramrod_eth_rx_cqe ramrod_cqe;
struct eth_rx_cqe_next_page next_page_cqe;
@@ -4580,324 +4924,328 @@ union eth_rx_cqe
/*
* Values for RX ETH CQE type field
*/
-enum eth_rx_cqe_type
-{
- RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */,
- RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */,
- RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */,
- RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */,
+enum eth_rx_cqe_type {
+ RX_ETH_CQE_TYPE_ETH_FASTPATH,
+ RX_ETH_CQE_TYPE_ETH_RAMROD,
+ RX_ETH_CQE_TYPE_ETH_START_AGG,
+ RX_ETH_CQE_TYPE_ETH_STOP_AGG,
MAX_ETH_RX_CQE_TYPE};
/*
* Type of SGL/Raw field in ETH RX fast path CQE
*/
-enum eth_rx_fp_sel
-{
- ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */,
- ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */,
+enum eth_rx_fp_sel {
+ ETH_FP_CQE_REGULAR,
+ ETH_FP_CQE_RAW,
MAX_ETH_RX_FP_SEL};
/*
* The eth Rx SGE Descriptor
*/
-struct eth_rx_sge
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
+struct eth_rx_sge {
+ __le32 addr_lo;
+ __le32 addr_hi;
};
/*
- * common data for all protocols $$KEEP_ENDIANNESS$$
+ * common data for all protocols
*/
-struct spe_hdr
-{
- uint32_t conn_and_cmd_data;
-#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
+struct spe_hdr {
+ __le32 conn_and_cmd_data;
+#define SPE_HDR_CID (0xFFFFFF<<0)
#define SPE_HDR_CID_SHIFT 0
-#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */
+#define SPE_HDR_CMD_ID (0xFF<<24)
#define SPE_HDR_CMD_ID_SHIFT 24
- uint16_t type;
-#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */
+ __le16 type;
+#define SPE_HDR_CONN_TYPE (0xFF<<0)
#define SPE_HDR_CONN_TYPE_SHIFT 0
-#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */
+#define SPE_HDR_FUNCTION_ID (0xFF<<8)
#define SPE_HDR_FUNCTION_ID_SHIFT 8
- uint16_t reserved1;
+ __le16 reserved1;
};
/*
* specific data for ethernet slow path element
*/
-union eth_specific_data
-{
- uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
- struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */;
- struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */;
- struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */;
- struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */;
- struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */;
- struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */;
- struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */;
- struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */;
+union eth_specific_data {
+ uint8_t protocol_data[8];
+ struct regpair client_update_ramrod_data;
+ struct regpair client_init_ramrod_init_data;
+ struct eth_halt_ramrod_data halt_ramrod_data;
+ struct regpair update_data_addr;
+ struct eth_common_ramrod_data common_ramrod_data;
+ struct regpair classify_cfg_addr;
+ struct regpair filter_cfg_addr;
+ struct regpair mcast_cfg_addr;
};
/*
* Ethernet slow path element
*/
-struct eth_spe
-{
- struct spe_hdr hdr /* common data for all protocols */;
- union eth_specific_data data /* data specific to ethernet protocol */;
+struct eth_spe {
+ struct spe_hdr hdr;
+ union eth_specific_data data;
};
/*
* Ethernet command ID for slow path elements
*/
-enum eth_spqe_cmd_id
-{
+enum eth_spqe_cmd_id {
RAMROD_CMD_ID_ETH_UNUSED,
- RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */,
- RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */,
- RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */,
- RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */,
- RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */,
- RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */,
- RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */,
- RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */,
- RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */,
- RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */,
+ RAMROD_CMD_ID_ETH_CLIENT_SETUP,
+ RAMROD_CMD_ID_ETH_HALT,
+ RAMROD_CMD_ID_ETH_FORWARD_SETUP,
+ RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
+ RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
+ RAMROD_CMD_ID_ETH_EMPTY,
+ RAMROD_CMD_ID_ETH_TERMINATE,
+ RAMROD_CMD_ID_ETH_TPA_UPDATE,
+ RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
+ RAMROD_CMD_ID_ETH_FILTER_RULES,
+ RAMROD_CMD_ID_ETH_MULTICAST_RULES,
+ RAMROD_CMD_ID_ETH_RSS_UPDATE,
+ RAMROD_CMD_ID_ETH_SET_MAC,
MAX_ETH_SPQE_CMD_ID};
/*
* eth tpa update command
*/
-enum eth_tpa_update_command
-{
- TPA_UPDATE_NONE_COMMAND /* nop command */,
- TPA_UPDATE_ENABLE_COMMAND /* enable command */,
- TPA_UPDATE_DISABLE_COMMAND /* disable command */,
+enum eth_tpa_update_command {
+ TPA_UPDATE_NONE_COMMAND,
+ TPA_UPDATE_ENABLE_COMMAND,
+ TPA_UPDATE_DISABLE_COMMAND,
MAX_ETH_TPA_UPDATE_COMMAND};
/*
* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header
*/
-enum eth_tunnel_lso_inc_ip_id
-{
- EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */,
- INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */,
+enum eth_tunnel_lso_inc_ip_id {
+ EXT_HEADER,
+ INT_HEADER,
MAX_ETH_TUNNEL_LSO_INC_IP_ID};
/*
* In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD.
*/
-enum eth_tunnel_non_lso_csum_location
-{
- CSUM_ON_PKT /* checksum is on the packet. */,
- CSUM_ON_BD /* checksum is on the BD. */,
+enum eth_tunnel_non_lso_csum_location {
+ CSUM_ON_PKT,
+ CSUM_ON_BD,
MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};
/*
- * Tx regular BD structure $$KEEP_ENDIANNESS$$
+ * Packet Tunneling Type
*/
-struct eth_tx_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
- uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */;
- uint16_t nbytes /* Size of the data represented by the BD */;
- uint8_t reserved[4] /* keeps same size as other eth tx bd types */;
+enum eth_tunn_type {
+ TUNN_TYPE_NONE,
+ TUNN_TYPE_VXLAN,
+ TUNN_TYPE_L2_GRE,
+ TUNN_TYPE_IPV4_GRE,
+ TUNN_TYPE_IPV6_GRE,
+ TUNN_TYPE_L2_GENEVE,
+ TUNN_TYPE_IPV4_GENEVE,
+ TUNN_TYPE_IPV6_GENEVE,
+ MAX_ETH_TUNN_TYPE};
+
+
+/*
+ * Tx regular BD structure
+ */
+struct eth_tx_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le16 total_pkt_bytes;
+ __le16 nbytes;
+ uint8_t reserved[4];
};
/*
* structure for easy accessibility to assembler
*/
-struct eth_tx_bd_flags
-{
+struct eth_tx_bd_flags {
uint8_t as_bitfield;
-#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */
+#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
-#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */
+#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
-#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */
+#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
-#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */
+#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
-#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */
+#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
-#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */
+#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
-#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */
+#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
};
/*
- * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$
+ * The eth Tx Buffer Descriptor
*/
-struct eth_tx_start_bd
-{
- uint64_t addr;
- uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */;
- uint16_t nbytes /* Size of the data represented by the BD */;
- uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */;
+struct eth_tx_start_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le16 nbd;
+ __le16 nbytes;
+ __le16 vlan_or_ethertype;
struct eth_tx_bd_flags bd_flags;
uint8_t general_data;
-#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */
+#define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
-#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */
+#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
+#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
+#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
-#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */
+#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
-#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */
+#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
};
/*
- * Tx parsing BD structure for ETH E1h $$KEEP_ENDIANNESS$$
+ * Tx parsing BD structure for ETH E1/E1h
*/
-struct eth_tx_parse_bd_e1x
-{
- uint16_t global_data;
-#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */
+struct eth_tx_parse_bd_e1x {
+ __le16 global_data;
+#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */
+#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
-#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */
+#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
-#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */
+#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
-#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
+#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
-#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */
+#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
uint8_t tcp_flags;
-#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
+#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
-#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
+#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
-#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
+#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
-#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
+#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
-#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
+#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
-#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
+#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
-#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
+#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
-#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
+#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
- uint8_t ip_hlen_w /* IP header length in WORDs */;
- uint16_t total_hlen_w /* IP+TCP+ETH */;
- uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */;
- uint16_t lso_mss /* for LSO mode */;
- uint16_t ip_id /* for LSO mode */;
- uint32_t tcp_send_seq /* for LSO mode */;
+ uint8_t ip_hlen_w;
+ __le16 total_hlen_w;
+ __le16 tcp_pseudo_csum;
+ __le16 lso_mss;
+ __le16 ip_id;
+ __le32 tcp_send_seq;
};
/*
- * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$
+ * Tx parsing BD structure for ETH E2
*/
-struct eth_tx_parse_bd_e2
-{
- union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */;
- uint32_t parsing_data;
-#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */
+struct eth_tx_parse_bd_e2 {
+ union eth_mac_addr_or_tunnel_data data;
+ __le32 parsing_data;
+#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */
+#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
-#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */
+#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
-#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */
+#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
-#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */
+#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
};
/*
- * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$
+ * Tx 2nd parsing BD structure for ETH packet
*/
-struct eth_tx_parse_2nd_bd
-{
- uint16_t global_data;
-#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */
+struct eth_tx_parse_2nd_bd {
+ __le16 global_data;
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
-#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */
+#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
-#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */
+#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
-#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
+#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
-#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */
+#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
-#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
-#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */
+#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
- uint16_t reserved2;
+ uint8_t bd_type;
+#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
+#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
+#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
+#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
+ uint8_t reserved3;
uint8_t tcp_flags;
-#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
+#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
-#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
+#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
-#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
+#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
-#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
+#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
-#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
+#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
-#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
+#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
-#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
+#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
-#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
+#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
- uint8_t reserved3;
- uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */;
- uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */;
- uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */;
- uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */;
- uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */;
+ uint8_t reserved4;
+ uint8_t tunnel_udp_hdr_start_w;
+ uint8_t fw_ip_hdr_to_payload_w;
+ __le16 fw_ip_csum_wo_len_flags_frag;
+ __le16 hw_ip_id;
+ __le32 tcp_send_seq;
};
/*
* The last BD in the BD memory will hold a pointer to the next BD memory
*/
-struct eth_tx_next_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
- uint8_t reserved[8] /* keeps same size as other eth tx bd types */;
+struct eth_tx_next_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ uint8_t reserved[8];
};
/*
* union for 4 Bd types
*/
-union eth_tx_bd_types
-{
- struct eth_tx_start_bd start_bd /* the first bd in a packets */;
- struct eth_tx_bd reg_bd /* the common bd */;
- struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */;
- struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */;
- struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */;
- struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */;
+union eth_tx_bd_types {
+ struct eth_tx_start_bd start_bd;
+ struct eth_tx_bd reg_bd;
+ struct eth_tx_parse_bd_e1x parse_bd_e1x;
+ struct eth_tx_parse_bd_e2 parse_bd_e2;
+ struct eth_tx_parse_2nd_bd parse_2nd_bd;
+ struct eth_tx_next_bd next_bd;
};
/*
* array of 13 bds as appears in the eth xstorm context
*/
-struct eth_tx_bds_array
-{
+struct eth_tx_bds_array {
union eth_tx_bd_types bds[13];
};
@@ -4905,79 +5253,73 @@ struct eth_tx_bds_array
/*
* VLAN mode on TX BDs
*/
-enum eth_tx_vlan_type
-{
+enum eth_tx_vlan_type {
X_ETH_NO_VLAN,
X_ETH_OUTBAND_VLAN,
X_ETH_INBAND_VLAN,
- X_ETH_FW_ADDED_VLAN /* Driver should not use this! */,
+ X_ETH_FW_ADDED_VLAN,
MAX_ETH_TX_VLAN_TYPE};
/*
* Ethernet VLAN filtering mode in E1x
*/
-enum eth_vlan_filter_mode
-{
- ETH_VLAN_FILTER_ANY_VLAN /* Don't filter by vlan */,
- ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */,
- ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */,
+enum eth_vlan_filter_mode {
+ ETH_VLAN_FILTER_ANY_VLAN,
+ ETH_VLAN_FILTER_SPECIFIC_VLAN,
+ ETH_VLAN_FILTER_CLASSIFY,
MAX_ETH_VLAN_FILTER_MODE};
/*
- * MAC filtering configuration command header $$KEEP_ENDIANNESS$$
+ * MAC filtering configuration command header
*/
-struct mac_configuration_hdr
-{
- uint8_t length /* number of entries valid in this command (6 bits) */;
- uint8_t offset /* offset of the first entry in the list */;
- uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+struct mac_configuration_hdr {
+ uint8_t length;
+ uint8_t offset;
+ __le16 client_id;
+ __le32 echo;
};
/*
- * MAC address in list for ramrod $$KEEP_ENDIANNESS$$
+ * MAC address in list for ramrod
*/
-struct mac_configuration_entry
-{
- uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */;
- uint8_t pf_id /* The pf id, for multi function mode */;
+struct mac_configuration_entry {
+ __le16 lsb_mac_addr;
+ __le16 middle_mac_addr;
+ __le16 msb_mac_addr;
+ __le16 vlan_id;
+ uint8_t pf_id;
uint8_t flags;
-#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */
+#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
-#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */
+#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
-#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */
+#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
-#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - can't remove vlan 1 - can remove vlan. relevant only to everest1 */
+#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
-#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */
+#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
-#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */
+#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
- uint16_t reserved0;
- uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */;
+ __le16 reserved0;
+ __le32 clients_bit_vector;
};
/*
* MAC filtering configuration command
*/
-struct mac_configuration_cmd
-{
- struct mac_configuration_hdr hdr /* header */;
- struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */;
+struct mac_configuration_cmd {
+ struct mac_configuration_hdr hdr;
+ struct mac_configuration_entry config_table[64];
};
/*
* Set-MAC command type (in E1x)
*/
-enum set_mac_action_type
-{
+enum set_mac_action_type {
T_ETH_MAC_COMMAND_INVALIDATE,
T_ETH_MAC_COMMAND_SET,
MAX_SET_MAC_ACTION_TYPE};
@@ -4986,160 +5328,211 @@ enum set_mac_action_type
/*
* Ethernet TPA Modes
*/
-enum tpa_mode
-{
- TPA_LRO /* LRO mode TPA */,
- TPA_GRO /* GRO mode TPA */,
+enum tpa_mode {
+ TPA_LRO,
+ TPA_GRO,
MAX_TPA_MODE};
/*
- * tpa update ramrod data $$KEEP_ENDIANNESS$$
+ * tpa update ramrod data
*/
-struct tpa_update_ramrod_data
-{
- uint8_t update_ipv4 /* none, enable or disable */;
- uint8_t update_ipv6 /* none, enable or disable */;
- uint8_t client_id /* client init flow control data */;
- uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
- uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
- uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */;
- uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
- uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */;
- uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
- uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
- uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */;
- uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */;
- uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
- uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
+struct tpa_update_ramrod_data {
+ uint8_t update_ipv4;
+ uint8_t update_ipv6;
+ uint8_t client_id;
+ uint8_t max_tpa_queues;
+ uint8_t max_sges_for_packet;
+ uint8_t complete_on_both_clients;
+ uint8_t dont_verify_rings_pause_thr_flg;
+ uint8_t tpa_mode;
+ __le16 sge_buff_size;
+ __le16 max_agg_size;
+ __le32 sge_page_base_lo;
+ __le32 sge_page_base_hi;
+ __le16 sge_pause_thr_low;
+ __le16 sge_pause_thr_high;
+ uint8_t tpa_over_vlan_disable;
+ uint8_t reserved[7];
};
/*
* approximate-match multicast filtering for E1H per function in Tstorm
*/
-struct tstorm_eth_approximate_match_multicast_filtering
-{
- uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */;
+struct tstorm_eth_approximate_match_multicast_filtering {
+ uint32_t mcast_add_hash_bit_array[8];
};
/*
- * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$
+ * Common configuration parameters per function in Tstorm
*/
-struct tstorm_eth_function_common_config
-{
- uint16_t config_flags;
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
+struct tstorm_eth_function_common_config {
+ __le16 config_flags;
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Don't filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
- uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
+ uint8_t rss_result_mask;
uint8_t reserved1;
- uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */;
+ __le16 vlan_id[2];
};
/*
- * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$
+ * MAC filtering configuration parameters per port in Tstorm
*/
-struct tstorm_eth_mac_filter_config
-{
- uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */;
- uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */;
- uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */;
- uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */;
- uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */;
- uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. The primary vlan is taken from the CAM target table. */;
- uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */;
+struct tstorm_eth_mac_filter_config {
+ uint32_t ucast_drop_all;
+ uint32_t ucast_accept_all;
+ uint32_t mcast_drop_all;
+ uint32_t mcast_accept_all;
+ uint32_t bcast_accept_all;
+ uint32_t vlan_filter[2];
+ uint32_t unmatched_unicast;
};
/*
- * tx only queue init ramrod data $$KEEP_ENDIANNESS$$
+ * tx only queue init ramrod data
*/
-struct tx_queue_init_ramrod_data
-{
- struct client_init_general_data general /* client init general data */;
- struct client_init_tx_data tx /* client init tx data */;
+struct tx_queue_init_ramrod_data {
+ struct client_init_general_data general;
+ struct client_init_tx_data tx;
};
/*
* Three RX producers for ETH
*/
-union ustorm_eth_rx_producers
-{
- struct {
+struct ustorm_eth_rx_producers {
#if defined(__BIG_ENDIAN)
- uint16_t bd_prod /* Producer of the RX BD ring */;
- uint16_t cqe_prod /* Producer of the RX CQE ring */;
+ uint16_t bd_prod;
+ uint16_t cqe_prod;
#elif defined(__LITTLE_ENDIAN)
- uint16_t cqe_prod /* Producer of the RX CQE ring */;
- uint16_t bd_prod /* Producer of the RX BD ring */;
+ uint16_t cqe_prod;
+ uint16_t bd_prod;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t reserved;
- uint16_t sge_prod /* Producer of the RX SGE ring */;
+ uint16_t reserved;
+ uint16_t sge_prod;
#elif defined(__LITTLE_ENDIAN)
- uint16_t sge_prod /* Producer of the RX SGE ring */;
- uint16_t reserved;
+ uint16_t sge_prod;
+ uint16_t reserved;
#endif
- } prod;
- uint32_t raw_data[2];
};
/*
- * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$
+ * FCoE RX statistics parameters section#0
+ */
+struct fcoe_rx_stat_params_section0 {
+ __le32 fcoe_rx_pkt_cnt;
+ __le32 fcoe_rx_byte_cnt;
+};
+
+
+/*
+ * FCoE RX statistics parameters section#1
+ */
+struct fcoe_rx_stat_params_section1 {
+ __le32 fcoe_ver_cnt;
+ __le32 fcoe_rx_drop_pkt_cnt;
+};
+
+
+/*
+ * FCoE RX statistics parameters section#2
+ */
+struct fcoe_rx_stat_params_section2 {
+ __le32 fc_crc_cnt;
+ __le32 eofa_del_cnt;
+ __le32 miss_frame_cnt;
+ __le32 seq_timeout_cnt;
+ __le32 drop_seq_cnt;
+ __le32 fcoe_rx_drop_pkt_cnt;
+ __le32 fcp_rx_pkt_cnt;
+ __le32 reserved0;
+};
+
+
+/*
+ * FCoE TX statistics parameters
+ */
+struct fcoe_tx_stat_params {
+ __le32 fcoe_tx_pkt_cnt;
+ __le32 fcoe_tx_byte_cnt;
+ __le32 fcp_tx_pkt_cnt;
+ __le32 reserved0;
+};
+
+/*
+ * FCoE statistics parameters
+ */
+struct fcoe_statistics_params {
+ struct fcoe_tx_stat_params tx_stat;
+ struct fcoe_rx_stat_params_section0 rx_stat0;
+ struct fcoe_rx_stat_params_section1 rx_stat1;
+ struct fcoe_rx_stat_params_section2 rx_stat2;
+};
+
+
+/*
+ * The data afex vif list ramrod need
*/
-struct afex_vif_list_ramrod_data
-{
- uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */;
- uint8_t func_bit_map /* the function bit map to set */;
- uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */;
- uint8_t func_to_clear /* the func id to clear in case of clear func mode */;
+struct afex_vif_list_ramrod_data {
+ uint8_t afex_vif_list_command;
+ uint8_t func_bit_map;
+ __le16 vif_list_index;
+ uint8_t func_to_clear;
uint8_t echo;
- uint16_t reserved1;
+ __le16 reserved1;
};
/*
- * cfc delete event data $$KEEP_ENDIANNESS$$
+ *
*/
-struct cfc_del_event_data
-{
- uint32_t cid /* cid of deleted connection */;
- uint32_t reserved0;
- uint32_t reserved1;
+struct c2s_pri_trans_table_entry {
+ uint8_t val[8];
+};
+
+
+/*
+ * cfc delete event data
+ */
+struct cfc_del_event_data {
+ __le32 cid;
+ __le32 reserved0;
+ __le32 reserved1;
};
/*
* per-port SAFC demo variables
*/
-struct cmng_flags_per_port
-{
+struct cmng_flags_per_port {
uint32_t cmng_enables;
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
-#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
-#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */
+#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
uint32_t __reserved1;
};
@@ -5148,46 +5541,42 @@ struct cmng_flags_per_port
/*
* per-port rate shaping variables
*/
-struct rate_shaping_vars_per_port
-{
- uint32_t rs_periodic_timeout /* timeout of periodic timer */;
- uint32_t rs_threshold /* threshold, below which we start to stop queues */;
+struct rate_shaping_vars_per_port {
+ uint32_t rs_periodic_timeout;
+ uint32_t rs_threshold;
};
/*
* per-port fairness variables
*/
-struct fairness_vars_per_port
-{
- uint32_t upper_bound /* Quota for a protocol/vnic */;
- uint32_t fair_threshold /* almost-empty threshold */;
- uint32_t fairness_timeout /* timeout of fairness timer */;
- uint32_t reserved0;
+struct fairness_vars_per_port {
+ uint32_t upper_bound;
+ uint32_t fair_threshold;
+ uint32_t fairness_timeout;
+ uint32_t size_thr;
};
/*
* per-port SAFC variables
*/
-struct safc_struct_per_port
-{
+struct safc_struct_per_port {
#if defined(__BIG_ENDIAN)
uint16_t __reserved1;
uint8_t __reserved0;
- uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
+ uint8_t safc_timeout_usec;
#elif defined(__LITTLE_ENDIAN)
- uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
+ uint8_t safc_timeout_usec;
uint8_t __reserved0;
uint16_t __reserved1;
#endif
- uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */;
- uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */;
+ uint8_t cos_to_traffic_types[MAX_COS_NUMBER];
+ uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS];
};
/*
* Per-port congestion management variables
*/
-struct cmng_struct_per_port
-{
+struct cmng_struct_per_port {
struct rate_shaping_vars_per_port rs_vars;
struct fairness_vars_per_port fair_vars;
struct safc_struct_per_port safc_vars;
@@ -5197,14 +5586,13 @@ struct cmng_struct_per_port
/*
* a single rate shaping counter. can be used as protocol or vnic counter
*/
-struct rate_shaping_counter
-{
- uint32_t quota /* Quota for a protocol/vnic */;
+struct rate_shaping_counter {
+ uint32_t quota;
#if defined(__BIG_ENDIAN)
uint16_t __reserved0;
- uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
+ uint16_t rate;
#elif defined(__LITTLE_ENDIAN)
- uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
+ uint16_t rate;
uint16_t __reserved0;
#endif
};
@@ -5212,26 +5600,23 @@ struct rate_shaping_counter
/*
* per-vnic rate shaping variables
*/
-struct rate_shaping_vars_per_vn
-{
- struct rate_shaping_counter vn_counter /* per-vnic counter */;
+struct rate_shaping_vars_per_vn {
+ struct rate_shaping_counter vn_counter;
};
/*
* per-vnic fairness variables
*/
-struct fairness_vars_per_vn
-{
- uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */;
- uint32_t vn_credit_delta /* used for incrementing the credit */;
+struct fairness_vars_per_vn {
+ uint32_t cos_credit_delta[MAX_COS_NUMBER];
+ uint32_t vn_credit_delta;
uint32_t __reserved0;
};
/*
* cmng port init state
*/
-struct cmng_vnic
-{
+struct cmng_vnic {
struct rate_shaping_vars_per_vn vnic_max_rate[4];
struct fairness_vars_per_vn vnic_min_rate[4];
};
@@ -5239,8 +5624,7 @@ struct cmng_vnic
/*
* cmng port init state
*/
-struct cmng_init
-{
+struct cmng_init {
struct cmng_struct_per_port port;
struct cmng_vnic vnic;
};
@@ -5249,12 +5633,13 @@ struct cmng_init
/*
* driver parameters for congestion management init, all rates are in Mbps
*/
-struct cmng_init_input
-{
+struct cmng_init_input {
uint32_t port_rate;
- uint16_t vnic_min_rate[4] /* rates are in Mbps */;
- uint16_t vnic_max_rate[4] /* rates are in Mbps */;
- uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */;
+ uint32_t size_thr;
+ uint32_t fairness_thr;
+ uint16_t vnic_min_rate[4];
+ uint16_t vnic_max_rate[4];
+ uint16_t cos_min_rate[MAX_COS_NUMBER];
uint16_t cos_to_pause_mask[MAX_COS_NUMBER];
struct cmng_flags_per_port flags;
};
@@ -5263,64 +5648,59 @@ struct cmng_init_input
/*
* Protocol-common command ID for slow path elements
*/
-enum common_spqe_cmd_id
-{
+enum common_spqe_cmd_id {
RAMROD_CMD_ID_COMMON_UNUSED,
- RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */,
- RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */,
- RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */,
- RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */,
- RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
- RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */,
- RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
- RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
- RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */,
- RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
+ RAMROD_CMD_ID_COMMON_FUNCTION_START,
+ RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
+ RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
+ RAMROD_CMD_ID_COMMON_CFC_DEL,
+ RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
+ RAMROD_CMD_ID_COMMON_STAT_QUERY,
+ RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
+ RAMROD_CMD_ID_COMMON_START_TRAFFIC,
+ RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
+ RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
MAX_COMMON_SPQE_CMD_ID};
/*
* Per-protocol connection types
*/
-enum connection_type
-{
- ETH_CONNECTION_TYPE /* Ethernet */,
- TOE_CONNECTION_TYPE /* TOE */,
- RDMA_CONNECTION_TYPE /* RDMA */,
- ISCSI_CONNECTION_TYPE /* iSCSI */,
- FCOE_CONNECTION_TYPE /* FCoE */,
+enum connection_type {
+ ETH_CONNECTION_TYPE,
+ TOE_CONNECTION_TYPE,
+ RDMA_CONNECTION_TYPE,
+ ISCSI_CONNECTION_TYPE,
+ FCOE_CONNECTION_TYPE,
RESERVED_CONNECTION_TYPE_0,
RESERVED_CONNECTION_TYPE_1,
RESERVED_CONNECTION_TYPE_2,
- NONE_CONNECTION_TYPE /* General- used for common slow path */,
+ NONE_CONNECTION_TYPE,
MAX_CONNECTION_TYPE};
/*
* Cos modes
*/
-enum cos_mode
-{
- OVERRIDE_COS /* Firmware deduce cos according to DCB */,
- STATIC_COS /* Firmware has constant queues per CoS */,
- FW_WRR /* Firmware keep fairness between different CoSes */,
+enum cos_mode {
+ OVERRIDE_COS,
+ STATIC_COS,
+ FW_WRR,
MAX_COS_MODE};
/*
* Dynamic HC counters set by the driver
*/
-struct hc_dynamic_drv_counter
-{
- uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */;
+struct hc_dynamic_drv_counter {
+ uint32_t val[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* zone A per-queue data
*/
-struct cstorm_queue_zone_data
-{
- struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */;
+struct cstorm_queue_zone_data {
+ struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
struct regpair reserved[2];
};
@@ -5328,120 +5708,106 @@ struct cstorm_queue_zone_data
/*
* Vf-PF channel data in cstorm ram (non-triggered zone)
*/
-struct vf_pf_channel_zone_data
-{
- uint32_t msg_addr_lo /* the message address on VF memory */;
- uint32_t msg_addr_hi /* the message address on VF memory */;
+struct vf_pf_channel_zone_data {
+ uint32_t msg_addr_lo;
+ uint32_t msg_addr_hi;
};
/*
* zone for VF non-triggered data
*/
-struct non_trigger_vf_zone
-{
- struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */;
+struct non_trigger_vf_zone {
+ struct vf_pf_channel_zone_data vf_pf_channel;
};
/*
* Vf-PF channel trigger zone in cstorm ram
*/
-struct vf_pf_channel_zone_trigger
-{
- uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */;
+struct vf_pf_channel_zone_trigger {
+ uint8_t addr_valid;
};
/*
* zone that triggers the in-bound interrupt
*/
-struct trigger_vf_zone
-{
-#if defined(__BIG_ENDIAN)
- uint16_t reserved1;
- uint8_t reserved0;
- struct vf_pf_channel_zone_trigger vf_pf_channel;
-#elif defined(__LITTLE_ENDIAN)
+struct trigger_vf_zone {
struct vf_pf_channel_zone_trigger vf_pf_channel;
uint8_t reserved0;
uint16_t reserved1;
-#endif
uint32_t reserved2;
};
/*
* zone B per-VF data
*/
-struct cstorm_vf_zone_data
-{
- struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */;
- struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */;
+struct cstorm_vf_zone_data {
+ struct non_trigger_vf_zone non_trigger;
+ struct trigger_vf_zone trigger;
};
/*
* Dynamic host coalescing init parameters, per state machine
*/
-struct dynamic_hc_sm_config
-{
- uint32_t threshold[3] /* thresholds of number of outstanding bytes */;
- uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */;
- uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */;
- uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */;
- uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */;
- uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */;
+struct dynamic_hc_sm_config {
+ uint32_t threshold[3];
+ uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* Dynamic host coalescing init parameters
*/
-struct dynamic_hc_config
-{
- struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */;
+struct dynamic_hc_config {
+ struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
};
-struct e2_integ_data
-{
+struct e2_integ_data {
#if defined(__BIG_ENDIAN)
uint8_t flags;
-#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
+#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
-#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
+#define E2_INTEG_DATA_LB_TX (0x1<<1)
#define E2_INTEG_DATA_LB_TX_SHIFT 1
-#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
+#define E2_INTEG_DATA_COS_TX (0x1<<2)
#define E2_INTEG_DATA_COS_TX_SHIFT 2
-#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
-#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
-#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
+#define E2_INTEG_DATA_RESERVED (0x7<<5)
#define E2_INTEG_DATA_RESERVED_SHIFT 5
- uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
- uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
+ uint8_t cos;
+ uint8_t voq;
+ uint8_t pbf_queue;
#elif defined(__LITTLE_ENDIAN)
- uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
+ uint8_t pbf_queue;
+ uint8_t voq;
+ uint8_t cos;
uint8_t flags;
-#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
+#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
-#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
+#define E2_INTEG_DATA_LB_TX (0x1<<1)
#define E2_INTEG_DATA_LB_TX_SHIFT 1
-#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
+#define E2_INTEG_DATA_COS_TX (0x1<<2)
#define E2_INTEG_DATA_COS_TX_SHIFT 2
-#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
-#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
-#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
+#define E2_INTEG_DATA_RESERVED (0x7<<5)
#define E2_INTEG_DATA_RESERVED_SHIFT 5
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3;
uint8_t reserved2;
- uint8_t ramEn /* context area reserved for reading enable bit from ram */;
+ uint8_t ramEn;
#elif defined(__LITTLE_ENDIAN)
- uint8_t ramEn /* context area reserved for reading enable bit from ram */;
+ uint8_t ramEn;
uint8_t reserved2;
uint16_t reserved3;
#endif
@@ -5449,333 +5815,320 @@ struct e2_integ_data
/*
- * set mac event data $$KEEP_ENDIANNESS$$
+ * set mac event data
*/
-struct eth_event_data
-{
- uint32_t echo /* set mac echo data to return to driver */;
- uint32_t reserved0;
- uint32_t reserved1;
+struct eth_event_data {
+ __le32 echo;
+ __le32 reserved0;
+ __le32 reserved1;
};
/*
- * pf-vf event data $$KEEP_ENDIANNESS$$
+ * pf-vf event data
*/
-struct vf_pf_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
+struct vf_pf_event_data {
+ uint8_t vf_id;
uint8_t reserved0;
- uint16_t reserved1;
- uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */;
- uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */;
+ __le16 reserved1;
+ __le32 msg_addr_lo;
+ __le32 msg_addr_hi;
};
/*
- * VF FLR event data $$KEEP_ENDIANNESS$$
+ * VF FLR event data
*/
-struct vf_flr_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
+struct vf_flr_event_data {
+ uint8_t vf_id;
uint8_t reserved0;
- uint16_t reserved1;
- uint32_t reserved2;
- uint32_t reserved3;
+ __le16 reserved1;
+ __le32 reserved2;
+ __le32 reserved3;
};
/*
- * malicious VF event data $$KEEP_ENDIANNESS$$
+ * malicious VF event data
*/
-struct malicious_vf_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
- uint8_t err_id /* reason for malicious notification */;
- uint16_t reserved1;
- uint32_t reserved2;
- uint32_t reserved3;
+struct malicious_vf_event_data {
+ uint8_t vf_id;
+ uint8_t err_id;
+ __le16 reserved1;
+ __le32 reserved2;
+ __le32 reserved3;
};
/*
- * vif list event data $$KEEP_ENDIANNESS$$
+ * vif list event data
*/
-struct vif_list_event_data
-{
- uint8_t func_bit_map /* bit map of pf indice */;
+struct vif_list_event_data {
+ uint8_t func_bit_map;
uint8_t echo;
- uint16_t reserved0;
- uint32_t reserved1;
- uint32_t reserved2;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le32 reserved2;
};
/*
- * function update event data $$KEEP_ENDIANNESS$$
+ * function update event data
*/
-struct function_update_event_data
-{
+struct function_update_event_data {
uint8_t echo;
uint8_t reserved;
- uint16_t reserved0;
- uint32_t reserved1;
- uint32_t reserved2;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le32 reserved2;
};
/*
* union for all event ring message types
*/
-union event_data
-{
- struct vf_pf_event_data vf_pf_event /* vf-pf event data */;
- struct eth_event_data eth_event /* set mac event data */;
- struct cfc_del_event_data cfc_del_event /* cfc delete event data */;
- struct vf_flr_event_data vf_flr_event /* vf flr event data */;
- struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */;
- struct vif_list_event_data vif_list_event /* vif list event data */;
- struct function_update_event_data function_update_event /* function update event data */;
+union event_data {
+ struct vf_pf_event_data vf_pf_event;
+ struct eth_event_data eth_event;
+ struct cfc_del_event_data cfc_del_event;
+ struct vf_flr_event_data vf_flr_event;
+ struct malicious_vf_event_data malicious_vf_event;
+ struct vif_list_event_data vif_list_event;
+ struct function_update_event_data function_update_event;
};
/*
* per PF event ring data
*/
-struct event_ring_data
-{
- struct regpair_native base_addr /* ring base address */;
+struct event_ring_data {
+ struct regpair_native base_addr;
#if defined(__BIG_ENDIAN)
- uint8_t index_id /* index ID within the status block */;
- uint8_t sb_id /* status block ID */;
- uint16_t producer /* event ring producer */;
+ uint8_t index_id;
+ uint8_t sb_id;
+ uint16_t producer;
#elif defined(__LITTLE_ENDIAN)
- uint16_t producer /* event ring producer */;
- uint8_t sb_id /* status block ID */;
- uint8_t index_id /* index ID within the status block */;
+ uint16_t producer;
+ uint8_t sb_id;
+ uint8_t index_id;
#endif
uint32_t reserved0;
};
/*
- * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$
+ * event ring message element (each element is 128 bits)
*/
-struct event_ring_msg
-{
+struct event_ring_msg {
uint8_t opcode;
- uint8_t error /* error on the mesasage */;
+ uint8_t error;
uint16_t reserved1;
- union event_data data /* message data (96 bits data) */;
+ union event_data data;
};
/*
* event ring next page element (128 bits)
*/
-struct event_ring_next
-{
- struct regpair addr /* Address of the next page of the ring */;
+struct event_ring_next {
+ struct regpair addr;
uint32_t reserved[2];
};
/*
* union for event ring element types (each element is 128 bits)
*/
-union event_ring_elem
-{
- struct event_ring_msg message /* event ring message */;
- struct event_ring_next next_page /* event ring next page */;
+union event_ring_elem {
+ struct event_ring_msg message;
+ struct event_ring_next next_page;
};
/*
* Common event ring opcodes
*/
-enum event_ring_opcode
-{
+enum event_ring_opcode {
EVENT_RING_OPCODE_VF_PF_CHANNEL,
- EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */,
- EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */,
- EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */,
- EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
- EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */,
- EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
- EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
- EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */,
- EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */,
- EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */,
- EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */,
- EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */,
- EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */,
- EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */,
- EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */,
- EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
- EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
+ EVENT_RING_OPCODE_FUNCTION_START,
+ EVENT_RING_OPCODE_FUNCTION_STOP,
+ EVENT_RING_OPCODE_CFC_DEL,
+ EVENT_RING_OPCODE_CFC_DEL_WB,
+ EVENT_RING_OPCODE_STAT_QUERY,
+ EVENT_RING_OPCODE_STOP_TRAFFIC,
+ EVENT_RING_OPCODE_START_TRAFFIC,
+ EVENT_RING_OPCODE_VF_FLR,
+ EVENT_RING_OPCODE_MALICIOUS_VF,
+ EVENT_RING_OPCODE_FORWARD_SETUP,
+ EVENT_RING_OPCODE_RSS_UPDATE_RULES,
+ EVENT_RING_OPCODE_FUNCTION_UPDATE,
+ EVENT_RING_OPCODE_AFEX_VIF_LISTS,
+ EVENT_RING_OPCODE_SET_MAC,
+ EVENT_RING_OPCODE_CLASSIFICATION_RULES,
+ EVENT_RING_OPCODE_FILTERS_RULES,
+ EVENT_RING_OPCODE_MULTICAST_RULES,
+ EVENT_RING_OPCODE_SET_TIMESYNC,
MAX_EVENT_RING_OPCODE};
/*
* Modes for fairness algorithm
*/
-enum fairness_mode
-{
- FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */,
- FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */,
+enum fairness_mode {
+ FAIRNESS_COS_WRR_MODE,
+ FAIRNESS_COS_ETS_MODE,
MAX_FAIRNESS_MODE};
/*
- * Priority and cos $$KEEP_ENDIANNESS$$
+ * Priority and cos
*/
-struct priority_cos
-{
- uint8_t priority /* Priority */;
- uint8_t cos /* Cos */;
- uint16_t reserved1;
+struct priority_cos {
+ uint8_t priority;
+ uint8_t cos;
+ __le16 reserved1;
};
/*
- * The data for flow control configuration $$KEEP_ENDIANNESS$$
+ * The data for flow control configuration
*/
-struct flow_control_configuration
-{
- struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */;
- uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */;
- uint8_t dcb_version /* DCB version Increase by one on each DCB update */;
- uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */;
+struct flow_control_configuration {
+ struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
+ uint8_t dcb_enabled;
+ uint8_t dcb_version;
+ uint8_t dont_add_pri_0_en;
uint8_t reserved1;
- uint32_t reserved2;
+ __le32 reserved2;
+ uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct function_start_data
-{
- uint8_t function_mode /* the function mode */;
- uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode. (E2/E3 Only) */;
- uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */;
- uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
+struct function_start_data {
+ uint8_t function_mode;
+ uint8_t allow_npar_tx_switching;
+ __le16 sd_vlan_tag;
+ __le16 vif_id;
uint8_t path_id;
- uint8_t network_cos_mode /* The cos mode for network traffic. */;
- uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */;
- uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
- uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
- uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
- uint16_t reserved1[2];
-};
-
-
-/*
- * $$KEEP_ENDIANNESS$$
- */
-struct function_update_data
-{
- uint8_t vif_id_change_flg /* If set, vif_id will be checked */;
- uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */;
- uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */;
- uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */;
- uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
- uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */;
- uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */;
- uint8_t network_cos_mode /* The cos mode for network traffic. */;
- uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */;
- uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */;
- uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */;
- uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */;
+ uint8_t network_cos_mode;
+ uint8_t dmae_cmd_id;
+ uint8_t no_added_tags;
+ __le16 reserved0;
+ __le32 reserved1;
+ uint8_t inner_clss_vxlan;
+ uint8_t inner_clss_l2gre;
+ uint8_t inner_clss_l2geneve;
+ uint8_t inner_rss;
+ __le16 vxlan_dst_port;
+ __le16 geneve_dst_port;
+ uint8_t sd_accept_mf_clss_fail;
+ uint8_t sd_accept_mf_clss_fail_match_ethtype;
+ __le16 sd_accept_mf_clss_fail_ethtype;
+ __le16 sd_vlan_eth_type;
+ uint8_t sd_vlan_force_pri_flg;
+ uint8_t sd_vlan_force_pri_val;
+ uint8_t c2s_pri_tt_valid;
+ uint8_t c2s_pri_default;
+ uint8_t tx_vlan_filtering_enable;
+ uint8_t tx_vlan_filtering_use_pvid;
+ uint8_t reserved2[4];
+ struct c2s_pri_trans_table_entry c2s_pri_trans_table;
+};
+
+
+/*
+ *
+ */
+struct function_update_data {
+ uint8_t vif_id_change_flg;
+ uint8_t afex_default_vlan_change_flg;
+ uint8_t allowed_priorities_change_flg;
+ uint8_t network_cos_mode_change_flg;
+ __le16 vif_id;
+ __le16 afex_default_vlan;
+ uint8_t allowed_priorities;
+ uint8_t network_cos_mode;
+ uint8_t lb_mode_en_change_flg;
+ uint8_t lb_mode_en;
+ uint8_t tx_switch_suspend_change_flg;
+ uint8_t tx_switch_suspend;
uint8_t echo;
+ uint8_t update_tunn_cfg_flg;
+ uint8_t inner_clss_vxlan;
+ uint8_t inner_clss_l2gre;
+ uint8_t inner_clss_l2geneve;
+ uint8_t inner_rss;
+ __le16 vxlan_dst_port;
+ __le16 geneve_dst_port;
+ uint8_t sd_vlan_force_pri_change_flg;
+ uint8_t sd_vlan_force_pri_flg;
+ uint8_t sd_vlan_force_pri_val;
+ uint8_t sd_vlan_tag_change_flg;
+ uint8_t sd_vlan_eth_type_change_flg;
uint8_t reserved1;
- uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */;
- uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
- uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
- uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
- uint32_t reserved3;
+ __le16 sd_vlan_tag;
+ __le16 sd_vlan_eth_type;
+ uint8_t tx_vlan_filtering_pvid_change_flg;
+ uint8_t reserved0;
+ __le32 reserved2;
};
/*
* FW version stored in the Xstorm RAM
*/
-struct fw_version
-{
+struct fw_version {
#if defined(__BIG_ENDIAN)
- uint8_t engineering /* firmware current engineering version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t major /* firmware current major version */;
+ uint8_t engineering;
+ uint8_t revision;
+ uint8_t minor;
+ uint8_t major;
#elif defined(__LITTLE_ENDIAN)
- uint8_t major /* firmware current major version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t engineering /* firmware current engineering version */;
+ uint8_t major;
+ uint8_t minor;
+ uint8_t revision;
+ uint8_t engineering;
#endif
uint32_t flags;
-#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
+#define FW_VERSION_OPTIMIZED (0x1<<0)
#define FW_VERSION_OPTIMIZED_SHIFT 0
-#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */
+#define FW_VERSION_BIG_ENDIEN (0x1<<1)
#define FW_VERSION_BIG_ENDIEN_SHIFT 1
-#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 1 - E1H */
+#define FW_VERSION_CHIP_VERSION (0x3<<2)
#define FW_VERSION_CHIP_VERSION_SHIFT 2
-#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */
+#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
#define __FW_VERSION_RESERVED_SHIFT 4
};
-/*
- * GRE RSS Mode
- */
-enum gre_rss_mode
-{
- GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */,
- GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */,
- NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */,
- MAX_GRE_RSS_MODE};
-
-
-/*
- * GRE Tunnel Mode
- */
-enum gre_tunnel_type
-{
- NO_GRE_TUNNEL,
- NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */,
- L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */,
- IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */,
- MAX_GRE_TUNNEL_TYPE};
-
-
/*
* Dynamic Host-Coalescing - Driver(host) counters
*/
-struct hc_dynamic_sb_drv_counters
-{
- uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */;
+struct hc_dynamic_sb_drv_counters {
+ uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* 2 bytes. configuration/state parameters for a single protocol index
*/
-struct hc_index_data
-{
+struct hc_index_data {
#if defined(__BIG_ENDIAN)
uint8_t flags;
-#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
+#define HC_INDEX_DATA_SM_ID (0x1<<0)
#define HC_INDEX_DATA_SM_ID_SHIFT 0
-#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
+#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
-#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
-#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
+#define HC_INDEX_DATA_RESERVE (0x1F<<3)
#define HC_INDEX_DATA_RESERVE_SHIFT 3
- uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
+ uint8_t timeout;
#elif defined(__LITTLE_ENDIAN)
- uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
+ uint8_t timeout;
uint8_t flags;
-#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
+#define HC_INDEX_DATA_SM_ID (0x1<<0)
#define HC_INDEX_DATA_SM_ID_SHIFT 0
-#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
+#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
-#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
-#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
+#define HC_INDEX_DATA_RESERVE (0x1F<<3)
#define HC_INDEX_DATA_RESERVE_SHIFT 3
#endif
};
@@ -5784,56 +6137,53 @@ struct hc_index_data
/*
* HC state-machine
*/
-struct hc_status_block_sm
-{
+struct hc_status_block_sm {
#if defined(__BIG_ENDIAN)
uint8_t igu_seg_id;
- uint8_t igu_sb_id /* sb_id within the IGU */;
- uint8_t timer_value /* Determines the time_to_expire */;
+ uint8_t igu_sb_id;
+ uint8_t timer_value;
uint8_t __flags;
#elif defined(__LITTLE_ENDIAN)
uint8_t __flags;
- uint8_t timer_value /* Determines the time_to_expire */;
- uint8_t igu_sb_id /* sb_id within the IGU */;
+ uint8_t timer_value;
+ uint8_t igu_sb_id;
uint8_t igu_seg_id;
#endif
- uint32_t time_to_expire /* The time in which it expects to wake up */;
+ uint32_t time_to_expire;
};
/*
* hold PCI identification variables- used in various places in firmware
*/
-struct pci_entity
-{
+struct pci_entity {
#if defined(__BIG_ENDIAN)
- uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
- uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
- uint8_t vnic_id /* Virtual NIC ID (0-3) */;
- uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
+ uint8_t vf_valid;
+ uint8_t vf_id;
+ uint8_t vnic_id;
+ uint8_t pf_id;
#elif defined(__LITTLE_ENDIAN)
- uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
- uint8_t vnic_id /* Virtual NIC ID (0-3) */;
- uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
- uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
+ uint8_t pf_id;
+ uint8_t vnic_id;
+ uint8_t vf_id;
+ uint8_t vf_valid;
#endif
};
/*
* The fast-path status block meta-data, common to all chips
*/
-struct hc_sb_data
-{
- struct regpair_native host_sb_addr /* Host status block address */;
- struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */;
- struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
+struct hc_sb_data {
+ struct regpair_native host_sb_addr;
+ struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
+ struct pci_entity p_func;
#if defined(__BIG_ENDIAN)
uint8_t rsrv0;
uint8_t state;
- uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
- uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
+ uint8_t dhc_qzone_id;
+ uint8_t same_igu_sb_1b;
#elif defined(__LITTLE_ENDIAN)
- uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
- uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
+ uint8_t same_igu_sb_1b;
+ uint8_t dhc_qzone_id;
uint8_t state;
uint8_t rsrv0;
#endif
@@ -5844,8 +6194,7 @@ struct hc_sb_data
/*
* Segment types for host coaslescing
*/
-enum hc_segment
-{
+enum hc_segment {
HC_REGULAR_SEGMENT,
HC_DEFAULT_SEGMENT,
MAX_HC_SEGMENT};
@@ -5854,59 +6203,64 @@ enum hc_segment
/*
* The fast-path status block meta-data
*/
-struct hc_sp_status_block_data
-{
- struct regpair_native host_sb_addr /* Host status block address */;
+struct hc_sp_status_block_data {
+ struct regpair_native host_sb_addr;
#if defined(__BIG_ENDIAN)
uint8_t rsrv1;
uint8_t state;
- uint8_t igu_seg_id /* segment id of the IGU */;
- uint8_t igu_sb_id /* sb_id within the IGU */;
+ uint8_t igu_seg_id;
+ uint8_t igu_sb_id;
#elif defined(__LITTLE_ENDIAN)
- uint8_t igu_sb_id /* sb_id within the IGU */;
- uint8_t igu_seg_id /* segment id of the IGU */;
+ uint8_t igu_sb_id;
+ uint8_t igu_seg_id;
uint8_t state;
uint8_t rsrv1;
#endif
- struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
+ struct pci_entity p_func;
};
/*
* The fast-path status block meta-data
*/
-struct hc_status_block_data_e1x
-{
- struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */;
- struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
+struct hc_status_block_data_e1x {
+ struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
+ struct hc_sb_data common;
};
/*
* The fast-path status block meta-data
*/
-struct hc_status_block_data_e2
-{
- struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */;
- struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
+struct hc_status_block_data_e2 {
+ struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
+ struct hc_sb_data common;
};
/*
* IGU block operartion modes (in Everest2)
*/
-enum igu_mode
-{
- HC_IGU_BC_MODE /* Backward compatible mode */,
- HC_IGU_NBC_MODE /* Non-backward compatible mode */,
+enum igu_mode {
+ HC_IGU_BC_MODE,
+ HC_IGU_NBC_MODE,
MAX_IGU_MODE};
+/*
+ * Inner Headers Classification Type
+ */
+enum inner_clss_type {
+ INNER_CLSS_DISABLED,
+ INNER_CLSS_USE_VLAN,
+ INNER_CLSS_USE_VNI,
+ MAX_INNER_CLSS_TYPE};
+
+
/*
* IP versions
*/
-enum ip_ver
-{
+enum ip_ver {
IP_V4,
IP_V6,
MAX_IP_VER};
@@ -5915,131 +6269,122 @@ enum ip_ver
/*
* Malicious VF error ID
*/
-enum malicious_vf_error_id
-{
- VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */,
- ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */,
- ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */,
- ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */,
- ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,
- ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */,
- ETH_TOO_MANY_BDS /* Tx packet has too many BDs */,
- ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */,
- ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */,
- ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */,
- ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */,
- ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */,
- ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */,
- ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */,
+enum malicious_vf_error_id {
+ MALICIOUS_VF_NO_ERROR,
+ VF_PF_CHANNEL_NOT_READY,
+ ETH_ILLEGAL_BD_LENGTHS,
+ ETH_PACKET_TOO_SHORT,
+ ETH_PAYLOAD_TOO_BIG,
+ ETH_ILLEGAL_ETH_TYPE,
+ ETH_ILLEGAL_LSO_HDR_LEN,
+ ETH_TOO_MANY_BDS,
+ ETH_ZERO_HDR_NBDS,
+ ETH_START_BD_NOT_SET,
+ ETH_ILLEGAL_PARSE_NBDS,
+ ETH_IPV6_AND_CHECKSUM,
+ ETH_VLAN_FLG_INCORRECT,
+ ETH_ILLEGAL_LSO_MSS,
+ ETH_TUNNEL_NOT_SUPPORTED,
MAX_MALICIOUS_VF_ERROR_ID};
/*
* Multi-function modes
*/
-enum mf_mode
-{
+enum mf_mode {
SINGLE_FUNCTION,
- MULTI_FUNCTION_SD /* Switch dependent (vlan based) */,
- MULTI_FUNCTION_SI /* Switch independent (mac based) */,
- MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */,
+ MULTI_FUNCTION_SD,
+ MULTI_FUNCTION_SI,
+ MULTI_FUNCTION_AFEX,
MAX_MF_MODE};
/*
- * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per pf)
*/
-struct tstorm_per_pf_stats
-{
- struct regpair rcv_error_bytes /* number of bytes received with errors */;
+struct tstorm_per_pf_stats {
+ struct regpair rcv_error_bytes;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_pf_stats
-{
+struct per_pf_stats {
struct tstorm_per_pf_stats tstorm_pf_statistics;
};
/*
- * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per port)
*/
-struct tstorm_per_port_stats
-{
- uint32_t mac_discard /* number of packets with mac errors */;
- uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */;
- uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */;
- uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */;
- uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */;
- uint32_t reserved;
+struct tstorm_per_port_stats {
+ __le32 mac_discard;
+ __le32 mac_filter_discard;
+ __le32 brb_truncate_discard;
+ __le32 mf_tag_discard;
+ __le32 packet_drop;
+ __le32 reserved;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_port_stats
-{
+struct per_port_stats {
struct tstorm_per_port_stats tstorm_port_statistics;
};
/*
- * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per client)
*/
-struct tstorm_per_queue_stats
-{
- struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */;
- uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */;
- uint32_t checksum_discard /* number of total packets received with checksum error */;
- struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */;
- uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */;
- uint32_t pkts_too_big_discard /* number of too long packets received */;
- struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */;
- uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */;
- uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;
- uint16_t no_buff_discard;
- uint16_t reserved0;
- uint32_t reserved1;
+struct tstorm_per_queue_stats {
+ struct regpair rcv_ucast_bytes;
+ __le32 rcv_ucast_pkts;
+ __le32 checksum_discard;
+ struct regpair rcv_bcast_bytes;
+ __le32 rcv_bcast_pkts;
+ __le32 pkts_too_big_discard;
+ struct regpair rcv_mcast_bytes;
+ __le32 rcv_mcast_pkts;
+ __le32 ttl0_discard;
+ __le16 no_buff_discard;
+ __le16 reserved0;
+ __le32 reserved1;
};
/*
- * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Ustorm (per client)
*/
-struct ustorm_per_queue_stats
-{
- struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */;
- struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */;
- struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */;
- uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */;
- struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */;
- uint32_t coalesced_events /* the number of aggregations */;
- uint32_t coalesced_aborts /* the number of exception which avoid aggregation */;
+struct ustorm_per_queue_stats {
+ struct regpair ucast_no_buff_bytes;
+ struct regpair mcast_no_buff_bytes;
+ struct regpair bcast_no_buff_bytes;
+ __le32 ucast_no_buff_pkts;
+ __le32 mcast_no_buff_pkts;
+ __le32 bcast_no_buff_pkts;
+ __le32 coalesced_pkts;
+ struct regpair coalesced_bytes;
+ __le32 coalesced_events;
+ __le32 coalesced_aborts;
};
/*
- * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Xstorm (per client)
*/
-struct xstorm_per_queue_stats
-{
- struct regpair ucast_bytes_sent /* number of total bytes sent without errors */;
- struct regpair mcast_bytes_sent /* number of total bytes sent without errors */;
- struct regpair bcast_bytes_sent /* number of total bytes sent without errors */;
- uint32_t ucast_pkts_sent /* number of total packets sent without errors */;
- uint32_t mcast_pkts_sent /* number of total packets sent without errors */;
- uint32_t bcast_pkts_sent /* number of total packets sent without errors */;
- uint32_t error_drop_pkts /* number of total packets drooped due to errors */;
+struct xstorm_per_queue_stats {
+ struct regpair ucast_bytes_sent;
+ struct regpair mcast_bytes_sent;
+ struct regpair bcast_bytes_sent;
+ __le32 ucast_pkts_sent;
+ __le32 mcast_pkts_sent;
+ __le32 bcast_pkts_sent;
+ __le32 error_drop_pkts;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_queue_stats
-{
+struct per_queue_stats {
struct tstorm_per_queue_stats tstorm_queue_statistics;
struct ustorm_per_queue_stats ustorm_queue_statistics;
struct xstorm_per_queue_stats xstorm_queue_statistics;
@@ -6047,24 +6392,23 @@ struct per_queue_stats
/*
- * FW version stored in first line of pram $$KEEP_ENDIANNESS$$
+ * FW version stored in first line of pram
*/
-struct pram_fw_version
-{
- uint8_t major /* firmware current major version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t engineering /* firmware current engineering version */;
+struct pram_fw_version {
+ uint8_t major;
+ uint8_t minor;
+ uint8_t revision;
+ uint8_t engineering;
uint8_t flags;
-#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
+#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
-#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */
+#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
-#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */
+#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
-#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 1 - E1H */
+#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
-#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */
+#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
};
@@ -6072,107 +6416,98 @@ struct pram_fw_version
/*
* Ethernet slow path element
*/
-union protocol_common_specific_data
-{
- uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
- struct regpair phy_address /* SPE physical address */;
- struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */;
- struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */;
+union protocol_common_specific_data {
+ uint8_t protocol_data[8];
+ struct regpair phy_address;
+ struct regpair mac_config_addr;
+ struct afex_vif_list_ramrod_data afex_vif_list_data;
};
/*
* The send queue element
*/
-struct protocol_common_spe
-{
- struct spe_hdr hdr /* SPE header */;
- union protocol_common_specific_data data /* data specific to common protocol */;
+struct protocol_common_spe {
+ struct spe_hdr hdr;
+ union protocol_common_specific_data data;
};
/*
- * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$
+ * The data for the Set Timesync Ramrod
*/
-struct set_timesync_ramrod_data
-{
- uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */;
- uint8_t offset_cmd /* Timesync Offset Command */;
- uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */;
- uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */;
- uint32_t drift_adjust_period /* Drift Adjust Period (in us) */;
- struct regpair offset_delta /* Timesync Offset Delta (in ns) */;
+struct set_timesync_ramrod_data {
+ uint8_t drift_adjust_cmd;
+ uint8_t offset_cmd;
+ uint8_t add_sub_drift_adjust_value;
+ uint8_t drift_adjust_value;
+ uint32_t drift_adjust_period;
+ struct regpair offset_delta;
};
/*
* The send queue element
*/
-struct slow_path_element
-{
- struct spe_hdr hdr /* common data for all protocols */;
- struct regpair protocol_data /* additional data specific to the protocol */;
+struct slow_path_element {
+ struct spe_hdr hdr;
+ struct regpair protocol_data;
};
/*
- * Protocol-common statistics counter $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics counter
*/
-struct stats_counter
-{
- uint16_t xstats_counter /* xstorm statistics counter */;
- uint16_t reserved0;
- uint32_t reserved1;
- uint16_t tstats_counter /* tstorm statistics counter */;
- uint16_t reserved2;
- uint32_t reserved3;
- uint16_t ustats_counter /* ustorm statistics counter */;
- uint16_t reserved4;
- uint32_t reserved5;
- uint16_t cstats_counter /* ustorm statistics counter */;
- uint16_t reserved6;
- uint32_t reserved7;
+struct stats_counter {
+ __le16 xstats_counter;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le16 tstats_counter;
+ __le16 reserved2;
+ __le32 reserved3;
+ __le16 ustats_counter;
+ __le16 reserved4;
+ __le32 reserved5;
+ __le16 cstats_counter;
+ __le16 reserved6;
+ __le32 reserved7;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct stats_query_entry
-{
+struct stats_query_entry {
uint8_t kind;
- uint8_t index /* queue index */;
- uint16_t funcID /* the func the statistic will send to */;
- uint32_t reserved;
- struct regpair address /* pxp address */;
+ uint8_t index;
+ __le16 funcID;
+ __le32 reserved;
+ struct regpair address;
};
/*
- * statistic command $$KEEP_ENDIANNESS$$
+ * statistic command
*/
-struct stats_query_cmd_group
-{
+struct stats_query_cmd_group {
struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
};
/*
- * statistic command header $$KEEP_ENDIANNESS$$
+ * statistic command header
*/
-struct stats_query_header
-{
- uint8_t cmd_num /* command number */;
+struct stats_query_header {
+ uint8_t cmd_num;
uint8_t reserved0;
- uint16_t drv_stats_counter;
- uint32_t reserved1;
- struct regpair stats_counters_addrs /* stats counter */;
+ __le16 drv_stats_counter;
+ __le32 reserved1;
+ struct regpair stats_counters_addrs;
};
/*
* Types of statistcis query entry
*/
-enum stats_query_type
-{
+enum stats_query_type {
STATS_TYPE_QUEUE,
STATS_TYPE_PORT,
STATS_TYPE_PF,
@@ -6184,8 +6519,7 @@ enum stats_query_type
/*
* Indicate of the function status block state
*/
-enum status_block_state
-{
+enum status_block_state {
SB_DISABLED,
SB_ENABLED,
SB_CLEANED,
@@ -6195,8 +6529,7 @@ enum status_block_state
/*
* Storm IDs (including attentions for IGU related enums)
*/
-enum storm_id
-{
+enum storm_id {
USTORM_ID,
CSTORM_ID,
XSTORM_ID,
@@ -6208,19 +6541,17 @@ enum storm_id
/*
* Taffic types used in ETS and flow control algorithms
*/
-enum traffic_type
-{
- LLFC_TRAFFIC_TYPE_NW /* Networking */,
- LLFC_TRAFFIC_TYPE_FCOE /* FCoE */,
- LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */,
+enum traffic_type {
+ LLFC_TRAFFIC_TYPE_NW,
+ LLFC_TRAFFIC_TYPE_FCOE,
+ LLFC_TRAFFIC_TYPE_ISCSI,
MAX_TRAFFIC_TYPE};
/*
* zone A per-queue data
*/
-struct tstorm_queue_zone_data
-{
+struct tstorm_queue_zone_data {
struct regpair reserved[4];
};
@@ -6228,8 +6559,7 @@ struct tstorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct tstorm_vf_zone_data
-{
+struct tstorm_vf_zone_data {
struct regpair reserved;
};
@@ -6237,41 +6567,87 @@ struct tstorm_vf_zone_data
/*
* Add or Subtract Value for Set Timesync Ramrod
*/
-enum ts_add_sub_value
-{
- TS_SUB_VALUE /* Subtract Value */,
- TS_ADD_VALUE /* Add Value */,
+enum ts_add_sub_value {
+ TS_SUB_VALUE,
+ TS_ADD_VALUE,
MAX_TS_ADD_SUB_VALUE};
/*
* Drift-Adjust Commands for Set Timesync Ramrod
*/
-enum ts_drift_adjust_cmd
-{
- TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */,
- TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */,
- TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */,
+enum ts_drift_adjust_cmd {
+ TS_DRIFT_ADJUST_KEEP,
+ TS_DRIFT_ADJUST_SET,
+ TS_DRIFT_ADJUST_RESET,
MAX_TS_DRIFT_ADJUST_CMD};
/*
* Offset Commands for Set Timesync Ramrod
*/
-enum ts_offset_cmd
-{
- TS_OFFSET_KEEP /* Keep Offset at current values */,
- TS_OFFSET_INC /* Increase Offset by Offset Delta */,
- TS_OFFSET_DEC /* Decrease Offset by Offset Delta */,
+enum ts_offset_cmd {
+ TS_OFFSET_KEEP,
+ TS_OFFSET_INC,
+ TS_OFFSET_DEC,
MAX_TS_OFFSET_CMD};
+/*
+ * Input for measuring Pci Latency
+ */
+struct t_measure_pci_latency_ctrl {
+ struct regpair read_addr;
+#if defined(__BIG_ENDIAN)
+ uint8_t sleep;
+ uint8_t enable;
+ uint8_t func_id;
+ uint8_t read_size;
+#elif defined(__LITTLE_ENDIAN)
+ uint8_t read_size;
+ uint8_t func_id;
+ uint8_t enable;
+ uint8_t sleep;
+#endif
+#if defined(__BIG_ENDIAN)
+ uint16_t num_meas;
+ uint8_t reserved;
+ uint8_t period_10us;
+#elif defined(__LITTLE_ENDIAN)
+ uint8_t period_10us;
+ uint8_t reserved;
+ uint16_t num_meas;
+#endif
+};
+
+
+/*
+ * Input for measuring Pci Latency
+ */
+struct t_measure_pci_latency_data {
+#if defined(__BIG_ENDIAN)
+ uint16_t max_time_ns;
+ uint16_t min_time_ns;
+#elif defined(__LITTLE_ENDIAN)
+ uint16_t min_time_ns;
+ uint16_t max_time_ns;
+#endif
+#if defined(__BIG_ENDIAN)
+ uint16_t reserved;
+ uint16_t num_reads;
+#elif defined(__LITTLE_ENDIAN)
+ uint16_t num_reads;
+ uint16_t reserved;
+#endif
+ struct regpair sum_time_ns;
+};
+
+
/*
* zone A per-queue data
*/
-struct ustorm_queue_zone_data
-{
- union ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */;
+struct ustorm_queue_zone_data {
+ struct ustorm_eth_rx_producers eth_rx_producers;
struct regpair reserved[3];
};
@@ -6279,8 +6655,7 @@ struct ustorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct ustorm_vf_zone_data
-{
+struct ustorm_vf_zone_data {
struct regpair reserved;
};
@@ -6288,15 +6663,14 @@ struct ustorm_vf_zone_data
/*
* data per VF-PF channel
*/
-struct vf_pf_channel_data
-{
+struct vf_pf_channel_data {
#if defined(__BIG_ENDIAN)
uint16_t reserved0;
- uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
- uint8_t state /* channel state (ready / waiting for ack) */;
+ uint8_t valid;
+ uint8_t state;
#elif defined(__LITTLE_ENDIAN)
- uint8_t state /* channel state (ready / waiting for ack) */;
- uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
+ uint8_t state;
+ uint8_t valid;
uint16_t reserved0;
#endif
uint32_t reserved1;
@@ -6306,18 +6680,16 @@ struct vf_pf_channel_data
/*
* State of VF-PF channel
*/
-enum vf_pf_channel_state
-{
- VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */,
- VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */,
+enum vf_pf_channel_state {
+ VF_PF_CHANNEL_STATE_READY,
+ VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
MAX_VF_PF_CHANNEL_STATE};
/*
* vif_list_rule_kind
*/
-enum vif_list_rule_kind
-{
+enum vif_list_rule_kind {
VIF_LIST_RULE_SET,
VIF_LIST_RULE_GET,
VIF_LIST_RULE_CLEAR_ALL,
@@ -6328,8 +6700,7 @@ enum vif_list_rule_kind
/*
* zone A per-queue data
*/
-struct xstorm_queue_zone_data
-{
+struct xstorm_queue_zone_data {
struct regpair reserved[4];
};
@@ -6337,10 +6708,8 @@ struct xstorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct xstorm_vf_zone_data
-{
+struct xstorm_vf_zone_data {
struct regpair reserved;
};
-
#endif /* ECORE_HSI_H */
diff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c
index 5ac22e725..ceac82815 100644
--- a/drivers/net/bnx2x/ecore_sp.c
+++ b/drivers/net/bnx2x/ecore_sp.c
@@ -3524,13 +3524,6 @@ static int ecore_setup_rss(struct bnx2x_softc *sc,
data->capabilities |=
ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
- if (ECORE_TEST_BIT(ECORE_RSS_TUNNELING, &p->rss_flags)) {
- data->udp_4tuple_dst_port_mask =
- ECORE_CPU_TO_LE16(p->tunnel_mask);
- data->udp_4tuple_dst_port_value =
- ECORE_CPU_TO_LE16(p->tunnel_value);
- }
-
/* Hashing mask */
data->rss_result_mask = p->rss_result_mask;
@@ -5088,8 +5081,6 @@ static int ecore_func_send_start(struct bnx2x_softc *sc,
rdata->sd_vlan_tag = ECORE_CPU_TO_LE16(start_params->sd_vlan_tag);
rdata->path_id = ECORE_PATH_ID(sc);
rdata->network_cos_mode = start_params->network_cos_mode;
- rdata->gre_tunnel_mode = start_params->gre_tunnel_mode;
- rdata->gre_tunnel_rss = start_params->gre_tunnel_rss;
/*
* No need for an explicit memory barrier here as long we would
@@ -5229,7 +5220,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st
rdata->dcb_enabled = tx_start_params->dcb_enabled;
rdata->dcb_version = tx_start_params->dcb_version;
- rdata->dont_add_pri_0 = tx_start_params->dont_add_pri_0;
+ rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;
for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
rdata->traffic_type_to_priority_cos[i] =
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH 3/5] net/bnx2x: update to latest FW 7.13.11
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
2019-09-06 7:25 ` [dpdk-dev] [PATCH 1/5] net/bnx2x: update and reorganize HW registers Rasesh Mody
2019-09-06 7:25 ` [dpdk-dev] [PATCH 2/5] net/bnx2x: update HSI code Rasesh Mody
@ 2019-09-06 7:25 ` Rasesh Mody
2019-09-12 12:25 ` Jerin Jacob
2019-09-06 7:25 ` [dpdk-dev] [PATCH 4/5] doc: cleanup SPDX license id usage in bnx2x guide Rasesh Mody
` (11 subsequent siblings)
14 siblings, 1 reply; 29+ messages in thread
From: Rasesh Mody @ 2019-09-06 7:25 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, ferruh.yigit, jerinj, GR-Everest-DPDK-Dev
Use latest firmware 7.13.11.
Some of the fixes included with this FW are as following:
- Packets from a VF with pvid configured which were sent with a
different vlan were transmitted instead of being discarded.
- In some multi-function configurations, inter-PF and inter-VF
Tx switching is incorrectly enabled.
- Wrong assert code in FLR final cleanup in case it is sent not
after FLR.
- Chip may stall in very rare cases under heavy traffic with FW GRO
enabled.
- VF malicious notification error fixes.
- Default gre tunnel to IPGRE which allows proper RSS for IPGRE
packets, L2GRE traffic will reach single queue.
- Removes unnecessary internal mem config, latest FW performs this
autonomously.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/bnx2x/bnx2x.c | 36 +---
drivers/net/bnx2x/bnx2x.h | 5 +-
drivers/net/bnx2x/ecore_fw_defs.h | 252 ++++++++++++-----------
drivers/net/bnx2x/ecore_hsi.h | 2 +-
drivers/net/bnx2x/ecore_init.h | 212 +++++++++----------
drivers/net/bnx2x/ecore_init_ops.h | 224 ++++++++++----------
drivers/net/bnx2x/ecore_mfw_req.h | 10 +-
drivers/net/bnx2x/ecore_sp.c | 39 ++--
drivers/net/bnx2x/ecore_sp.h | 319 ++++++++++++++++++++++++-----
9 files changed, 680 insertions(+), 419 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index a83a7103e..d744493cc 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -5230,20 +5230,6 @@ static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
{
int i;
- if (IS_MF_SI(sc)) {
-/*
- * In switch independent mode, the TSTORM needs to accept
- * packets that failed classification, since approximate match
- * mac addresses aren't written to NIG LLH.
- */
- REG_WR8(sc,
- (BAR_TSTRORM_INTMEM +
- TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
- } else
- REG_WR8(sc,
- (BAR_TSTRORM_INTMEM +
- TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
-
/*
* Zero this manually as its initialization is currently missing
* in the initTool.
@@ -5797,15 +5783,12 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc)
VNICS_PER_PATH(sc));
/* RSS configuration object */
- ecore_init_rss_config_obj(&sc->rss_conf_obj,
- sc->fp[0].cl_id,
- sc->fp[0].index,
- SC_FUNC(sc),
- SC_FUNC(sc),
+ ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
+ sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
BNX2X_SP(sc, rss_rdata),
(rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
- ECORE_FILTER_RSS_CONF_PENDING,
- &sc->sp_state, ECORE_OBJ_TYPE_RX);
+ ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
+ ECORE_OBJ_TYPE_RX);
}
/*
@@ -5834,9 +5817,6 @@ static int bnx2x_func_start(struct bnx2x_softc *sc)
start_params->network_cos_mode = FW_WRR;
}
- start_params->gre_tunnel_mode = 0;
- start_params->gre_tunnel_rss = 0;
-
return ecore_func_state_change(sc, &func_params);
}
@@ -9650,8 +9630,8 @@ static void bnx2x_init_rte(struct bnx2x_softc *sc)
}
#define FW_HEADER_LEN 104
-#define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
-#define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
+#define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
+#define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
void bnx2x_load_firmware(struct bnx2x_softc *sc)
{
@@ -10367,7 +10347,7 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
/* clean the DMAE memory */
sc->dmae_ready = 1;
- ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
+ ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
@@ -11579,7 +11559,7 @@ static void bnx2x_reset_func(struct bnx2x_softc *sc)
ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
ilt_cli.client_num = ILT_CLIENT_TM;
- ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
+ ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
}
/* this assumes that reset_port() called before reset_func() */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 054d95424..43c60408a 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -83,9 +83,6 @@
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif
-#ifndef ARRSIZE
-#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-#endif
#ifndef DIV_ROUND_UP
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#endif
@@ -1020,6 +1017,8 @@ struct bnx2x_pci_cap {
uint16_t addr;
};
+struct ecore_ilt;
+
struct bnx2x_vfdb;
/* Top level device private data structure. */
diff --git a/drivers/net/bnx2x/ecore_fw_defs.h b/drivers/net/bnx2x/ecore_fw_defs.h
index 5984acd94..5397a701a 100644
--- a/drivers/net/bnx2x/ecore_fw_defs.h
+++ b/drivers/net/bnx2x/ecore_fw_defs.h
@@ -13,170 +13,170 @@
#ifndef ECORE_FW_DEFS_H
#define ECORE_FW_DEFS_H
-
-#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base)
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
- (IRO[147].base + ((assertListEntry) * IRO[147].m1))
+ (IRO[151].base + ((assertListEntry) * IRO[151].m1))
#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
- (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
- IRO[153].m2))
+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
+ IRO[157].m2))
#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
- (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
- IRO[154].m2))
-#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
- (IRO[155].base + ((vfId) * IRO[155].m1))
-#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
- (IRO[156].base + ((vfId) * IRO[156].m1))
-#define CSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[150].base + ((funcId) * IRO[150].m1))
+ (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
+ IRO[158].m2))
#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
- (IRO[159].base + ((funcId) * IRO[159].m1))
+ (IRO[163].base + ((funcId) * IRO[163].m1))
#define CSTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[149].base + ((funcId) * IRO[149].m1))
+ (IRO[153].base + ((funcId) * IRO[153].m1))
#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
- (IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))
+ (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
- (IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \
- * IRO[138].m2) + ((sbId) * IRO[138].m3))
-#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
+ (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
+ * IRO[142].m2) + ((sbId) * IRO[142].m3))
+#define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
- (IRO[317].base + ((pfId) * IRO[317].m1))
+ (IRO[323].base + ((pfId) * IRO[323].m1))
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
- (IRO[318].base + ((pfId) * IRO[318].m1))
+ (IRO[324].base + ((pfId) * IRO[324].m1))
#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
- (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))
+ (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
- (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))
+ (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
- (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))
+ (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
- (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))
+ (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
- (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
-#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
(IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
+ (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
- (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))
+ (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
- (IRO[316].base + ((pfId) * IRO[316].m1))
+ (IRO[322].base + ((pfId) * IRO[322].m1))
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[308].base + ((pfId) * IRO[308].m1))
+ (IRO[314].base + ((pfId) * IRO[314].m1))
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[307].base + ((pfId) * IRO[307].m1))
+ (IRO[313].base + ((pfId) * IRO[313].m1))
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[306].base + ((pfId) * IRO[306].m1))
+ (IRO[312].base + ((pfId) * IRO[312].m1))
#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[151].base + ((funcId) * IRO[151].m1))
+ (IRO[155].base + ((funcId) * IRO[155].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
- (IRO[142].base + ((pfId) * IRO[142].m1))
+ (IRO[146].base + ((pfId) * IRO[146].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
- (IRO[143].base + ((pfId) * IRO[143].m1))
+ (IRO[147].base + ((pfId) * IRO[147].m1))
#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
- (IRO[141].base + ((pfId) * IRO[141].m1))
-#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)
+ (IRO[145].base + ((pfId) * IRO[145].m1))
+#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
- (IRO[144].base + ((pfId) * IRO[144].m1))
-#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)
+ (IRO[148].base + ((pfId) * IRO[148].m1))
+#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
- (IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))
+ (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
- (IRO[133].base + ((sbId) * IRO[133].m1))
+ (IRO[137].base + ((sbId) * IRO[137].m1))
#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
- (IRO[134].base + ((sbId) * IRO[134].m1))
+ (IRO[138].base + ((sbId) * IRO[138].m1))
#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
- (IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))
+ (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
- (IRO[132].base + ((sbId) * IRO[132].m1))
-#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)
+ (IRO[136].base + ((sbId) * IRO[136].m1))
+#define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
- (IRO[137].base + ((sbId) * IRO[137].m1))
-#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)
+ (IRO[141].base + ((sbId) * IRO[141].m1))
+#define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
+#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
+ (IRO[159].base + ((vfId) * IRO[159].m1))
+#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
+ (IRO[160].base + ((vfId) * IRO[160].m1))
#define CSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[150].base + ((funcId) * IRO[150].m1))
-#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base)
+ (IRO[154].base + ((funcId) * IRO[154].m1))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
- (IRO[203].base + ((pfId) * IRO[203].m1))
+ (IRO[207].base + ((pfId) * IRO[207].m1))
#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[101].base + ((assertListEntry) * IRO[101].m1))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
- (IRO[201].base + ((pfId) * IRO[201].m1))
+ (IRO[205].base + ((pfId) * IRO[205].m1))
#define TSTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[103].base + ((funcId) * IRO[103].m1))
+ (IRO[107].base + ((funcId) * IRO[107].m1))
#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
- (IRO[272].base + ((pfId) * IRO[272].m1))
+ (IRO[278].base + ((pfId) * IRO[278].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
+ (IRO[279].base + ((pfId) * IRO[279].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
+ (IRO[280].base + ((pfId) * IRO[280].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
+ (IRO[281].base + ((pfId) * IRO[281].m1))
#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[271].base + ((pfId) * IRO[271].m1))
+ (IRO[277].base + ((pfId) * IRO[277].m1))
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[270].base + ((pfId) * IRO[270].m1))
+ (IRO[276].base + ((pfId) * IRO[276].m1))
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[269].base + ((pfId) * IRO[269].m1))
+ (IRO[275].base + ((pfId) * IRO[275].m1))
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
- (IRO[268].base + ((pfId) * IRO[268].m1))
+ (IRO[274].base + ((pfId) * IRO[274].m1))
#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
- (IRO[278].base + ((pfId) * IRO[278].m1))
+ (IRO[284].base + ((pfId) * IRO[284].m1))
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
- (IRO[264].base + ((pfId) * IRO[264].m1))
+ (IRO[270].base + ((pfId) * IRO[270].m1))
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[265].base + ((pfId) * IRO[265].m1))
+ (IRO[271].base + ((pfId) * IRO[271].m1))
#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[266].base + ((pfId) * IRO[266].m1))
+ (IRO[272].base + ((pfId) * IRO[272].m1))
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[267].base + ((pfId) * IRO[267].m1))
+ (IRO[273].base + ((pfId) * IRO[273].m1))
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
- (IRO[202].base + ((pfId) * IRO[202].m1))
+ (IRO[206].base + ((pfId) * IRO[206].m1))
#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[105].base + ((funcId) * IRO[105].m1))
+ (IRO[109].base + ((funcId) * IRO[109].m1))
#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
- (IRO[217].base + ((pfId) * IRO[217].m1))
+ (IRO[223].base + ((pfId) * IRO[223].m1))
#define TSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[104].base + ((funcId) * IRO[104].m1))
-#define USTORM_AGG_DATA_OFFSET (IRO[206].base)
-#define USTORM_AGG_DATA_SIZE (IRO[206].size)
-#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base)
+ (IRO[108].base + ((funcId) * IRO[108].m1))
+#define USTORM_AGG_DATA_OFFSET (IRO[212].base)
+#define USTORM_AGG_DATA_SIZE (IRO[212].size)
+#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
- (IRO[176].base + ((assertListEntry) * IRO[176].m1))
-#define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \
- (IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * IRO[205].m2))
+ (IRO[180].base + ((assertListEntry) * IRO[180].m1))
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
- (IRO[183].base + ((portId) * IRO[183].m1))
+ (IRO[187].base + ((portId) * IRO[187].m1))
#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
- (IRO[319].base + ((pfId) * IRO[319].m1))
+ (IRO[325].base + ((pfId) * IRO[325].m1))
#define USTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[178].base + ((funcId) * IRO[178].m1))
+ (IRO[182].base + ((funcId) * IRO[182].m1))
#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
- (IRO[283].base + ((pfId) * IRO[283].m1))
+ (IRO[289].base + ((pfId) * IRO[289].m1))
#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
- (IRO[284].base + ((pfId) * IRO[284].m1))
+ (IRO[290].base + ((pfId) * IRO[290].m1))
#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
- (IRO[288].base + ((pfId) * IRO[288].m1))
+ (IRO[294].base + ((pfId) * IRO[294].m1))
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
- (IRO[285].base + ((pfId) * IRO[285].m1))
+ (IRO[291].base + ((pfId) * IRO[291].m1))
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[281].base + ((pfId) * IRO[281].m1))
+ (IRO[287].base + ((pfId) * IRO[287].m1))
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[280].base + ((pfId) * IRO[280].m1))
+ (IRO[286].base + ((pfId) * IRO[286].m1))
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[279].base + ((pfId) * IRO[279].m1))
+ (IRO[285].base + ((pfId) * IRO[285].m1))
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
- (IRO[282].base + ((pfId) * IRO[282].m1))
+ (IRO[288].base + ((pfId) * IRO[288].m1))
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
- (IRO[286].base + ((pfId) * IRO[286].m1))
+ (IRO[292].base + ((pfId) * IRO[292].m1))
#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
- (IRO[287].base + ((pfId) * IRO[287].m1))
+ (IRO[293].base + ((pfId) * IRO[293].m1))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
- (IRO[182].base + ((pfId) * IRO[182].m1))
+ (IRO[186].base + ((pfId) * IRO[186].m1))
#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[180].base + ((funcId) * IRO[180].m1))
+ (IRO[184].base + ((funcId) * IRO[184].m1))
#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
- (IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \
- IRO[209].m2))
+ (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
+ IRO[215].m2))
#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
- (IRO[210].base + ((qzoneId) * IRO[210].m1))
-#define USTORM_TPA_BTR_OFFSET (IRO[207].base)
-#define USTORM_TPA_BTR_SIZE (IRO[207].size)
+ (IRO[216].base + ((qzoneId) * IRO[216].m1))
+#define USTORM_TPA_BTR_OFFSET (IRO[213].base)
+#define USTORM_TPA_BTR_SIZE (IRO[213].size)
#define USTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[179].base + ((funcId) * IRO[179].m1))
+ (IRO[183].base + ((funcId) * IRO[183].m1))
#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
@@ -189,39 +189,39 @@
#define XSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[47].base + ((funcId) * IRO[47].m1))
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
- (IRO[296].base + ((pfId) * IRO[296].m1))
+ (IRO[302].base + ((pfId) * IRO[302].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
- (IRO[299].base + ((pfId) * IRO[299].m1))
+ (IRO[305].base + ((pfId) * IRO[305].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
- (IRO[300].base + ((pfId) * IRO[300].m1))
+ (IRO[306].base + ((pfId) * IRO[306].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
- (IRO[301].base + ((pfId) * IRO[301].m1))
+ (IRO[307].base + ((pfId) * IRO[307].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
- (IRO[302].base + ((pfId) * IRO[302].m1))
+ (IRO[308].base + ((pfId) * IRO[308].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
- (IRO[303].base + ((pfId) * IRO[303].m1))
+ (IRO[309].base + ((pfId) * IRO[309].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
- (IRO[304].base + ((pfId) * IRO[304].m1))
+ (IRO[310].base + ((pfId) * IRO[310].m1))
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
- (IRO[305].base + ((pfId) * IRO[305].m1))
+ (IRO[311].base + ((pfId) * IRO[311].m1))
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[295].base + ((pfId) * IRO[295].m1))
+ (IRO[301].base + ((pfId) * IRO[301].m1))
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[294].base + ((pfId) * IRO[294].m1))
+ (IRO[300].base + ((pfId) * IRO[300].m1))
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[293].base + ((pfId) * IRO[293].m1))
+ (IRO[299].base + ((pfId) * IRO[299].m1))
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
- (IRO[298].base + ((pfId) * IRO[298].m1))
+ (IRO[304].base + ((pfId) * IRO[304].m1))
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
- (IRO[297].base + ((pfId) * IRO[297].m1))
+ (IRO[303].base + ((pfId) * IRO[303].m1))
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
- (IRO[292].base + ((pfId) * IRO[292].m1))
+ (IRO[298].base + ((pfId) * IRO[298].m1))
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
- (IRO[291].base + ((pfId) * IRO[291].m1))
+ (IRO[297].base + ((pfId) * IRO[297].m1))
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
- (IRO[290].base + ((pfId) * IRO[290].m1))
+ (IRO[296].base + ((pfId) * IRO[296].m1))
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
- (IRO[289].base + ((pfId) * IRO[289].m1))
+ (IRO[295].base + ((pfId) * IRO[295].m1))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
(IRO[44].base + ((pfId) * IRO[44].m1))
#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
@@ -234,15 +234,18 @@
#define XSTORM_SPQ_PROD_OFFSET(funcId) \
(IRO[31].base + ((funcId) * IRO[31].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
- (IRO[211].base + ((portId) * IRO[211].m1))
+ (IRO[217].base + ((portId) * IRO[217].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
- (IRO[212].base + ((portId) * IRO[212].m1))
+ (IRO[218].base + ((portId) * IRO[218].m1))
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
- (IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \
- IRO[214].m2))
+ (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
+ IRO[220].m2))
#define XSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[48].base + ((funcId) * IRO[48].m1))
-#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base)
+#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+
+/* eth hsi version */
+#define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)
/* Ethernet Ring parameters */
@@ -250,19 +253,27 @@
#define FIRST_BD_IN_PKT 0
#define PARSE_BD_INDEX 1
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
+#define U_ETH_NUM_OF_SGES_TO_FETCH 8
+#define U_ETH_MAX_SGES_FOR_PACKET 3
/* Rx ring params */
#define U_ETH_LOCAL_BD_RING_SIZE 8
+#define U_ETH_LOCAL_SGE_RING_SIZE 10
#define U_ETH_SGL_SIZE 8
/* The fw will padd the buffer with this value, so the IP header \
will be align to 4 Byte */
#define IP_HEADER_ALIGNMENT_PADDING 2
+#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
+
#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
#define U_ETH_UNDEFINED_Q 0xFF
@@ -281,20 +292,25 @@
#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
/* Maximal L2 clients supported */
+#define ETH_MAX_RX_CLIENTS_E1 18
#define ETH_MAX_RX_CLIENTS_E1H 28
#define ETH_MAX_RX_CLIENTS_E2 152
/* Maximal statistics client Ids */
+#define MAX_STAT_COUNTER_ID_E1 36
#define MAX_STAT_COUNTER_ID_E1H 56
#define MAX_STAT_COUNTER_ID_E2 140
+#define MAX_MAC_CREDIT_E1 192 /* Per Chip */
#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
#define MAX_MAC_CREDIT_E2 272 /* Per Path */
+#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */
#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
#define MAX_VLAN_CREDIT_E2 272 /* Per Path */
/* Maximal aggregation queues supported */
+#define ETH_MAX_AGGREGATION_QUEUES_E1 32
#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
@@ -302,6 +318,8 @@
#define ETH_NUM_OF_MCAST_ENGINES_E2 72
#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
+#define ETH_MIN_RX_CQES_WITH_TPA_E1 \
+ (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)
#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
(ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
@@ -357,6 +375,7 @@
/* used for Host Coallescing */
#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
+#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
@@ -370,7 +389,7 @@
#define MAX_COS_NUMBER 4
#define MAX_TRAFFIC_TYPES 8
#define MAX_PFC_PRIORITIES 8
-
+#define MAX_VLAN_PRIORITIES 8
/* used by array traffic_type_to_priority[] to mark traffic type \
that is not mapped to priority*/
#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
@@ -397,5 +416,4 @@
#define MAX_NUM_FCOE_TASKS_PER_ENGINE \
4096 /*Each port can have at max 1 function*/
-
#endif /* ECORE_FW_DEFS_H */
diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index e1077da1d..2df993516 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -5505,7 +5505,7 @@ struct afex_vif_list_ramrod_data {
*
*/
struct c2s_pri_trans_table_entry {
- uint8_t val[8];
+ uint8_t val[MAX_VLAN_PRIORITIES];
};
diff --git a/drivers/net/bnx2x/ecore_init.h b/drivers/net/bnx2x/ecore_init.h
index 97dfe69b5..c011cbb86 100644
--- a/drivers/net/bnx2x/ecore_init.h
+++ b/drivers/net/bnx2x/ecore_init.h
@@ -26,10 +26,6 @@ enum {
OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */
OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
- OP_IF_PHASE,
- OP_RT,
- OP_DELAY,
- OP_VERIFY,
OP_MAX
};
@@ -86,17 +82,6 @@ struct op_if_mode {
uint32_t mode_bit_map;
};
-struct op_if_phase {
- uint32_t op:8;
- uint32_t cmd_offset:24;
- uint32_t phase_bit_map;
-};
-
-struct op_delay {
- uint32_t op:8;
- uint32_t reserved:24;
- uint32_t delay;
-};
union init_op {
struct op_read read;
@@ -105,8 +90,6 @@ union init_op {
struct op_zero zero;
struct raw_op raw;
struct op_if_mode if_mode;
- struct op_if_phase if_phase;
- struct op_delay delay;
};
@@ -187,12 +170,7 @@ enum {
NUM_OF_INIT_BLOCKS
};
-
-
-
-
-
-
+#include "bnx2x.h"
/* Vnics per mode */
#define ECORE_PORT2_MODE_NUM_VNICS 4
@@ -239,7 +217,7 @@ static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint3
/* update parameters for 4port mode */
if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
- if (PORT_ID(sc)) {
+ if (SC_PORT(sc)) {
curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
}
@@ -248,7 +226,7 @@ static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint3
/* change queue mapping for each VNIC */
for (vnic = 0; vnic < num_vnics; vnic++) {
uint32_t pf_q_num =
- ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
+ ECORE_PF_Q_NUM(q_num, SC_PORT(sc), vnic);
uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
/* overwrite queue->VOQ mapping */
@@ -427,7 +405,10 @@ static inline void ecore_init_min(const struct cmng_init_input *input_data,
tFair = T_FAIR_COEF / input_data->port_rate;
/* this is the threshold below which we won't arm the timer anymore */
- pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
+ pdata->fair_vars.fair_threshold = QM_ARB_BYTES + input_data->fairness_thr;
+
+ /*New limitation - minimal packet size to cause timeout to be armed */
+ pdata->fair_vars.size_thr = input_data->size_thr;
/*
* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
@@ -469,6 +450,7 @@ static inline void ecore_init_min(const struct cmng_init_input *input_data,
}
static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
+ uint32_t r_param __rte_unused,
struct cmng_init *ram_data)
{
uint32_t vnic, cos;
@@ -507,7 +489,8 @@ static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
}
}
-static inline void ecore_init_safc(struct cmng_init *ram_data)
+static inline void ecore_init_safc(const struct cmng_init_input *input_data __rte_unused,
+ struct cmng_init *ram_data)
{
/* in microSeconds */
ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
@@ -518,7 +501,7 @@ static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
struct cmng_init *ram_data)
{
uint32_t r_param;
- ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
+ ECORE_MEMSET(ram_data, 0, sizeof(struct cmng_init));
ram_data->port.flags = input_data->flags;
@@ -529,8 +512,8 @@ static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
r_param = BITS_TO_BYTES(input_data->port_rate);
ecore_init_max(input_data, r_param, ram_data);
ecore_init_min(input_data, r_param, ram_data);
- ecore_init_fw_wrr(input_data, ram_data);
- ecore_init_safc(ram_data);
+ ecore_init_fw_wrr(input_data, r_param, ram_data);
+ ecore_init_safc(input_data, ram_data);
}
@@ -585,25 +568,25 @@ struct src_ent {
/****************************************************************************
* Parity configuration
****************************************************************************/
-#define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK, \
block##_REG_##block##_PRTY_STS_CLR, \
- en_mask, {m1h, m2, m3}, #block \
+ en_mask, {m1, m1h, m2, m3}, #block \
}
-#define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK_0, \
block##_REG_##block##_PRTY_STS_CLR_0, \
- en_mask, {m1h, m2, m3}, #block"_0" \
+ en_mask, {m1, m1h, m2, m3}, #block"_0" \
}
-#define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK_1, \
block##_REG_##block##_PRTY_STS_CLR_1, \
- en_mask, {m1h, m2, m3}, #block"_1" \
+ en_mask, {m1, m1h, m2, m3}, #block"_1" \
}
static const struct {
@@ -611,6 +594,7 @@ static const struct {
uint32_t sts_clr_addr;
uint32_t en_mask; /* Mask to enable parity attentions */
struct {
+ uint32_t e1; /* 57710 */
uint32_t e1h; /* 57711 */
uint32_t e2; /* 57712 */
uint32_t e3; /* 578xx */
@@ -620,63 +604,67 @@ static const struct {
*/
} ecore_blocks_parity_data[] = {
/* bit 19 masked */
- /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
+ /* REG_WR(sc, PXP_REG_PXP_PRTY_MASK, 0x80000); */
/* bit 5,18,20-31 */
- /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
+ /* REG_WR(sc, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
/* bit 5 */
- /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
- /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
- /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
+ /* REG_WR(sc, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
+ /* REG_WR(sc, HC_REG_HC_PRTY_MASK, 0x0); */
+ /* REG_WR(sc, MISC_REG_MISC_PRTY_MASK, 0x0); */
/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
* want to handle "system kill" flow at the moment.
*/
- BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,
+ BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
0x7ffffff),
- BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff,
+ BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff),
- BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),
- BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),
- BLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),
- BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0xff, 0xffff),
- BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
- BLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),
- BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),
- BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),
- BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
+ BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
+ BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
+ BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
+ BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
+ BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
+ BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
+ BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
+ BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
+ BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
- {0xf, 0xf, 0xf}, "UPB"},
+ {0xf, 0xf, 0xf, 0xf}, "UPB"},
{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
- {0xf, 0xf, 0xf}, "XPB"},
- BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
- BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),
- BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
- BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
- BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
- BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
- BLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),
- BLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),
- BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
- BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),
- BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),
+ {0xf, 0xf, 0xf, 0xf}, "XPB"},
+ BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
+ BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
+ BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
+ BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
+ BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
+ BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
+ BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
+ BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
+ BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
+ BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
+ BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
};
@@ -685,45 +673,59 @@ static const struct {
* [30] MCP Latched ump_tx_parity
* [31] MCP Latched scpad_parity
*/
-#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
+#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
+
+#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
+ (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
/* Below registers control the MCP parity attention output. When
* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
* enabled, when cleared - disabled.
*/
-static const uint32_t mcp_attn_ctl_regs[] = {
- MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
- MISC_REG_AEU_ENABLE4_NIG_0,
- MISC_REG_AEU_ENABLE4_PXP_0,
- MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
- MISC_REG_AEU_ENABLE4_NIG_1,
- MISC_REG_AEU_ENABLE4_PXP_1
+static const struct {
+ uint32_t addr;
+ uint32_t bits;
+} mcp_attn_ctl_regs[] = {
+ { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
+ MISC_AEU_ENABLE_MCP_PRTY_BITS },
+ { MISC_REG_AEU_ENABLE4_NIG_0,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_PXP_0,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
+ MISC_AEU_ENABLE_MCP_PRTY_BITS },
+ { MISC_REG_AEU_ENABLE4_NIG_1,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_PXP_1,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
};
static inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable)
{
- uint32_t i;
+ unsigned int i;
uint32_t reg_val;
- for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
- reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);
+ for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
+ reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);
if (enable)
- reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
+ reg_val |= mcp_attn_ctl_regs[i].bits;
else
- reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
+ reg_val &= ~mcp_attn_ctl_regs[i].bits;
- REG_WR(sc, mcp_attn_ctl_regs[i], reg_val);
+ REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val);
}
}
static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
{
- if (CHIP_IS_E1H(sc))
+ if (CHIP_IS_E1(sc))
+ return ecore_blocks_parity_data[idx].reg_mask.e1;
+ else if (CHIP_IS_E1H(sc))
return ecore_blocks_parity_data[idx].reg_mask.e1h;
else if (CHIP_IS_E2(sc))
return ecore_blocks_parity_data[idx].reg_mask.e2;
@@ -733,9 +735,9 @@ static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
if (dis_mask) {
@@ -748,7 +750,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
}
/* Disable MCP parity attentions */
- ecore_set_mcp_parity(sc, FALSE);
+ ecore_set_mcp_parity(sc, false);
}
/**
@@ -756,7 +758,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
*/
static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
uint32_t reg_val, mcp_aeu_bits =
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
@@ -769,7 +771,7 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
if (reg_mask) {
@@ -799,9 +801,9 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
if (reg_mask)
@@ -810,7 +812,7 @@ static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
}
/* Enable MCP parity attentions */
- ecore_set_mcp_parity(sc, TRUE);
+ ecore_set_mcp_parity(sc, true);
}
diff --git a/drivers/net/bnx2x/ecore_init_ops.h b/drivers/net/bnx2x/ecore_init_ops.h
index 733ad1aa8..2111f3c81 100644
--- a/drivers/net/bnx2x/ecore_init_ops.h
+++ b/drivers/net/bnx2x/ecore_init_ops.h
@@ -15,6 +15,9 @@
#define ECORE_INIT_OPS_H
static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t *zbuf, int len);
+#if 0
+static void ecore_reg_wr_ind(struct bnx2x_softc *sc, uint32_t addr, uint32_t val);
+#endif
static void ecore_write_dmae_phys_len(struct bnx2x_softc *sc,
ecore_dma_addr_t phys_addr, uint32_t addr,
uint32_t len);
@@ -28,16 +31,41 @@ static void ecore_init_str_wr(struct bnx2x_softc *sc, uint32_t addr,
REG_WR(sc, addr + i*4, data[i]);
}
-static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len)
+#if 0
+static void ecore_init_ind_wr(struct bnx2x_softc *sc, uint32_t addr,
+ const uint32_t *data, uint32_t len)
+{
+ uint32_t i;
+
+ for (i = 0; i < len; i++)
+ ecore_reg_wr_ind(sc, addr + i*4, data[i]);
+}
+#endif
+
+#if 0
+static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len,
+ uint8_t wb)
+#else
+static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len,
+ uint8_t wb __rte_unused)
+#endif
{
if (DMAE_READY(sc))
ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
- else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
+#if 0
+ /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
+ else if (wb && CHIP_IS_E1(sc))
+ ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
+#endif
+
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
}
static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,
- uint32_t len)
+ uint32_t len, uint8_t wb)
{
uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
uint32_t buf_len32 = buf_len/4;
@@ -48,7 +76,7 @@ static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,
for (i = 0; i < len; i += buf_len32) {
uint32_t cur_len = min(buf_len32, len - i);
- ecore_write_big_buf(sc, addr + i*4, cur_len);
+ ecore_write_big_buf(sc, addr + i*4, cur_len, wb);
}
}
@@ -57,7 +85,15 @@ static void ecore_write_big_buf_wb(struct bnx2x_softc *sc, uint32_t addr, uint32
if (DMAE_READY(sc))
ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
- else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
+#if 0
+ /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
+ else if (CHIP_IS_E1(sc))
+ ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
+#endif
+
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
}
static void ecore_init_wr_64(struct bnx2x_softc *sc, uint32_t addr,
@@ -135,9 +171,18 @@ static void ecore_init_wr_wb(struct bnx2x_softc *sc, uint32_t addr,
if (DMAE_READY(sc))
VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
- else ecore_init_str_wr(sc, addr, data, len);
+#if 0
+ /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
+ else if (CHIP_IS_E1(sc))
+ ecore_init_ind_wr(sc, addr, data, len);
+#endif
+
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, data, len);
}
+
static void ecore_wr_64(struct bnx2x_softc *sc, uint32_t reg, uint32_t val_lo,
uint32_t val_hi)
{
@@ -215,11 +260,14 @@ static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t st
ecore_init_wr_wb(sc, addr, data, len);
break;
case OP_ZR:
+ ecore_init_fill(sc, addr, 0, op->zero.len, 0);
+ break;
case OP_WB_ZR:
- ecore_init_fill(sc, addr, 0, op->zero.len);
+ ecore_init_fill(sc, addr, 0, op->zero.len, 1);
break;
case OP_ZP:
- ecore_init_wr_zp(sc, addr, len, op->arr_wr.data_off);
+ ecore_init_wr_zp(sc, addr, len,
+ op->arr_wr.data_off);
break;
case OP_WR_64:
ecore_init_wr_64(sc, addr, data, len);
@@ -241,11 +289,6 @@ static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t st
op->if_mode.mode_bit_map) == 0)
op_idx += op->if_mode.cmd_offset;
break;
- /* the following opcodes are unused at the moment. */
- case OP_IF_PHASE:
- case OP_RT:
- case OP_DELAY:
- case OP_VERIFY:
default:
/* Should never get here! */
@@ -490,7 +533,7 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
- if (CHIP_IS_E1H(sc) && (r_order == MAX_RD_ORD))
+ if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))
REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
if (CHIP_IS_E3(sc))
@@ -500,31 +543,33 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
else
REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
- /* MPS w_order optimal TH presently TH
- * 128 0 0 2
- * 256 1 1 3
- * >=512 2 2 3
- */
- /* DMAE is special */
- if (!CHIP_IS_E1H(sc)) {
- /* E2 can use optimal TH */
- val = w_order;
- REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
- } else {
- val = ((w_order == 0) ? 2 : 3);
- REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
- }
+ if (!CHIP_IS_E1(sc)) {
+ /* MPS w_order optimal TH presently TH
+ * 128 0 0 2
+ * 256 1 1 3
+ * >=512 2 2 3
+ */
+ /* DMAE is special */
+ if (!CHIP_IS_E1H(sc)) {
+ /* E2 can use optimal TH */
+ val = w_order;
+ REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
+ } else {
+ val = ((w_order == 0) ? 2 : 3);
+ REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
+ }
- REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
- REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
- REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
- REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
+ }
/* Validate number of tags suppoted by device */
#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
@@ -559,18 +604,14 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
#define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
#define ILT_RANGE(f, l) (((l) << 10) | f)
-static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,
- struct ilt_line *line, uint32_t size, uint8_t memop, int cli_num, int i)
+static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc __rte_unused,
+ struct ilt_line *line, uint32_t size, uint8_t memop)
{
-#define ECORE_ILT_NAMESIZE 10
- char str[ECORE_ILT_NAMESIZE];
-
if (memop == ILT_MEMOP_FREE) {
ECORE_ILT_FREE(line->page, line->page_mapping, line->size);
return 0;
}
- snprintf(str, ECORE_ILT_NAMESIZE, "ILT_%d_%d", cli_num, i);
- ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size, str);
+ ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size);
if (!line->page)
return -1;
line->size = size;
@@ -581,7 +622,7 @@ static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,
static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,
uint8_t memop)
{
- int i, rc = 0;
+ int i, rc;
struct ecore_ilt *ilt = SC_ILT(sc);
struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
@@ -591,25 +632,13 @@ static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,
if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
return 0;
- for (i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
+ for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],
- ilt_cli->page_size, memop, cli_num, i);
+ ilt_cli->page_size, memop);
}
return rc;
}
-static inline int ecore_ilt_mem_op_cnic(struct bnx2x_softc *sc, uint8_t memop)
-{
- int rc = 0;
-
- if (CONFIGURE_NIC_MODE(sc))
- rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
- if (!rc)
- rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);
-
- return rc;
-}
-
static int ecore_ilt_mem_op(struct bnx2x_softc *sc, uint8_t memop)
{
int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);
@@ -626,7 +655,10 @@ static void ecore_ilt_line_wr(struct bnx2x_softc *sc, int abs_idx,
{
uint32_t reg;
- reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
+ if (CHIP_IS_E1(sc))
+ reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
+ else
+ reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
}
@@ -637,6 +669,7 @@ static void ecore_ilt_line_init_op(struct bnx2x_softc *sc,
ecore_dma_addr_t null_mapping;
int abs_idx = ilt->start_line + idx;
+
switch (initop) {
case INITOP_INIT:
/* set in the init-value array */
@@ -652,7 +685,8 @@ static void ecore_ilt_line_init_op(struct bnx2x_softc *sc,
static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
struct ilt_client_info *ilt_cli,
- uint32_t ilt_start)
+ uint32_t ilt_start,
+ uint8_t initop __rte_unused)
{
uint32_t start_reg = 0;
uint32_t end_reg = 0;
@@ -661,7 +695,26 @@ static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
CLEAR => SET and for now SET ~~ INIT */
/* find the appropriate regs */
- switch (ilt_cli->client_num) {
+ if (CHIP_IS_E1(sc)) {
+ switch (ilt_cli->client_num) {
+ case ILT_CLIENT_CDU:
+ start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
+ break;
+ case ILT_CLIENT_QM:
+ start_reg = PXP2_REG_PSWRQ_QM0_L2P;
+ break;
+ case ILT_CLIENT_SRC:
+ start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
+ break;
+ case ILT_CLIENT_TM:
+ start_reg = PXP2_REG_PSWRQ_TM0_L2P;
+ break;
+ }
+ REG_WR(sc, start_reg + SC_FUNC(sc) * 4,
+ ILT_RANGE((ilt_start + ilt_cli->start),
+ (ilt_start + ilt_cli->end)));
+ } else {
+ switch (ilt_cli->client_num) {
case ILT_CLIENT_CDU:
start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
@@ -678,9 +731,10 @@ static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
end_reg = PXP2_REG_RQ_TM_LAST_ILT;
break;
+ }
+ REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
+ REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
}
- REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
- REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
}
static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,
@@ -697,7 +751,7 @@ static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,
ecore_ilt_line_init_op(sc, ilt, i, initop);
/* init/clear the ILT boundries */
- ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line);
+ ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line, initop);
}
static void ecore_ilt_client_init_op(struct bnx2x_softc *sc,
@@ -717,13 +771,6 @@ static void ecore_ilt_client_id_init_op(struct bnx2x_softc *sc,
ecore_ilt_client_init_op(sc, ilt_cli, initop);
}
-static inline void ecore_ilt_init_op_cnic(struct bnx2x_softc *sc, uint8_t initop)
-{
- if (CONFIGURE_NIC_MODE(sc))
- ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
- ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);
-}
-
static void ecore_ilt_init_op(struct bnx2x_softc *sc, uint8_t initop)
{
ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);
@@ -771,7 +818,7 @@ static void ecore_ilt_init_page_size(struct bnx2x_softc *sc, uint8_t initop)
/****************************************************************************
* QM initializations
****************************************************************************/
-#define QM_QUEUES_PER_FUNC 16
+#define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
#define QM_INIT_MIN_CID_COUNT 31
#define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
@@ -831,33 +878,4 @@ static void ecore_qm_init_ptr_table(struct bnx2x_softc *sc, int qm_cid_count,
}
}
-/****************************************************************************
-* SRC initializations
-****************************************************************************/
-#ifdef ECORE_L5
-/* called during init func stage */
-static void ecore_src_init_t2(struct bnx2x_softc *sc, struct src_ent *t2,
- ecore_dma_addr_t t2_mapping, int src_cid_count)
-{
- int i;
- int port = SC_PORT(sc);
-
- /* Initialize T2 */
- for (i = 0; i < src_cid_count-1; i++)
- t2[i].next = (uint64_t)(t2_mapping +
- (i+1)*sizeof(struct src_ent));
-
- /* tell the searcher where the T2 table is */
- REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
-
- ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,
- U64_LO(t2_mapping), U64_HI(t2_mapping));
-
- ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,
- U64_LO((uint64_t)t2_mapping +
- (src_cid_count-1) * sizeof(struct src_ent)),
- U64_HI((uint64_t)t2_mapping +
- (src_cid_count-1) * sizeof(struct src_ent)));
-}
-#endif
#endif /* ECORE_INIT_OPS_H */
diff --git a/drivers/net/bnx2x/ecore_mfw_req.h b/drivers/net/bnx2x/ecore_mfw_req.h
index fe9450481..c929c7f7c 100644
--- a/drivers/net/bnx2x/ecore_mfw_req.h
+++ b/drivers/net/bnx2x/ecore_mfw_req.h
@@ -14,7 +14,6 @@
#define ECORE_MFW_REQ_H
-
#define PORT_0 0
#define PORT_1 1
#define PORT_MAX 2
@@ -143,6 +142,14 @@ struct iscsi_stats_info {
uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
/* QoS Priority (per 802.1p). 0-7255 */
uint32_t qos_priority;
+#define ISCSI_QOS_PRIORITY_OFFSET 0
+#define ISCSI_QOS_PRIORITY_MASK (0xffff)
+
+#define ISCSI_IP_ADDRESS_TYPE_OFFSET 30
+#define ISCSI_IP_ADDRESS_TYPE_MASK (3 << 30)
+#define ISCSI_IP_ADDRESS_TYPE_NOT_SET (0 << 30) /* Driver does not have the IP address and type populated */
+#define ISCSI_IP_ADDRESS_TYPE_IPV4 (1 << 30) /* IPV4 IP address set */
+#define ISCSI_IP_ADDRESS_TYPE_IPV6 (2 << 30) /* IPV6 IP address set */
uint8_t initiator_name[64]; /* iSCSI Boot Initiator Node name. */
@@ -181,5 +188,4 @@ union drv_info_to_mcp {
struct iscsi_stats_info iscsi_stat;
};
-
#endif /* ECORE_MFW_REQ_H */
diff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c
index ceac82815..b9bca9115 100644
--- a/drivers/net/bnx2x/ecore_sp.c
+++ b/drivers/net/bnx2x/ecore_sp.c
@@ -501,7 +501,7 @@ static int __ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc __rte_unused,
*
* @details May sleep. Claims and releases execution queue lock during its run.
*/
-static int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
+int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *o)
{
int rc;
@@ -712,7 +712,7 @@ static uint8_t ecore_vlan_mac_get_rx_tx_flag(struct ecore_vlan_mac_obj
return rx_tx_flag;
}
-static void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
+void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
int add, unsigned char *dev_addr, int index)
{
uint32_t wb_data[2];
@@ -2764,12 +2764,16 @@ static int ecore_mcast_validate_e2(__rte_unused struct bnx2x_softc *sc,
static void ecore_mcast_revert_e2(__rte_unused struct bnx2x_softc *sc,
struct ecore_mcast_ramrod_params *p,
- int old_num_bins)
+ int old_num_bins,
+ enum ecore_mcast_cmd cmd)
{
struct ecore_mcast_obj *o = p->mcast_obj;
o->set_registry_size(o, old_num_bins);
o->total_pending_num -= p->mcast_list_len;
+
+ if (cmd == ECORE_MCAST_CMD_SET)
+ o->total_pending_num -= o->max_cmd_len;
}
/**
@@ -2915,7 +2919,8 @@ static int ecore_mcast_validate_e1h(__rte_unused struct bnx2x_softc *sc,
static void ecore_mcast_revert_e1h(__rte_unused struct bnx2x_softc *sc,
__rte_unused struct ecore_mcast_ramrod_params
- *p, __rte_unused int old_num_bins)
+ *p, __rte_unused int old_num_bins,
+ __rte_unused enum ecore_mcast_cmd cmd)
{
/* Do nothing */
}
@@ -3093,7 +3098,7 @@ int ecore_config_mcast(struct bnx2x_softc *sc,
r->clear_pending(r);
error_exit1:
- o->revert(sc, p, old_reg_size);
+ o->revert(sc, p, old_reg_size, cmd);
return rc;
}
@@ -3350,7 +3355,7 @@ static int ecore_credit_pool_get_entry_always_TRUE(__rte_unused struct
* If credit is negative pool operations will always succeed (unlimited pool).
*
*/
-static void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
+void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
int base, int credit)
{
/* Zero the object first */
@@ -3588,11 +3593,13 @@ int ecore_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *p)
return rc;
}
-void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
+void ecore_init_rss_config_obj(struct bnx2x_softc *sc __rte_unused,
+ struct ecore_rss_config_obj *rss_obj,
uint8_t cl_id, uint32_t cid, uint8_t func_id,
- uint8_t engine_id, void *rdata,
- ecore_dma_addr_t rdata_mapping, int state,
- unsigned long *pstate, ecore_obj_type type)
+ uint8_t engine_id,
+ void *rdata, ecore_dma_addr_t rdata_mapping,
+ int state, unsigned long *pstate,
+ ecore_obj_type type)
{
ecore_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,
rdata_mapping, state, pstate, type);
@@ -5107,8 +5114,14 @@ static int ecore_func_send_switch_update(struct bnx2x_softc *sc, struct ecore_fu
ECORE_MEMSET(rdata, 0, sizeof(*rdata));
/* Fill the ramrod data with provided parameters */
- rdata->tx_switch_suspend_change_flg = 1;
- rdata->tx_switch_suspend = switch_update_params->suspend;
+ if (ECORE_TEST_BIT(ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+ &switch_update_params->changes)) {
+ rdata->tx_switch_suspend_change_flg = 1;
+ rdata->tx_switch_suspend =
+ ECORE_TEST_BIT(ECORE_F_UPDATE_TX_SWITCH_SUSPEND,
+ &switch_update_params->changes);
+ }
+
rdata->echo = SWITCH_UPDATE;
return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
@@ -5220,7 +5233,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st
rdata->dcb_enabled = tx_start_params->dcb_enabled;
rdata->dcb_version = tx_start_params->dcb_version;
- rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;
+ rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en;
for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
rdata->traffic_type_to_priority_cos[i] =
diff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h
index fce715b6d..11b9f77fb 100644
--- a/drivers/net/bnx2x/ecore_sp.h
+++ b/drivers/net/bnx2x/ecore_sp.h
@@ -135,6 +135,7 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
#define SC_ILT(sc) ((sc)->ilt)
#define ILOG2(x) bnx2x_ilog2(x)
+#if 0
#define ECORE_ILT_ZALLOC(x, y, size, str) \
do { \
x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \
@@ -150,6 +151,23 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
} \
} \
} while (0)
+#else
+#define ECORE_ILT_ZALLOC(x, y, size) \
+ do { \
+ x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \
+ if (x) { \
+ if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
+ size, (struct bnx2x_dma *)x, \
+ "ILT", RTE_CACHE_LINE_SIZE) != 0) { \
+ rte_free(x); \
+ x = NULL; \
+ *y = 0; \
+ } else { \
+ *y = ((struct bnx2x_dma *)x)->paddr; \
+ } \
+ } \
+ } while (0)
+#endif
#define ECORE_ILT_FREE(x, y, size) \
do { \
@@ -161,7 +179,7 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
} \
} while (0)
-#define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE
+#define ECORE_IS_VALID_ETHER_ADDR(_mac) true
#define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE
#define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE
@@ -238,11 +256,11 @@ typedef struct ecore_list_t
(_list)->cnt = 0; \
} while (0)
-/* return TRUE if the element is the last on the list */
+/* return true if the element is the last on the list */
#define ECORE_LIST_IS_LAST(_elem, _list) \
(_elem == (_list)->tail)
-/* return TRUE if the list is empty */
+/* return true if the list is empty */
#define ECORE_LIST_IS_EMPTY(_list) \
((_list)->cnt == 0)
@@ -413,9 +431,6 @@ enum {
AFEX_UPDATE,
};
-
-
-
struct bnx2x_softc;
struct eth_context;
@@ -461,11 +476,18 @@ enum {
ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
ECORE_FILTER_FCOE_ETH_START_SCHED,
ECORE_FILTER_FCOE_ETH_STOP_SCHED,
+#ifdef ECORE_CHAR_DEV
+ ECORE_FILTER_BYPASS_RX_MODE_PENDING,
+ ECORE_FILTER_BYPASS_MAC_PENDING,
+ ECORE_FILTER_BYPASS_RSS_CONF_PENDING,
+#endif
ECORE_FILTER_MCAST_PENDING,
ECORE_FILTER_MCAST_SCHED,
ECORE_FILTER_RSS_CONF_PENDING,
ECORE_AFEX_FCOE_Q_UPDATE_PENDING,
- ECORE_AFEX_PENDING_VIFSET_MCP_ACK
+ ECORE_AFEX_PENDING_VIFSET_MCP_ACK,
+ ECORE_FILTER_VXLAN_PENDING,
+ ECORE_FILTER_PVLAN_PENDING
};
struct ecore_raw_obj {
@@ -488,7 +510,7 @@ struct ecore_raw_obj {
int (*wait_comp)(struct bnx2x_softc *sc,
struct ecore_raw_obj *o);
- int (*check_pending)(struct ecore_raw_obj *o);
+ bool (*check_pending)(struct ecore_raw_obj *o);
void (*clear_pending)(struct ecore_raw_obj *o);
void (*set_pending)(struct ecore_raw_obj *o);
};
@@ -509,10 +531,16 @@ struct ecore_vlan_mac_ramrod_data {
uint16_t vlan;
};
+struct ecore_vxlan_fltr_ramrod_data {
+ uint8_t innermac[ETH_ALEN];
+ uint32_t vni;
+};
+
union ecore_classification_ramrod_data {
struct ecore_mac_ramrod_data mac;
struct ecore_vlan_ramrod_data vlan;
struct ecore_vlan_mac_ramrod_data vlan_mac;
+ struct ecore_vxlan_fltr_ramrod_data vxlan_fltr;
};
/* VLAN_MAC commands */
@@ -541,6 +569,7 @@ union ecore_exe_queue_cmd_data {
struct ecore_vlan_mac_data vlan_mac;
struct {
+ /* TODO */
} mcast;
};
@@ -642,7 +671,7 @@ struct ecore_vlan_mac_registry_elem {
ecore_list_entry_t link;
/* Used to store the cam offset used for the mac/vlan/vlan-mac.
- * Relevant for 57711 only. VLANs and MACs share the
+ * Relevant for 57710 and 57711 only. VLANs and MACs share the
* same CAM for these chips.
*/
int cam_offset;
@@ -659,9 +688,18 @@ enum {
ECORE_ETH_MAC,
ECORE_ISCSI_ETH_MAC,
ECORE_NETQ_ETH_MAC,
+ ECORE_VLAN,
ECORE_DONT_CONSUME_CAM_CREDIT,
ECORE_DONT_CONSUME_CAM_CREDIT_DEST,
};
+/* When looking for matching filters, some flags are not interesting */
+#define ECORE_VLAN_MAC_CMP_MASK (1 << ECORE_UC_LIST_MAC | \
+ 1 << ECORE_ETH_MAC | \
+ 1 << ECORE_ISCSI_ETH_MAC | \
+ 1 << ECORE_NETQ_ETH_MAC | \
+ 1 << ECORE_VLAN)
+#define ECORE_VLAN_MAC_CMP_FLAGS(flags) \
+ ((flags) & ECORE_VLAN_MAC_CMP_MASK)
struct ecore_vlan_mac_ramrod_params {
/* Object to run the command from */
@@ -685,7 +723,7 @@ struct ecore_vlan_mac_obj {
* all these fields should only be accessed under the exe_queue lock
*/
uint8_t head_reader; /* Num. of readers accessing head list */
- int head_exe_request; /* Pending execution request. */
+ bool head_exe_request; /* Pending execution request. */
unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
/* Execution queue interface instance */
@@ -728,7 +766,7 @@ struct ecore_vlan_mac_obj {
/**
* Checks if DEL-ramrod with the given params may be performed.
*
- * @return TRUE if the element may be deleted
+ * @return true if the element may be deleted
*/
struct ecore_vlan_mac_registry_elem *
(*check_del)(struct bnx2x_softc *sc,
@@ -738,9 +776,9 @@ struct ecore_vlan_mac_obj {
/**
* Checks if DEL-ramrod with the given params may be performed.
*
- * @return TRUE if the element may be deleted
+ * @return true if the element may be deleted
*/
- int (*check_move)(struct bnx2x_softc *sc,
+ bool (*check_move)(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *src_o,
struct ecore_vlan_mac_obj *dst_o,
union ecore_classification_ramrod_data *data);
@@ -749,10 +787,10 @@ struct ecore_vlan_mac_obj {
* Update the relevant credit object(s) (consume/return
* correspondingly).
*/
- int (*get_credit)(struct ecore_vlan_mac_obj *o);
- int (*put_credit)(struct ecore_vlan_mac_obj *o);
- int (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
- int (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
+ bool (*get_credit)(struct ecore_vlan_mac_obj *o);
+ bool (*put_credit)(struct ecore_vlan_mac_obj *o);
+ bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
+ bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
/**
* Configures one rule in the ramrod data buffer.
@@ -838,6 +876,9 @@ enum {
ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
};
+void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
+ bool add, unsigned char *dev_addr, int index);
+
/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
/* RX_MODE ramrod special flags: set in rx_mode_flags field in
@@ -898,7 +939,7 @@ struct ecore_mcast_list_elem {
union ecore_mcast_config_data {
uint8_t *mac;
- uint8_t bin; /* used in a RESTORE flow */
+ uint8_t bin; /* used in a RESTORE/SET flows */
};
struct ecore_mcast_ramrod_params {
@@ -908,6 +949,14 @@ struct ecore_mcast_ramrod_params {
unsigned long ramrod_flags;
ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */
+ /** TODO:
+ * - rename it to macs_num.
+ * - Add a new command type for handling pending commands
+ * (remove "zero semantics").
+ *
+ * Length of mcast_list. If zero and ADD_CONT command - post
+ * pending commands.
+ */
int mcast_list_len;
};
@@ -916,6 +965,15 @@ enum ecore_mcast_cmd {
ECORE_MCAST_CMD_CONT,
ECORE_MCAST_CMD_DEL,
ECORE_MCAST_CMD_RESTORE,
+
+ /* Following this, multicast configuration should equal to approx
+ * the set of MACs provided [i.e., remove all else].
+ * The two sub-commands are used internally to decide whether a given
+ * bin is to be added or removed
+ */
+ ECORE_MCAST_CMD_SET,
+ ECORE_MCAST_CMD_SET_ADD,
+ ECORE_MCAST_CMD_SET_DEL,
};
struct ecore_mcast_obj {
@@ -989,14 +1047,14 @@ struct ecore_mcast_obj {
/** Checks if there are more mcast MACs to be set or a previous
* command is still pending.
*/
- int (*check_pending)(struct ecore_mcast_obj *o);
+ bool (*check_pending)(struct ecore_mcast_obj *o);
/**
* Set/Clear/Check SCHEDULED state of the object
*/
void (*set_sched)(struct ecore_mcast_obj *o);
void (*clear_sched)(struct ecore_mcast_obj *o);
- int (*check_sched)(struct ecore_mcast_obj *o);
+ bool (*check_sched)(struct ecore_mcast_obj *o);
/* Wait until all pending commands complete */
int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o);
@@ -1015,7 +1073,8 @@ struct ecore_mcast_obj {
*/
void (*revert)(struct bnx2x_softc *sc,
struct ecore_mcast_ramrod_params *p,
- int old_num_bins);
+ int old_num_bins,
+ enum ecore_mcast_cmd cmd);
int (*get_registry_size)(struct ecore_mcast_obj *o);
void (*set_registry_size)(struct ecore_mcast_obj *o, int n);
@@ -1045,33 +1104,33 @@ struct ecore_credit_pool_obj {
/**
* Get the next free pool entry.
*
- * @return TRUE if there was a free entry in the pool
+ * @return true if there was a free entry in the pool
*/
- int (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
+ bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
/**
* Return the entry back to the pool.
*
- * @return TRUE if entry is legal and has been successfully
+ * @return true if entry is legal and has been successfully
* returned to the pool.
*/
- int (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
+ bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
/**
* Get the requested amount of credit from the pool.
*
* @param cnt Amount of requested credit
- * @return TRUE if the operation is successful
+ * @return true if the operation is successful
*/
- int (*get)(struct ecore_credit_pool_obj *o, int cnt);
+ bool (*get)(struct ecore_credit_pool_obj *o, int cnt);
/**
* Returns the credit to the pool.
*
* @param cnt Amount of credit to return
- * @return TRUE if the operation is successful
+ * @return true if the operation is successful
*/
- int (*put)(struct ecore_credit_pool_obj *o, int cnt);
+ bool (*put)(struct ecore_credit_pool_obj *o, int cnt);
/**
* Reads the current amount of credit.
@@ -1094,7 +1153,9 @@ enum {
ECORE_RSS_IPV6_TCP,
ECORE_RSS_IPV6_UDP,
- ECORE_RSS_TUNNELING,
+ ECORE_RSS_IPV4_VXLAN,
+ ECORE_RSS_IPV6_VXLAN,
+ ECORE_RSS_TUNN_INNER_HDRS,
};
struct ecore_config_rss_params {
@@ -1117,10 +1178,6 @@ struct ecore_config_rss_params {
/* valid only if ECORE_RSS_UPDATE_TOE is set */
uint16_t toe_rss_bitmap;
-
- /* valid if ECORE_RSS_TUNNELING is set */
- uint16_t tunnel_value;
- uint16_t tunnel_mask;
};
struct ecore_rss_config_obj {
@@ -1158,6 +1215,8 @@ enum {
ECORE_Q_UPDATE_SILENT_VLAN_REM,
ECORE_Q_UPDATE_TX_SWITCHING_CHNG,
ECORE_Q_UPDATE_TX_SWITCHING,
+ ECORE_Q_UPDATE_PTP_PKTS_CHNG,
+ ECORE_Q_UPDATE_PTP_PKTS,
};
/* Allowed Queue states */
@@ -1222,12 +1281,16 @@ enum {
ECORE_Q_FLG_FORCE_DEFAULT_PRI,
ECORE_Q_FLG_REFUSE_OUTBAND_VLAN,
ECORE_Q_FLG_PCSUM_ON_PKT,
- ECORE_Q_FLG_TUN_INC_INNER_IP_ID
+ ECORE_Q_FLG_TUN_INC_INNER_IP_ID,
+ ECORE_Q_FLG_TPA_VLAN_DIS,
};
/* Queue type options: queue type may be a combination of below. */
enum ecore_q_type {
ECORE_Q_TYPE_FWD,
+ /** TODO: Consider moving both these flags into the init()
+ * ramrod params.
+ */
ECORE_Q_TYPE_HAS_RX,
ECORE_Q_TYPE_HAS_TX,
};
@@ -1238,6 +1301,10 @@ enum ecore_q_type {
#define ECORE_MULTI_TX_COS_E3B0 3
#define ECORE_MULTI_TX_COS 3 /* Maximum possible */
#define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)
+/* DMAE channel to be used by FW for timesync workaroun. A driver that sends
+ * timesync-related ramrods must not use this DMAE command ID.
+ */
+#define FW_DMAE_CMD_ID 6
struct ecore_queue_init_params {
struct {
@@ -1280,6 +1347,26 @@ struct ecore_queue_update_params {
uint8_t cid_index;
};
+struct ecore_queue_update_tpa_params {
+ ecore_dma_addr_t sge_map;
+ uint8_t update_ipv4;
+ uint8_t update_ipv6;
+ uint8_t max_tpa_queues;
+ uint8_t max_sges_pkt;
+ uint8_t complete_on_both_clients;
+ uint8_t dont_verify_thr;
+ uint8_t tpa_mode;
+ uint8_t _pad;
+
+ uint16_t sge_buff_sz;
+ uint16_t max_agg_sz;
+
+ uint16_t sge_pause_thr_low;
+ uint16_t sge_pause_thr_high;
+
+ uint8_t disable_tpa_over_vlan;
+};
+
struct rxq_pause_params {
uint16_t bd_th_lo;
uint16_t bd_th_hi;
@@ -1298,11 +1385,14 @@ struct ecore_general_setup_params {
uint8_t spcl_id;
uint16_t mtu;
uint8_t cos;
+
+ uint8_t fp_hsi;
};
struct ecore_rxq_setup_params {
/* dma */
ecore_dma_addr_t dscr_map;
+ ecore_dma_addr_t sge_map;
ecore_dma_addr_t rcq_map;
ecore_dma_addr_t rcq_np_map;
@@ -1313,6 +1403,8 @@ struct ecore_rxq_setup_params {
/* valid if ECORE_Q_FLG_TPA */
uint16_t tpa_agg_sz;
+ uint16_t sge_buf_sz;
+ uint8_t max_sges_pkt;
uint8_t max_tpa_queues;
uint8_t rss_engine_id;
@@ -1323,7 +1415,7 @@ struct ecore_rxq_setup_params {
uint8_t sb_cq_index;
- /* valid if BXN2X_Q_FLG_SILENT_VLAN_REM */
+ /* valid if ECORE_Q_FLG_SILENT_VLAN_REM */
uint16_t silent_removal_value;
uint16_t silent_removal_mask;
};
@@ -1371,6 +1463,7 @@ struct ecore_queue_state_params {
/* Params according to the current command */
union {
struct ecore_queue_update_params update;
+ struct ecore_queue_update_tpa_params update_tpa;
struct ecore_queue_setup_params setup;
struct ecore_queue_init_params init;
struct ecore_queue_setup_tx_only_params tx_only;
@@ -1450,6 +1543,24 @@ struct ecore_queue_sp_obj {
};
/********************** Function state update *********************************/
+
+/* UPDATE command options */
+enum {
+ ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+ ECORE_F_UPDATE_TX_SWITCH_SUSPEND,
+ ECORE_F_UPDATE_SD_VLAN_TAG_CHNG,
+ ECORE_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
+ ECORE_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
+ ECORE_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
+ ECORE_F_UPDATE_TUNNEL_CFG_CHNG,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
+ ECORE_F_UPDATE_TUNNEL_INNER_RSS,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN_INNER_VNI,
+ ECORE_F_UPDATE_VLAN_FILTERING_PVID_CHNG,
+};
+
/* Allowed Function states */
enum ecore_func_state {
ECORE_F_STATE_RESET,
@@ -1470,6 +1581,7 @@ enum ecore_func_cmd {
ECORE_F_CMD_TX_STOP,
ECORE_F_CMD_TX_START,
ECORE_F_CMD_SWITCH_UPDATE,
+ ECORE_F_CMD_SET_TIMESYNC,
ECORE_F_CMD_MAX,
};
@@ -1511,19 +1623,60 @@ struct ecore_func_start_params {
/* Function cos mode */
uint8_t network_cos_mode;
- /* NVGRE classification enablement */
- uint8_t nvgre_clss_en;
+ /* DMAE command id to be used for FW DMAE transactions */
+ uint8_t dmae_cmd_id;
+
+ /* UDP dest port for VXLAN */
+ uint16_t vxlan_dst_port;
+
+ /* UDP dest port for Geneve */
+ uint16_t geneve_dst_port;
+
+ /* Enable inner Rx classifications for L2GRE packets */
+ uint8_t inner_clss_l2gre;
+
+ /* Enable inner Rx classifications for L2-Geneve packets */
+ uint8_t inner_clss_l2geneve;
+
+ /* Enable inner Rx classification for vxlan packets */
+ uint8_t inner_clss_vxlan;
+
+ /* Enable RSS according to inner header */
+ uint8_t inner_rss;
- /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
- uint8_t gre_tunnel_mode;
+ /** Allows accepting of packets failing MF classification, possibly
+ * only matching a given ethertype
+ */
+ uint8_t class_fail;
+ uint16_t class_fail_ethtype;
+
+ /* Override priority of output packets */
+ uint8_t sd_vlan_force_pri;
+ uint8_t sd_vlan_force_pri_val;
+
+ /* Replace vlan's ethertype */
+ uint16_t sd_vlan_eth_type;
+
+ /* Prevent inner vlans from being added by FW */
+ uint8_t no_added_tags;
- /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
- uint8_t gre_tunnel_rss;
+ /* Inner-to-Outer vlan priority mapping */
+ uint8_t c2s_pri[MAX_VLAN_PRIORITIES];
+ uint8_t c2s_pri_default;
+ uint8_t c2s_pri_valid;
+ /* TX Vlan filtering configuration */
+ uint8_t tx_vlan_filtering_enable;
+ uint8_t tx_vlan_filtering_use_pvid;
};
struct ecore_func_switch_update_params {
- uint8_t suspend;
+ unsigned long changes; /* ECORE_F_UPDATE_XX bits */
+ uint16_t vlan;
+ uint16_t vlan_eth_type;
+ uint8_t vlan_force_prio;
+ uint16_t vxlan_dst_port;
+ uint16_t geneve_dst_port;
};
struct ecore_func_afex_update_params {
@@ -1538,11 +1691,28 @@ struct ecore_func_afex_viflists_params {
uint8_t afex_vif_list_command;
uint8_t func_to_clear;
};
+
struct ecore_func_tx_start_params {
struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
uint8_t dcb_enabled;
uint8_t dcb_version;
- uint8_t dont_add_pri_0;
+ uint8_t dont_add_pri_0_en;
+ uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];
+};
+
+struct ecore_func_set_timesync_params {
+ /* Reset, set or keep the current drift value */
+ uint8_t drift_adjust_cmd;
+ /* Dec, inc or keep the current offset */
+ uint8_t offset_cmd;
+ /* Drift value direction */
+ uint8_t add_sub_drift_adjust_value;
+ /* Drift, period and offset values to be used according to the commands
+ * above.
+ */
+ uint8_t drift_adjust_value;
+ uint32_t drift_adjust_period;
+ uint64_t offset_delta;
};
struct ecore_func_state_params {
@@ -1563,6 +1733,7 @@ struct ecore_func_state_params {
struct ecore_func_afex_update_params afex_update;
struct ecore_func_afex_viflists_params afex_viflists;
struct ecore_func_tx_start_params tx_start;
+ struct ecore_func_set_timesync_params set_timesync;
} params;
};
@@ -1583,6 +1754,10 @@ struct ecore_func_sp_drv_ops {
void (*reset_hw_port)(struct bnx2x_softc *sc);
void (*reset_hw_func)(struct bnx2x_softc *sc);
+ /* Init/Free GUNZIP resources */
+ int (*gunzip_init)(struct bnx2x_softc *sc);
+ void (*gunzip_end)(struct bnx2x_softc *sc);
+
/* Prepare/Release FW resources */
int (*init_fw)(struct bnx2x_softc *sc);
void (*release_fw)(struct bnx2x_softc *sc);
@@ -1669,6 +1844,9 @@ void ecore_init_queue_obj(struct bnx2x_softc *sc,
int ecore_queue_state_change(struct bnx2x_softc *sc,
struct ecore_queue_state_params *params);
+int ecore_get_q_logical_state(struct bnx2x_softc *sc,
+ struct ecore_queue_sp_obj *obj);
+
/********************* VLAN-MAC ****************/
void ecore_init_mac_obj(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *mac_obj,
@@ -1677,6 +1855,31 @@ void ecore_init_mac_obj(struct bnx2x_softc *sc,
unsigned long *pstate, ecore_obj_type type,
struct ecore_credit_pool_obj *macs_pool);
+void ecore_init_vlan_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+void ecore_init_vlan_mac_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_mac_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *macs_pool,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+void ecore_init_vxlan_fltr_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_mac_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *macs_pool,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *o);
void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *o);
int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc,
@@ -1719,7 +1922,7 @@ void ecore_init_mcast_obj(struct bnx2x_softc *sc,
/**
* ecore_config_mcast - Configure multicast MACs list.
*
- * @cmd: command to execute: BNX2X_MCAST_CMD_X
+ * @cmd: command to execute: ECORE_MCAST_CMD_X
*
* May configure a new list
* provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up
@@ -1732,7 +1935,7 @@ void ecore_init_mcast_obj(struct bnx2x_softc *sc,
* the current command will be enqueued to the tail of the
* pending commands list.
*
- * Return: 0 is operation was successful and there are no pending completions,
+ * Return: 0 is operation was successfull and there are no pending completions,
* negative if there were errors, positive if there are pending
* completions.
*/
@@ -1747,9 +1950,12 @@ void ecore_init_mac_credit_pool(struct bnx2x_softc *sc,
void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,
struct ecore_credit_pool_obj *p, uint8_t func_id,
uint8_t func_num);
+void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
+ int base, int credit);
/****************** RSS CONFIGURATION ****************/
-void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
+void ecore_init_rss_config_obj(struct bnx2x_softc *sc,
+ struct ecore_rss_config_obj *rss_obj,
uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,
void *rdata, ecore_dma_addr_t rdata_mapping,
int state, unsigned long *pstate,
@@ -1763,5 +1969,24 @@ void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
int ecore_config_rss(struct bnx2x_softc *sc,
struct ecore_config_rss_params *p);
+/**
+ * ecore_get_rss_ind_table - Return the current ind_table configuration.
+ *
+ * @ind_table: buffer to fill with the current indirection
+ * table content. Should be at least
+ * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
+ */
+void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj,
+ uint8_t *ind_table);
+
+#define PF_MAC_CREDIT_E2(sc, func_num) \
+ ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_MAC_CREDIT_CNT) / \
+ func_num + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT)
+
+#define PF_VLAN_CREDIT_E2(sc, func_num) \
+ ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_VLAN_CREDIT_CNT) / \
+ func_num + GET_NUM_VFS_PER_PF(sc) * VF_VLAN_CREDIT_CNT)
+
+#define ECORE_PF_VLAN_CREDIT_VLAN_FILTERING 256
#endif /* ECORE_SP_H */
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH 3/5] net/bnx2x: update to latest FW 7.13.11
2019-09-06 7:25 ` [dpdk-dev] [PATCH 3/5] net/bnx2x: update to latest FW 7.13.11 Rasesh Mody
@ 2019-09-12 12:25 ` Jerin Jacob
0 siblings, 0 replies; 29+ messages in thread
From: Jerin Jacob @ 2019-09-12 12:25 UTC (permalink / raw)
To: Rasesh Mody; +Cc: dev, ferruh.yigit, Jerin Jacob, GR-Everest-DPDK-Dev
On Fri, Sep 6, 2019 at 12:56 PM Rasesh Mody <rmody@marvell.com> wrote:
>
> Use latest firmware 7.13.11.
>
> Some of the fixes included with this FW are as following:
> - Packets from a VF with pvid configured which were sent with a
> different vlan were transmitted instead of being discarded.
> - In some multi-function configurations, inter-PF and inter-VF
> Tx switching is incorrectly enabled.
> - Wrong assert code in FLR final cleanup in case it is sent not
> after FLR.
> - Chip may stall in very rare cases under heavy traffic with FW GRO
> enabled.
> - VF malicious notification error fixes.
> - Default gre tunnel to IPGRE which allows proper RSS for IPGRE
> packets, L2GRE traffic will reach single queue.
> - Removes unnecessary internal mem config, latest FW performs this
> autonomously.
>
> Signed-off-by: Rasesh Mody <rmody@marvell.com>
> ---
> drivers/net/bnx2x/bnx2x.c | 36 +---
> drivers/net/bnx2x/bnx2x.h | 5 +-
> drivers/net/bnx2x/ecore_fw_defs.h | 252 ++++++++++++-----------
> drivers/net/bnx2x/ecore_hsi.h | 2 +-
> drivers/net/bnx2x/ecore_init.h | 212 +++++++++----------
> drivers/net/bnx2x/ecore_init_ops.h | 224 ++++++++++----------
> drivers/net/bnx2x/ecore_mfw_req.h | 10 +-
> drivers/net/bnx2x/ecore_sp.c | 39 ++--
> drivers/net/bnx2x/ecore_sp.h | 319 ++++++++++++++++++++++++-----
> 9 files changed, 680 insertions(+), 419 deletions(-)
Please update the release note as well.
> > diff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h
> index fce715b6d..11b9f77fb 100644
> --- a/drivers/net/bnx2x/ecore_sp.h
> +++ b/drivers/net/bnx2x/ecore_sp.h
> @@ -135,6 +135,7 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
> #define SC_ILT(sc) ((sc)->ilt)
> #define ILOG2(x) bnx2x_ilog2(x)
>
> +#if 0
Found dead code.
Don't just copy-paste code from some SDK code.
Please clean the code properly and submit the next version.
> #define ECORE_ILT_ZALLOC(x, y, size, str) \
> do { \
> x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \
> @@ -150,6 +151,23 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
> } \
> } \
> } while (0)
> +#else
^ permalink raw reply [flat|nested] 29+ messages in thread
* [dpdk-dev] [PATCH 4/5] doc: cleanup SPDX license id usage in bnx2x guide
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (2 preceding siblings ...)
2019-09-06 7:25 ` [dpdk-dev] [PATCH 3/5] net/bnx2x: update to latest FW 7.13.11 Rasesh Mody
@ 2019-09-06 7:25 ` Rasesh Mody
2019-09-06 7:25 ` [dpdk-dev] [PATCH 5/5] net/bnx2x: change PMD version to 1.1.0.1 Rasesh Mody
` (10 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-06 7:25 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, ferruh.yigit, jerinj, GR-Everest-DPDK-Dev
Removed redundant BSD boilerplate text from bnx2ix guide.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
doc/guides/nics/bnx2x.rst | 26 --------------------------
1 file changed, 26 deletions(-)
diff --git a/doc/guides/nics/bnx2x.rst b/doc/guides/nics/bnx2x.rst
index 00e131484..0a16f0c70 100644
--- a/doc/guides/nics/bnx2x.rst
+++ b/doc/guides/nics/bnx2x.rst
@@ -1,32 +1,6 @@
.. SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2015 QLogic Corporation
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in
- the documentation and/or other materials provided with the
- distribution.
- * Neither the name of QLogic Corporation nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
BNX2X Poll Mode Driver
======================
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH 5/5] net/bnx2x: change PMD version to 1.1.0.1
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (3 preceding siblings ...)
2019-09-06 7:25 ` [dpdk-dev] [PATCH 4/5] doc: cleanup SPDX license id usage in bnx2x guide Rasesh Mody
@ 2019-09-06 7:25 ` Rasesh Mody
2019-09-12 12:11 ` [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Jerin Jacob
` (9 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-06 7:25 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, ferruh.yigit, jerinj, GR-Everest-DPDK-Dev
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/bnx2x/bnx2x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index d744493cc..9b3ac0ab5 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -29,8 +29,8 @@
#define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
#define BNX2X_PMD_VERSION_MAJOR 1
-#define BNX2X_PMD_VERSION_MINOR 0
-#define BNX2X_PMD_VERSION_REVISION 7
+#define BNX2X_PMD_VERSION_MINOR 1
+#define BNX2X_PMD_VERSION_REVISION 0
#define BNX2X_PMD_VERSION_PATCH 1
static inline const char *
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (4 preceding siblings ...)
2019-09-06 7:25 ` [dpdk-dev] [PATCH 5/5] net/bnx2x: change PMD version to 1.1.0.1 Rasesh Mody
@ 2019-09-12 12:11 ` Jerin Jacob
2019-09-12 22:00 ` [dpdk-dev] [EXT] " Rasesh Mody
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 0/4] " Rasesh Mody
` (8 subsequent siblings)
14 siblings, 1 reply; 29+ messages in thread
From: Jerin Jacob @ 2019-09-12 12:11 UTC (permalink / raw)
To: Rasesh Mody; +Cc: dev, ferruh.yigit, Jerin Jacob, GR-Everest-DPDK-Dev
On Fri, Sep 6, 2019 at 12:56 PM Rasesh Mody <rmody@marvell.com> wrote:
>
> Hi,
>
> Currently, BNX2X PMD uses a very old firmware 7.2.51.
> This patch series updated the base driver to use to latest
> firmware 7.13.11. The latest firmware comprises of enhancements
> and fixes.
>
> Thanks!
> -Rasesh
>
> Rasesh Mody (5):
> net/bnx2x: update and reorganize HW registers
> net/bnx2x: update HSI code
> net/bnx2x: update to latest FW 7.13.11
> doc: cleanup SPDX license id usage in bnx2x guide
> net/bnx2x: change PMD version to 1.1.0.1
I think, The last patch can be squashed to "net/bnx2x: update to
latest FW 7.13.11" patch.
There are tons of checkpatch errors with this patch series. Please fix
as much as possible and send v2.
http://mails.dpdk.org/archives/test-report/2019-September/096011.html
http://mails.dpdk.org/archives/test-report/2019-September/096013.html
http://mails.dpdk.org/archives/test-report/2019-September/096012.html
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [EXT] Re: [PATCH 0/5] net/bnx2x: update to latest FW
2019-09-12 12:11 ` [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Jerin Jacob
@ 2019-09-12 22:00 ` Rasesh Mody
0 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-12 22:00 UTC (permalink / raw)
To: Jerin Jacob
Cc: dev, ferruh.yigit, Jerin Jacob Kollanukkaran, GR-Everest-DPDK-Dev
Hi Jerin,
>From: Jerin Jacob <jerinjacobk@gmail.com>
>Sent: Thursday, September 12, 2019 5:12 AM
>
>----------------------------------------------------------------------
>On Fri, Sep 6, 2019 at 12:56 PM Rasesh Mody <rmody@marvell.com> wrote:
>>
>> Hi,
>>
>> Currently, BNX2X PMD uses a very old firmware 7.2.51.
>> This patch series updated the base driver to use to latest firmware
>> 7.13.11. The latest firmware comprises of enhancements and fixes.
>>
>> Thanks!
>> -Rasesh
>>
>> Rasesh Mody (5):
>> net/bnx2x: update and reorganize HW registers
>> net/bnx2x: update HSI code
>> net/bnx2x: update to latest FW 7.13.11
>> doc: cleanup SPDX license id usage in bnx2x guide
>> net/bnx2x: change PMD version to 1.1.0.1
>
>I think, The last patch can be squashed to "net/bnx2x: update to latest FW
>7.13.11" patch.
>
>There are tons of checkpatch errors with this patch series. Please fix as much
>as possible and send v2.
>
>http://mails.dpdk.org/archives/test-report/2019-September/096011.html
>http://mails.dpdk.org/archives/test-report/2019-September/096013.html
>http://mails.dpdk.org/archives/test-report/2019-September/096012.html
I will send a v2 addressing the review comments.
Thanks!
-Rasesh
^ permalink raw reply [flat|nested] 29+ messages in thread
* [dpdk-dev] [PATCH v2 0/4] net/bnx2x: update to latest FW
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (5 preceding siblings ...)
2019-09-12 12:11 ` [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Jerin Jacob
@ 2019-09-19 21:11 ` Rasesh Mody
2019-09-23 16:33 ` Ferruh Yigit
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 1/4] net/bnx2x: update and reorganize HW registers Rasesh Mody
` (7 subsequent siblings)
14 siblings, 1 reply; 29+ messages in thread
From: Rasesh Mody @ 2019-09-19 21:11 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, jerinj, ferruh.yigit, GR-Everest-DPDK-Dev
Hi,
Currently, BNX2X PMD uses a very old firmware 7.2.51.
This patch series updated the base driver to use to latest
firmware 7.13.11. The latest firmware comprises of enhancements
and fixes.
v2:
- Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
- Addressed most of checkpatch issues
Thanks!
-Rasesh
Rasesh Mody (4):
net/bnx2x: update and reorganize HW registers
net/bnx2x: update HSI code
net/bnx2x: update to latest FW 7.13.11
doc: cleanup SPDX license id usage in bnx2x guide
doc/guides/nics/bnx2x.rst | 30 +-
drivers/net/bnx2x/bnx2x.c | 62 +-
drivers/net/bnx2x/bnx2x.h | 95 +-
drivers/net/bnx2x/bnx2x_osal.h | 27 +
drivers/net/bnx2x/bnx2x_rxtx.c | 10 +-
drivers/net/bnx2x/ecore_fw_defs.h | 252 +-
drivers/net/bnx2x/ecore_hsi.h | 3508 ++++++++-------
drivers/net/bnx2x/ecore_init.h | 214 +-
drivers/net/bnx2x/ecore_init_ops.h | 192 +-
drivers/net/bnx2x/ecore_mfw_req.h | 11 +-
drivers/net/bnx2x/ecore_reg.h | 6617 +++++++++++++++++++---------
drivers/net/bnx2x/ecore_sp.c | 48 +-
drivers/net/bnx2x/ecore_sp.h | 308 +-
13 files changed, 7182 insertions(+), 4192 deletions(-)
create mode 100644 drivers/net/bnx2x/bnx2x_osal.h
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH v2 0/4] net/bnx2x: update to latest FW
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 0/4] " Rasesh Mody
@ 2019-09-23 16:33 ` Ferruh Yigit
2019-09-24 15:39 ` Jerin Jacob
0 siblings, 1 reply; 29+ messages in thread
From: Ferruh Yigit @ 2019-09-23 16:33 UTC (permalink / raw)
To: Rasesh Mody, dev; +Cc: jerinj, GR-Everest-DPDK-Dev
On 9/19/2019 10:11 PM, Rasesh Mody wrote:
> Hi,
>
> Currently, BNX2X PMD uses a very old firmware 7.2.51.
> This patch series updated the base driver to use to latest
> firmware 7.13.11. The latest firmware comprises of enhancements
> and fixes.
>
> v2:
> - Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
> - Addressed most of checkpatch issues
>
> Thanks!
> -Rasesh
>
> Rasesh Mody (4):
> net/bnx2x: update and reorganize HW registers
> net/bnx2x: update HSI code
> net/bnx2x: update to latest FW 7.13.11
> doc: cleanup SPDX license id usage in bnx2x guide
>
I am getting build errors with this patchset [1], since it is merged into
next-net-mrvl, I only pulled the doc patch, 4/4, but not others, can you please
check the patchset?
[1]
In file included from .../dpdk/drivers/net/bnx2x/bnx2x.h:22,
from .../dpdk/drivers/net/bnx2x/bnx2x_rxtx.c:8:
.../dpdk/drivers/net/bnx2x/bnx2x_osal.h:25:17: error: conflicting types for
‘uint64_t’
25 | #define __le64 uint64_t
| ^~~~~~~~
In file included from /usr/include/stdint.h:37,
from /usr/lib/gcc/x86_64-redhat-linux/9/include/stdint.h:9,
from
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_byteorder.h:12,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:17,
from .../dpdk/drivers/net/bnx2x/bnx2x_rxtx.c:8:
/usr/include/bits/stdint-uintn.h:27:20: note: previous declaration of ‘uint64_t’
was here
27 | typedef __uint64_t uint64_t;
| ^~~~~~~~
In file included from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.h:33,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:23,
from .../dpdk/drivers/net/bnx2x/bnx2x_rxtx.c:8:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_ethdev_driver.h: In function
‘rte_eth_linkstatus_set’:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_ethdev_driver.h:176:37: error:
passing argument 1 of ‘rte_atomic64_exchange’ from incompatible pointer type
[-Werror=incompatible-pointer-types]
176 | orig.val64 = rte_atomic64_exchange(dev_link,
| ^~~~~~~~
| |
| volatile uint64_t * {aka volatile
long long unsigned int *}
In file included from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_atomic.h:263,
from
.../dpdk/x86_64-native-linuxapp-gcc/include/generic/rte_cycles.h:18,
from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_cycles.h:13,
from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_spinlock.h:18,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:18,
from .../dpdk/drivers/net/bnx2x/bnx2x_rxtx.c:8:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_atomic_64.h:48:42: note:
expected ‘volatile uint64_t *’ {aka ‘volatile long unsigned int *’} but argument
is of type ‘volatile uint64_t *’ {aka ‘volatile long long unsigned int *’}
48 | rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
| ~~~~~~~~~~~~~~~~~~~^~~
cc1: all warnings being treated as errors
In file included from .../dpdk/drivers/net/bnx2x/bnx2x.h:22,
from .../dpdk/drivers/net/bnx2x/bnx2x_vfpf.c:8:
.../dpdk/drivers/net/bnx2x/bnx2x_osal.h:25:17: error: conflicting types for
‘uint64_t’
25 | #define __le64 uint64_t
| ^~~~~~~~
In file included from /usr/include/stdint.h:37,
from /usr/lib/gcc/x86_64-redhat-linux/9/include/stdint.h:9,
from
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_byteorder.h:12,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:17,
from .../dpdk/drivers/net/bnx2x/bnx2x_vfpf.c:8:
/usr/include/bits/stdint-uintn.h:27:20: note: previous declaration of ‘uint64_t’
was here
27 | typedef __uint64_t uint64_t;
| ^~~~~~~~
In file included from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.h:33,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:23,
from .../dpdk/drivers/net/bnx2x/bnx2x_vfpf.c:8:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_ethdev_driver.h: In function
‘rte_eth_linkstatus_set’:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_ethdev_driver.h:176:37: error:
passing argument 1 of ‘rte_atomic64_exchange’ from incompatible pointer type
[-Werror=incompatible-pointer-types]
176 | orig.val64 = rte_atomic64_exchange(dev_link,
| ^~~~~~~~
| |
| volatile uint64_t * {aka volatile
long long unsigned int *}
In file included from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_atomic.h:263,
from
.../dpdk/x86_64-native-linuxapp-gcc/include/generic/rte_cycles.h:18,
from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_cycles.h:13,
from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_spinlock.h:18,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:18,
from .../dpdk/drivers/net/bnx2x/bnx2x_vfpf.c:8:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_atomic_64.h:48:42: note:
expected ‘volatile uint64_t *’ {aka ‘volatile long unsigned int *’} but argument
is of type ‘volatile uint64_t *’ {aka ‘volatile long long unsigned int *’}
48 | rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
| ~~~~~~~~~~~~~~~~~~~^~~
cc1: all warnings being treated as errors
make[7]: *** [.../dpdk/mk/internal/rte.compile-pre.mk:116: ecore_sp.o] Error 1
In file included from .../dpdk/drivers/net/bnx2x/bnx2x.h:22,
from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.c:8:
.../dpdk/drivers/net/bnx2x/bnx2x_osal.h:25:17: error: conflicting types for
‘uint64_t’
25 | #define __le64 uint64_t
| ^~~~~~~~
In file included from /usr/include/stdint.h:37,
from /usr/lib/gcc/x86_64-redhat-linux/9/include/stdint.h:9,
from
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_byteorder.h:12,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:17,
from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.c:8:
/usr/include/bits/stdint-uintn.h:27:20: note: previous declaration of ‘uint64_t’
was here
27 | typedef __uint64_t uint64_t;
| ^~~~~~~~
In file included from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.h:33,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:23,
from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.c:8:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_ethdev_driver.h: In function
‘rte_eth_linkstatus_set’:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_ethdev_driver.h:176:37: error:
passing argument 1 of ‘rte_atomic64_exchange’ from incompatible pointer type
[-Werror=incompatible-pointer-types]
176 | orig.val64 = rte_atomic64_exchange(dev_link,
| ^~~~~~~~
| |
| volatile uint64_t * {aka volatile
long long unsigned int *}
In file included from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_atomic.h:263,
from
.../dpdk/x86_64-native-linuxapp-gcc/include/generic/rte_cycles.h:18,
from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_cycles.h:13,
from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_spinlock.h:18,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:18,
from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.c:8:
.../dpdk/x86_64-native-linuxapp-gcc/include/rte_atomic_64.h:48:42: note:
expected ‘volatile uint64_t *’ {aka ‘volatile long unsigned int *’} but argument
is of type ‘volatile uint64_t *’ {aka ‘volatile long long unsigned int *’}
48 | rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
| ~~~~~~~~~~~~~~~~~~~^~~
cc1: all warnings being treated as errors
In file included from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.h:40,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:23,
from .../dpdk/drivers/net/bnx2x/bnx2x.c:16:
.../dpdk/drivers/net/bnx2x/bnx2x.c: In function ‘bnx2x_dma_alloc’:
.../dpdk/drivers/net/bnx2x/bnx2x_logs.h:21:3: error: format ‘%lx’ expects
argument of type ‘long unsigned int’, but argument 9 has type ‘rte_iova_t’ {aka
‘long long unsigned int’} [-Werror=format=]
21 | "[%s:%d(%s)] " fmt, __func__, __LINE__, \
| ^~~~~~~~~~~~~~
.../dpdk/drivers/net/bnx2x/bnx2x_logs.h:25:2: note: in expansion of macro
‘PMD_DRV_LOG_RAW’
25 | PMD_DRV_LOG_RAW(level, sc, fmt "\n", ## args)
| ^~~~~~~~~~~~~~~
.../dpdk/drivers/net/bnx2x/bnx2x.c:190:2: note: in expansion of macro ‘PMD_DRV_LOG’
190 | PMD_DRV_LOG(DEBUG, sc,
| ^~~~~~~~~~~
In file included from .../dpdk/x86_64-native-linuxapp-gcc/include/rte_bus_pci.h:25,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:19,
from .../dpdk/drivers/net/bnx2x/bnx2x.c:16:
/usr/include/inttypes.h:121:34: note: format string is defined here
121 | # define PRIx64 __PRI64_PREFIX "x"
In file included from .../dpdk/drivers/net/bnx2x/bnx2x_ethdev.h:40,
from .../dpdk/drivers/net/bnx2x/bnx2x.h:23,
from .../dpdk/drivers/net/bnx2x/bnx2x.c:16:
.../dpdk/drivers/net/bnx2x/bnx2x.c: In function ‘bnx2x_load_firmware’:
.../dpdk/drivers/net/bnx2x/bnx2x_logs.h:21:3: error: format ‘%lu’ expects
argument of type ‘long unsigned int’, but argument 7 has type ‘uint64_t’ {aka
‘long long unsigned int’} [-Werror=format=]
21 | "[%s:%d(%s)] " fmt, __func__, __LINE__, \
| ^~~~~~~~~~~~~~
.../dpdk/drivers/net/bnx2x/bnx2x_logs.h:25:2: note: in expansion of macro
‘PMD_DRV_LOG_RAW’
25 | PMD_DRV_LOG_RAW(level, sc, fmt "\n", ## args)
| ^~~~~~~~~~~~~~~
.../dpdk/drivers/net/bnx2x/bnx2x.c:9672:3: note: in expansion of macro ‘PMD_DRV_LOG’
9672 | PMD_DRV_LOG(NOTICE, sc,
| ^~~~~~~~~~~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH v2 0/4] net/bnx2x: update to latest FW
2019-09-23 16:33 ` Ferruh Yigit
@ 2019-09-24 15:39 ` Jerin Jacob
2019-09-24 15:57 ` Ferruh Yigit
0 siblings, 1 reply; 29+ messages in thread
From: Jerin Jacob @ 2019-09-24 15:39 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: Rasesh Mody, dev, Jerin Jacob, GR-Everest-DPDK-Dev
On Mon, Sep 23, 2019 at 10:03 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/19/2019 10:11 PM, Rasesh Mody wrote:
> > Hi,
> >
> > Currently, BNX2X PMD uses a very old firmware 7.2.51.
> > This patch series updated the base driver to use to latest
> > firmware 7.13.11. The latest firmware comprises of enhancements
> > and fixes.
> >
> > v2:
> > - Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
> > - Addressed most of checkpatch issues
> >
> > Thanks!
> > -Rasesh
> >
> > Rasesh Mody (4):
> > net/bnx2x: update and reorganize HW registers
> > net/bnx2x: update HSI code
> > net/bnx2x: update to latest FW 7.13.11
> > doc: cleanup SPDX license id usage in bnx2x guide
> >
>
> I am getting build errors with this patchset [1], since it is merged into
> next-net-mrvl, I only pulled the doc patch, 4/4, but not others, can you please
> check the patchset?
OK. We will for Rasesh input.
For some reason, it is passing with gcc 9.1.0. My build environment is
based on gcc 9.1.0, So I could not catch this.
test command:
make -j config T=x86_64-native-linux-gcc && sed -ri
's,(CONFIG_RTE_LIBRTE_BNX2X_PMD=)n,\1y,' build/.config && make -j
[master][dpdk-next-net-mrvl] $ gcc -v
Using built-in specs.
COLLECT_GCC=/usr/bin/gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-pc-linux-gnu/9.1.0/lto-wrapper
Target: x86_64-pc-linux-gnu
Configured with: /build/gcc/src/gcc/configure --prefix=/usr
--libdir=/usr/lib --libexecdir=/usr/lib --mandir=/usr/share/man
--infodir=/usr/share/info --with-bugurl=https://bugs.archlinux.org/
--enable-languages=c,c++,ada,fortran,go,lto,objc,obj-c++
--enable-shared --enable-threads=posix --with-system-zlib --with-isl
--enable-__cxa_atexit --disable-libunwind-exceptions --enable-cl
ocale=gnu --disable-libstdcxx-pch --disable-libssp
--enable-gnu-unique-object --enable-linker-build-id --enable-lto
--enable-plugin --enable-install-libiberty
--with-linker-hash-style=gnu --e
nable-gnu-indirect-function --enable-multilib --disable-werror
--enable-checking=release --enable-default-pie --enable-default-ssp
--enable-cet=auto
Thread model: posix
gcc version 9.1.0 (GCC)
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [dpdk-dev] [PATCH v2 0/4] net/bnx2x: update to latest FW
2019-09-24 15:39 ` Jerin Jacob
@ 2019-09-24 15:57 ` Ferruh Yigit
2019-09-24 16:30 ` Jerin Jacob
0 siblings, 1 reply; 29+ messages in thread
From: Ferruh Yigit @ 2019-09-24 15:57 UTC (permalink / raw)
To: Jerin Jacob; +Cc: Rasesh Mody, dev, Jerin Jacob, GR-Everest-DPDK-Dev
On 9/24/2019 4:39 PM, Jerin Jacob wrote:
> On Mon, Sep 23, 2019 at 10:03 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>>
>> On 9/19/2019 10:11 PM, Rasesh Mody wrote:
>>> Hi,
>>>
>>> Currently, BNX2X PMD uses a very old firmware 7.2.51.
>>> This patch series updated the base driver to use to latest
>>> firmware 7.13.11. The latest firmware comprises of enhancements
>>> and fixes.
>>>
>>> v2:
>>> - Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
>>> - Addressed most of checkpatch issues
>>>
>>> Thanks!
>>> -Rasesh
>>>
>>> Rasesh Mody (4):
>>> net/bnx2x: update and reorganize HW registers
>>> net/bnx2x: update HSI code
>>> net/bnx2x: update to latest FW 7.13.11
>>> doc: cleanup SPDX license id usage in bnx2x guide
>>>
>>
>> I am getting build errors with this patchset [1], since it is merged into
>> next-net-mrvl, I only pulled the doc patch, 4/4, but not others, can you please
>> check the patchset?
>
> OK. We will for Rasesh input.
>
> For some reason, it is passing with gcc 9.1.0. My build environment is
> based on gcc 9.1.0, So I could not catch this.
>
> test command:
>
> make -j config T=x86_64-native-linux-gcc && sed -ri
> 's,(CONFIG_RTE_LIBRTE_BNX2X_PMD=)n,\1y,' build/.config && make -j
>
> [master][dpdk-next-net-mrvl] $ gcc -v
> Using built-in specs.
> COLLECT_GCC=/usr/bin/gcc
> COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-pc-linux-gnu/9.1.0/lto-wrapper
> Target: x86_64-pc-linux-gnu
> Configured with: /build/gcc/src/gcc/configure --prefix=/usr
> --libdir=/usr/lib --libexecdir=/usr/lib --mandir=/usr/share/man
> --infodir=/usr/share/info --with-bugurl=https://bugs.archlinux.org/
> --enable-languages=c,c++,ada,fortran,go,lto,objc,obj-c++
> --enable-shared --enable-threads=posix --with-system-zlib --with-isl
> --enable-__cxa_atexit --disable-libunwind-exceptions --enable-cl
> ocale=gnu --disable-libstdcxx-pch --disable-libssp
> --enable-gnu-unique-object --enable-linker-build-id --enable-lto
> --enable-plugin --enable-install-libiberty
> --with-linker-hash-style=gnu --e
> nable-gnu-indirect-function --enable-multilib --disable-werror
> --enable-checking=release --enable-default-pie --enable-default-ssp
> --enable-cet=auto
> Thread model: posix
> gcc version 9.1.0 (GCC)
>
I have slightly newer one, not sure if that is the reason:
gcc version 9.2.1 20190827 (Red Hat 9.2.1-1) (GCC)
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [dpdk-dev] [PATCH v2 0/4] net/bnx2x: update to latest FW
2019-09-24 15:57 ` Ferruh Yigit
@ 2019-09-24 16:30 ` Jerin Jacob
2019-09-24 16:51 ` Rasesh Mody
0 siblings, 1 reply; 29+ messages in thread
From: Jerin Jacob @ 2019-09-24 16:30 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: Rasesh Mody, dev, Jerin Jacob, GR-Everest-DPDK-Dev
On Tue, Sep 24, 2019 at 9:27 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/24/2019 4:39 PM, Jerin Jacob wrote:
> > On Mon, Sep 23, 2019 at 10:03 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
> >>
> >> On 9/19/2019 10:11 PM, Rasesh Mody wrote:
> >>> Hi,
> >>>
> >>> Currently, BNX2X PMD uses a very old firmware 7.2.51.
> >>> This patch series updated the base driver to use to latest
> >>> firmware 7.13.11. The latest firmware comprises of enhancements
> >>> and fixes.
> >>>
> >>> v2:
> >>> - Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
> >>> - Addressed most of checkpatch issues
> >>>
> >>> Thanks!
> >>> -Rasesh
> >>>
> >>> Rasesh Mody (4):
> >>> net/bnx2x: update and reorganize HW registers
> >>> net/bnx2x: update HSI code
> >>> net/bnx2x: update to latest FW 7.13.11
> >>> doc: cleanup SPDX license id usage in bnx2x guide
> >>>
> >>
> >> I am getting build errors with this patchset [1], since it is merged into
> >> next-net-mrvl, I only pulled the doc patch, 4/4, but not others, can you please
> >> check the patchset?
> >
> > OK. We will for Rasesh input.
> >
> > For some reason, it is passing with gcc 9.1.0. My build environment is
> > based on gcc 9.1.0, So I could not catch this.
> >
> > test command:
> >
> > make -j config T=x86_64-native-linux-gcc && sed -ri
> > 's,(CONFIG_RTE_LIBRTE_BNX2X_PMD=)n,\1y,' build/.config && make -j
> >
> > [master][dpdk-next-net-mrvl] $ gcc -v
> > Using built-in specs.
> > COLLECT_GCC=/usr/bin/gcc
> > COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-pc-linux-gnu/9.1.0/lto-wrapper
> > Target: x86_64-pc-linux-gnu
> > Configured with: /build/gcc/src/gcc/configure --prefix=/usr
> > --libdir=/usr/lib --libexecdir=/usr/lib --mandir=/usr/share/man
> > --infodir=/usr/share/info --with-bugurl=https://bugs.archlinux.org/
> > --enable-languages=c,c++,ada,fortran,go,lto,objc,obj-c++
> > --enable-shared --enable-threads=posix --with-system-zlib --with-isl
> > --enable-__cxa_atexit --disable-libunwind-exceptions --enable-cl
> > ocale=gnu --disable-libstdcxx-pch --disable-libssp
> > --enable-gnu-unique-object --enable-linker-build-id --enable-lto
> > --enable-plugin --enable-install-libiberty
> > --with-linker-hash-style=gnu --e
> > nable-gnu-indirect-function --enable-multilib --disable-werror
> > --enable-checking=release --enable-default-pie --enable-default-ssp
> > --enable-cet=auto
> > Thread model: posix
> > gcc version 9.1.0 (GCC)
> >
>
>
> I have slightly newer one, not sure if that is the reason:
> gcc version 9.2.1 20190827 (Red Hat 9.2.1-1) (GCC)
OK, I could reproduce the issue with gcc 9.2.0. Something changed
between gcc 9.1.0 and gcc 9.2.0.
Rasesh,
Please fix check with gcc 9.2.1 or 9.2.0 and send the new patch.
[master][dpdk-next-net-mrvl] $ aarch64-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=aarch64-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/aarch64-linux-gnu/9.2.0/lto-wrapper
Target: aarch64-linux-gnu
Configured with: /build/aarch64-linux-gnu-gcc/src/gcc-9.2.0/configure
--prefix=/usr --program-prefix=aarch64-linux-gnu-
--with-local-prefix=/usr/aarch64-linux-gnu
--with-sysroot=/usr/aarch64-
linux-gnu --with-build-sysroot=/usr/aarch64-linux-gnu
--with-native-system-header-dir=/include --libdir=/usr/lib
--libexecdir=/usr/lib --target=aarch64-linux-gnu
--host=x86_64-pc-linux-gnu --
build=x86_64-pc-linux-gnu --disable-nls
--enable-languages=c,c++,fortran --enable-shared
--enable-threads=posix --with-system-zlib --with-isl
--enable-__cxa_atexit --disable-libunwind-excepti
ons --enable-clocale=gnu --disable-libstdcxx-pch --disable-libssp
--enable-gnu-unique-object --enable-linker-build-id --enable-lto
--enable-plugin --enable-install-libiberty --with-linker-has
h-style=gnu --enable-gnu-indirect-function --disable-multilib
--disable-werror --enable-checking=release
Thread model: posix
gcc version 9.2.0 (GCC)
[master]dell[dpdk-next-net-mrvl] $
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [dpdk-dev] [PATCH v2 0/4] net/bnx2x: update to latest FW
2019-09-24 16:30 ` Jerin Jacob
@ 2019-09-24 16:51 ` Rasesh Mody
0 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-24 16:51 UTC (permalink / raw)
To: Jerin Jacob, Ferruh Yigit
Cc: dev, Jerin Jacob Kollanukkaran, GR-Everest-DPDK-Dev
>From: Jerin Jacob <jerinjacobk@gmail.com>
>Sent: Tuesday, September 24, 2019 9:30 AM
>
>On Tue, Sep 24, 2019 at 9:27 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>>
>> On 9/24/2019 4:39 PM, Jerin Jacob wrote:
>> > On Mon, Sep 23, 2019 at 10:03 PM Ferruh Yigit <ferruh.yigit@intel.com>
>wrote:
>> >>
>> >> On 9/19/2019 10:11 PM, Rasesh Mody wrote:
>> >>> Hi,
>> >>>
>> >>> Currently, BNX2X PMD uses a very old firmware 7.2.51.
>> >>> This patch series updated the base driver to use to latest
>> >>> firmware 7.13.11. The latest firmware comprises of enhancements
>> >>> and fixes.
>> >>>
>> >>> v2:
>> >>> - Squashed pmd version patch into "net/bnx2x: update to latest FW
>7.13.11"
>> >>> - Addressed most of checkpatch issues
>> >>>
>> >>> Thanks!
>> >>> -Rasesh
>> >>>
>> >>> Rasesh Mody (4):
>> >>> net/bnx2x: update and reorganize HW registers
>> >>> net/bnx2x: update HSI code
>> >>> net/bnx2x: update to latest FW 7.13.11
>> >>> doc: cleanup SPDX license id usage in bnx2x guide
>> >>>
>> >>
>> >> I am getting build errors with this patchset [1], since it is
>> >> merged into next-net-mrvl, I only pulled the doc patch, 4/4, but
>> >> not others, can you please check the patchset?
>> >
>> > OK. We will for Rasesh input.
>> >
>> > For some reason, it is passing with gcc 9.1.0. My build environment
>> > is based on gcc 9.1.0, So I could not catch this.
>> >
>> > test command:
>> >
>> > make -j config T=x86_64-native-linux-gcc && sed -ri
>> > 's,(CONFIG_RTE_LIBRTE_BNX2X_PMD=)n,\1y,' build/.config && make -j
>> >
>> > [master][dpdk-next-net-mrvl] $ gcc -v Using built-in specs.
>> > COLLECT_GCC=/usr/bin/gcc
>> > COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-pc-linux-gnu/9.1.0/lto-
>wrapp
>> > er
>> > Target: x86_64-pc-linux-gnu
>> > Configured with: /build/gcc/src/gcc/configure --prefix=/usr
>> > --libdir=/usr/lib --libexecdir=/usr/lib --mandir=/usr/share/man
>> > --infodir=/usr/share/info --with-bugurl=https://bugs.archlinux.org/
>> > --enable-languages=c,c++,ada,fortran,go,lto,objc,obj-c++
>> > --enable-shared --enable-threads=posix --with-system-zlib --with-isl
>> > --enable-__cxa_atexit --disable-libunwind-exceptions --enable-cl
>> > ocale=gnu --disable-libstdcxx-pch --disable-libssp
>> > --enable-gnu-unique-object --enable-linker-build-id --enable-lto
>> > --enable-plugin --enable-install-libiberty
>> > --with-linker-hash-style=gnu --e nable-gnu-indirect-function
>> > --enable-multilib --disable-werror --enable-checking=release
>> > --enable-default-pie --enable-default-ssp --enable-cet=auto Thread
>> > model: posix gcc version 9.1.0 (GCC)
>> >
>>
>>
>> I have slightly newer one, not sure if that is the reason:
>> gcc version 9.2.1 20190827 (Red Hat 9.2.1-1) (GCC)
>
>
>OK, I could reproduce the issue with gcc 9.2.0. Something changed between
>gcc 9.1.0 and gcc 9.2.0.
>
>Rasesh,
>
>Please fix check with gcc 9.2.1 or 9.2.0 and send the new patch.
Sure, we didn't test with 9.2 gcc, I'll re-spin the series.
Thanks!
-Rasesh
>
>[master][dpdk-next-net-mrvl] $ aarch64-linux-gnu-gcc -v Using built-in specs.
>COLLECT_GCC=aarch64-linux-gnu-gcc
>COLLECT_LTO_WRAPPER=/usr/lib/gcc/aarch64-linux-gnu/9.2.0/lto-wrapper
>Target: aarch64-linux-gnu
>Configured with: /build/aarch64-linux-gnu-gcc/src/gcc-9.2.0/configure
>--prefix=/usr --program-prefix=aarch64-linux-gnu-
>--with-local-prefix=/usr/aarch64-linux-gnu
>--with-sysroot=/usr/aarch64-
>linux-gnu --with-build-sysroot=/usr/aarch64-linux-gnu
>--with-native-system-header-dir=/include --libdir=/usr/lib --
>libexecdir=/usr/lib --target=aarch64-linux-gnu --host=x86_64-pc-linux-gnu --
>build=x86_64-pc-linux-gnu --disable-nls --enable-languages=c,c++,fortran --
>enable-shared --enable-threads=posix --with-system-zlib --with-isl --enable-
>__cxa_atexit --disable-libunwind-excepti ons --enable-clocale=gnu --disable-
>libstdcxx-pch --disable-libssp --enable-gnu-unique-object --enable-linker-
>build-id --enable-lto --enable-plugin --enable-install-libiberty --with-linker-has
>h-style=gnu --enable-gnu-indirect-function --disable-multilib --disable-werror
>--enable-checking=release Thread model: posix gcc version 9.2.0 (GCC)
>[master]dell[dpdk-next-net-mrvl] $
^ permalink raw reply [flat|nested] 29+ messages in thread
* [dpdk-dev] [PATCH v2 1/4] net/bnx2x: update and reorganize HW registers
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (6 preceding siblings ...)
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 0/4] " Rasesh Mody
@ 2019-09-19 21:11 ` Rasesh Mody
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 2/4] net/bnx2x: update HSI code Rasesh Mody
` (6 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-19 21:11 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, jerinj, ferruh.yigit, GR-Everest-DPDK-Dev
Update and reorganize HW registers in preparation to update the firmware
to version 7.13.11.
Move HW_INTERRUT_ASSERT_SET_0 out from ecore_reg.h to bnx2x.h.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/bnx2x/bnx2x.c | 3 +-
drivers/net/bnx2x/bnx2x.h | 67 +
drivers/net/bnx2x/ecore_reg.h | 6617 ++++++++++++++++++++++-----------
3 files changed, 4553 insertions(+), 2134 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 1a088269f..d552f50e2 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -4095,7 +4095,7 @@ static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
REG_WR(sc, reg_offset, val);
rte_panic("FATAL HW block attention set0 0x%lx",
- (attn & HW_INTERRUT_ASSERT_SET_0));
+ (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
}
}
@@ -10394,7 +10394,6 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
- REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
if (!CHIP_REV_IS_SLOW(sc)) {
/* enable hw interrupt from doorbell Q */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index ceaecb031..1ea8b55c9 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -1714,6 +1714,73 @@ static const uint32_t dmae_reg_go_c[] = {
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
+#define HW_INTERRUT_ASSERT_SET_0 \
+ (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_1 \
+ (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_2 \
+ (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
+ AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
+
+#define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
+ (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
+
+#define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
+
+#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
+
#define MULTI_MASK 0x7f
#define PFS_PER_PORT(sc) \
diff --git a/drivers/net/bnx2x/ecore_reg.h b/drivers/net/bnx2x/ecore_reg.h
index 7af9a2d81..bb92d131f 100644
--- a/drivers/net/bnx2x/ecore_reg.h
+++ b/drivers/net/bnx2x/ecore_reg.h
@@ -13,2105 +13,4417 @@
#ifndef ECORE_REG_H
#define ECORE_REG_H
-
-#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \
- (0x1<<0)
-#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \
- (0x1<<2)
-#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \
- (0x1<<5)
-#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \
- (0x1<<3)
-#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \
- (0x1<<4)
-#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \
- (0x1<<1)
-#define ATC_REG_ATC_INIT_DONE \
- 0x1100bcUL
-#define ATC_REG_ATC_INT_STS_CLR \
- 0x1101c0UL
-#define ATC_REG_ATC_PRTY_MASK \
- 0x1101d8UL
-#define ATC_REG_ATC_PRTY_STS_CLR \
- 0x1101d0UL
-#define BRB1_REG_BRB1_INT_MASK \
- 0x60128UL
-#define BRB1_REG_BRB1_PRTY_MASK \
- 0x60138UL
-#define BRB1_REG_BRB1_PRTY_STS_CLR \
- 0x60130UL
-#define BRB1_REG_MAC_GUARANTIED_0 \
- 0x601e8UL
-#define BRB1_REG_MAC_GUARANTIED_1 \
- 0x60240UL
-#define BRB1_REG_NUM_OF_FULL_BLOCKS \
- 0x60090UL
-#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \
- 0x60078UL
-#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \
- 0x60068UL
-#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \
- 0x60094UL
-#define CCM_REG_CCM_INT_MASK \
- 0xd01e4UL
-#define CCM_REG_CCM_PRTY_MASK \
- 0xd01f4UL
-#define CCM_REG_CCM_PRTY_STS_CLR \
- 0xd01ecUL
-#define CDU_REG_CDU_GLOBAL_PARAMS \
- 0x101020UL
-#define CDU_REG_CDU_INT_MASK \
- 0x10103cUL
-#define CDU_REG_CDU_PRTY_MASK \
- 0x10104cUL
-#define CDU_REG_CDU_PRTY_STS_CLR \
- 0x101044UL
-#define CFC_REG_AC_INIT_DONE \
- 0x104078UL
-#define CFC_REG_CAM_INIT_DONE \
- 0x10407cUL
-#define CFC_REG_CFC_INT_MASK \
- 0x104108UL
-#define CFC_REG_CFC_INT_STS_CLR \
- 0x104100UL
-#define CFC_REG_CFC_PRTY_MASK \
- 0x104118UL
-#define CFC_REG_CFC_PRTY_STS_CLR \
- 0x104110UL
-#define CFC_REG_DEBUG0 \
- 0x104050UL
-#define CFC_REG_INIT_REG \
- 0x10404cUL
-#define CFC_REG_LL_INIT_DONE \
- 0x104074UL
-#define CFC_REG_NUM_LCIDS_INSIDE_PF \
- 0x104120UL
-#define CFC_REG_STRONG_ENABLE_PF \
- 0x104128UL
-#define CFC_REG_WEAK_ENABLE_PF \
- 0x104124UL
-#define CSDM_REG_CSDM_INT_MASK_0 \
- 0xc229cUL
-#define CSDM_REG_CSDM_INT_MASK_1 \
- 0xc22acUL
-#define CSDM_REG_CSDM_PRTY_MASK \
- 0xc22bcUL
-#define CSDM_REG_CSDM_PRTY_STS_CLR \
- 0xc22b4UL
-#define CSEM_REG_CSEM_INT_MASK_0 \
- 0x200110UL
-#define CSEM_REG_CSEM_INT_MASK_1 \
- 0x200120UL
-#define CSEM_REG_CSEM_PRTY_MASK_0 \
- 0x200130UL
-#define CSEM_REG_CSEM_PRTY_MASK_1 \
- 0x200140UL
-#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \
- 0x200128UL
-#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \
- 0x200138UL
-#define CSEM_REG_FAST_MEMORY \
- 0x220000UL
-#define CSEM_REG_INT_TABLE \
- 0x200400UL
-#define CSEM_REG_PASSIVE_BUFFER \
- 0x202000UL
-#define CSEM_REG_PRAM \
- 0x240000UL
-#define CSEM_REG_VFPF_ERR_NUM \
- 0x200380UL
-#define DBG_REG_DBG_PRTY_MASK \
- 0xc0a8UL
-#define DBG_REG_DBG_PRTY_STS_CLR \
- 0xc0a0UL
-#define DMAE_REG_BACKWARD_COMP_EN \
- 0x10207cUL
-#define DMAE_REG_CMD_MEM \
- 0x102400UL
-#define DMAE_REG_DMAE_INT_MASK \
- 0x102054UL
-#define DMAE_REG_DMAE_PRTY_MASK \
- 0x102064UL
-#define DMAE_REG_DMAE_PRTY_STS_CLR \
- 0x10205cUL
-#define DMAE_REG_GO_C0 \
- 0x102080UL
-#define DMAE_REG_GO_C1 \
- 0x102084UL
-#define DMAE_REG_GO_C10 \
- 0x102088UL
-#define DMAE_REG_GO_C11 \
- 0x10208cUL
-#define DMAE_REG_GO_C12 \
- 0x102090UL
-#define DMAE_REG_GO_C13 \
- 0x102094UL
-#define DMAE_REG_GO_C14 \
- 0x102098UL
-#define DMAE_REG_GO_C15 \
- 0x10209cUL
-#define DMAE_REG_GO_C2 \
- 0x1020a0UL
-#define DMAE_REG_GO_C3 \
- 0x1020a4UL
-#define DMAE_REG_GO_C4 \
- 0x1020a8UL
-#define DMAE_REG_GO_C5 \
- 0x1020acUL
-#define DMAE_REG_GO_C6 \
- 0x1020b0UL
-#define DMAE_REG_GO_C7 \
- 0x1020b4UL
-#define DMAE_REG_GO_C8 \
- 0x1020b8UL
-#define DMAE_REG_GO_C9 \
- 0x1020bcUL
-#define DORQ_REG_DORQ_INT_MASK \
- 0x170180UL
-#define DORQ_REG_DORQ_INT_STS_CLR \
- 0x170178UL
-#define DORQ_REG_DORQ_PRTY_MASK \
- 0x170190UL
-#define DORQ_REG_DORQ_PRTY_STS_CLR \
- 0x170188UL
-#define DORQ_REG_DPM_CID_OFST \
- 0x170030UL
-#define DORQ_REG_MAX_RVFID_SIZE \
- 0x1701ecUL
-#define DORQ_REG_NORM_CID_OFST \
- 0x17002cUL
-#define DORQ_REG_PF_USAGE_CNT \
- 0x1701d0UL
-#define DORQ_REG_VF_NORM_CID_BASE \
- 0x1701a0UL
-#define DORQ_REG_VF_NORM_CID_OFST \
- 0x1701f4UL
-#define DORQ_REG_VF_NORM_CID_WND_SIZE \
- 0x1701a4UL
-#define DORQ_REG_VF_NORM_MAX_CID_COUNT \
- 0x1701e4UL
-#define DORQ_REG_VF_NORM_VF_BASE \
- 0x1701a8UL
-#define DORQ_REG_VF_TYPE_MASK_0 \
- 0x170218UL
-#define DORQ_REG_VF_TYPE_MAX_MCID_0 \
- 0x1702d8UL
-#define DORQ_REG_VF_TYPE_MIN_MCID_0 \
- 0x170298UL
-#define DORQ_REG_VF_TYPE_VALUE_0 \
- 0x170258UL
-#define DORQ_REG_VF_USAGE_CNT \
- 0x170320UL
-#define DORQ_REG_VF_USAGE_CT_LIMIT \
- 0x170340UL
-#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \
- (0x1<<4)
-#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \
- (0x1<<0)
-#define HC_CONFIG_0_REG_INT_LINE_EN_0 \
- (0x1<<3)
-#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \
- (0x1<<7)
-#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \
- (0x1<<2)
-#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \
- (0x1<<1)
-#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \
- (0x1<<0)
-#define HC_REG_ATTN_MSG0_ADDR_L \
- 0x108018UL
-#define HC_REG_ATTN_MSG1_ADDR_L \
- 0x108020UL
-#define HC_REG_COMMAND_REG \
- 0x108180UL
-#define HC_REG_CONFIG_0 \
- 0x108000UL
-#define HC_REG_CONFIG_1 \
- 0x108004UL
-#define HC_REG_HC_PRTY_MASK \
- 0x1080a0UL
-#define HC_REG_HC_PRTY_STS_CLR \
- 0x108098UL
-#define HC_REG_INT_MASK \
- 0x108108UL
-#define HC_REG_LEADING_EDGE_0 \
- 0x108040UL
-#define HC_REG_MAIN_MEMORY \
- 0x108800UL
-#define HC_REG_MAIN_MEMORY_SIZE \
- 152
-#define HC_REG_TRAILING_EDGE_0 \
- 0x108044UL
-#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \
- (0x1<<1)
-#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \
- (0x1<<0)
-#define IGU_REG_ATTENTION_ACK_BITS \
- 0x130108UL
-#define IGU_REG_ATTN_MSG_ADDR_H \
- 0x13011cUL
-#define IGU_REG_ATTN_MSG_ADDR_L \
- 0x130120UL
-#define IGU_REG_BLOCK_CONFIGURATION \
- 0x130000UL
-#define IGU_REG_COMMAND_REG_32LSB_DATA \
- 0x130124UL
-#define IGU_REG_COMMAND_REG_CTRL \
- 0x13012cUL
-#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \
- 0x130200UL
-#define IGU_REG_IGU_PRTY_MASK \
- 0x1300a8UL
-#define IGU_REG_IGU_PRTY_STS_CLR \
- 0x1300a0UL
-#define IGU_REG_LEADING_EDGE_LATCH \
- 0x130134UL
-#define IGU_REG_MAPPING_MEMORY \
- 0x131000UL
-#define IGU_REG_MAPPING_MEMORY_SIZE \
- 136
-#define IGU_REG_PBA_STATUS_LSB \
- 0x130138UL
-#define IGU_REG_PBA_STATUS_MSB \
- 0x13013cUL
-#define IGU_REG_PCI_PF_MSIX_EN \
- 0x130144UL
-#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \
- 0x130148UL
-#define IGU_REG_PCI_PF_MSI_EN \
- 0x130140UL
-#define IGU_REG_PENDING_BITS_STATUS \
- 0x130300UL
-#define IGU_REG_PF_CONFIGURATION \
- 0x130154UL
-#define IGU_REG_PROD_CONS_MEMORY \
- 0x132000UL
-#define IGU_REG_RESET_MEMORIES \
- 0x130158UL
-#define IGU_REG_SB_INT_BEFORE_MASK_LSB \
- 0x13015cUL
-#define IGU_REG_SB_INT_BEFORE_MASK_MSB \
- 0x130160UL
-#define IGU_REG_SB_MASK_LSB \
- 0x130164UL
-#define IGU_REG_SB_MASK_MSB \
- 0x130168UL
-#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \
- 0x130800UL
-#define IGU_REG_TRAILING_EDGE_LATCH \
- 0x130104UL
-#define IGU_REG_VF_CONFIGURATION \
- 0x130170UL
-#define MCP_REG_MCPR_ACCESS_LOCK \
- 0x8009c
-#define MCP_REG_MCPR_GP_INPUTS \
- 0x800c0
-#define MCP_REG_MCPR_GP_OENABLE \
- 0x800c8
-#define MCP_REG_MCPR_GP_OUTPUTS \
- 0x800c4
-#define MCP_REG_MCPR_IMC_COMMAND \
- 0x85900
-#define MCP_REG_MCPR_IMC_DATAREG0 \
- 0x85920
-#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \
- 0x85904
-#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \
- 0x86424
-#define MCP_REG_MCPR_NVM_ADDR \
- 0x8640c
-#define MCP_REG_MCPR_NVM_CFG4 \
- 0x8642c
-#define MCP_REG_MCPR_NVM_COMMAND \
- 0x86400
-#define MCP_REG_MCPR_NVM_READ \
- 0x86410
-#define MCP_REG_MCPR_NVM_SW_ARB \
- 0x86420
-#define MCP_REG_MCPR_NVM_WRITE \
- 0x86408
-#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \
- (0x1<<1)
-#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \
- (0x1<<0)
-#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \
- 0xa42cUL
-#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \
- 0xa438UL
-#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \
- 0xa444UL
-#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \
- 0xa450UL
-#define MISC_REG_AEU_AFTER_INVERT_4_MCP \
- 0xa458UL
-#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \
- 0xa700UL
-#define MISC_REG_AEU_CLR_LATCH_SIGNAL \
- 0xa45cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \
- 0xa06cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \
- 0xa07cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \
- 0xa08cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \
- 0xa10cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \
- 0xa11cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \
- 0xa12cUL
-#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \
- 0xa078UL
-#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \
- 0xa118UL
-#define MISC_REG_AEU_ENABLE4_NIG_0 \
- 0xa0f8UL
-#define MISC_REG_AEU_ENABLE4_NIG_1 \
- 0xa198UL
-#define MISC_REG_AEU_ENABLE4_PXP_0 \
- 0xa108UL
-#define MISC_REG_AEU_ENABLE4_PXP_1 \
- 0xa1a8UL
-#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \
- 0xa688UL
-#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \
- 0xa6b0UL
-#define MISC_REG_AEU_GENERAL_ATTN_0 \
- 0xa000UL
-#define MISC_REG_AEU_GENERAL_ATTN_1 \
- 0xa004UL
-#define MISC_REG_AEU_GENERAL_ATTN_10 \
- 0xa028UL
-#define MISC_REG_AEU_GENERAL_ATTN_11 \
- 0xa02cUL
-#define MISC_REG_AEU_GENERAL_ATTN_12 \
- 0xa030UL
-#define MISC_REG_AEU_GENERAL_ATTN_2 \
- 0xa008UL
-#define MISC_REG_AEU_GENERAL_ATTN_3 \
- 0xa00cUL
-#define MISC_REG_AEU_GENERAL_ATTN_4 \
- 0xa010UL
-#define MISC_REG_AEU_GENERAL_ATTN_5 \
- 0xa014UL
-#define MISC_REG_AEU_GENERAL_ATTN_6 \
- 0xa018UL
-#define MISC_REG_AEU_GENERAL_ATTN_7 \
- 0xa01cUL
-#define MISC_REG_AEU_GENERAL_ATTN_8 \
- 0xa020UL
-#define MISC_REG_AEU_GENERAL_ATTN_9 \
- 0xa024UL
-#define MISC_REG_AEU_GENERAL_MASK \
- 0xa61cUL
-#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \
- 0xa060UL
-#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \
- 0xa064UL
-#define MISC_REG_BOND_ID \
- 0xa400UL
-#define MISC_REG_CHIP_NUM \
- 0xa408UL
-#define MISC_REG_CHIP_REV \
- 0xa40cUL
-#define MISC_REG_CHIP_TYPE \
- 0xac60UL
-#define MISC_REG_CHIP_TYPE_57811_MASK \
- (1<<1)
-#define MISC_REG_CPMU_LP_DR_ENABLE \
- 0xa858UL
-#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \
- 0xa84cUL
-#define MISC_REG_CPMU_LP_IDLE_THR_P0 \
- 0xa8a0UL
-#define MISC_REG_CPMU_LP_MASK_ENT_P0 \
- 0xa880UL
-#define MISC_REG_CPMU_LP_MASK_EXT_P0 \
- 0xa888UL
-#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \
- 0xa8b8UL
-#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \
- 0xa8bcUL
-#define MISC_REG_DRIVER_CONTROL_1 \
- 0xa510UL
-#define MISC_REG_DRIVER_CONTROL_7 \
- 0xa3c8UL
-#define MISC_REG_FOUR_PORT_PATH_SWAP \
- 0xa75cUL
-#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \
- 0xa738UL
-#define MISC_REG_FOUR_PORT_PORT_SWAP \
- 0xa754UL
-#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \
- 0xa734UL
-#define MISC_REG_GENERIC_CR_0 \
- 0xa460UL
-#define MISC_REG_GENERIC_CR_1 \
- 0xa464UL
-#define MISC_REG_GENERIC_POR_1 \
- 0xa474UL
-#define MISC_REG_GEN_PURP_HWG \
- 0xa9a0UL
-#define MISC_REG_GPIO \
- 0xa490UL
-#define MISC_REG_GPIO_EVENT_EN \
- 0xa2bcUL
-#define MISC_REG_GPIO_INT \
- 0xa494UL
-#define MISC_REG_GRC_RSV_ATTN \
- 0xa3c0UL
-#define MISC_REG_GRC_TIMEOUT_ATTN \
- 0xa3c4UL
-#define MISC_REG_LCPLL_E40_PWRDWN \
- 0xaa74UL
-#define MISC_REG_LCPLL_E40_RESETB_ANA \
- 0xaa78UL
-#define MISC_REG_LCPLL_E40_RESETB_DIG \
- 0xaa7cUL
-#define MISC_REG_MISC_INT_MASK \
- 0xa388UL
-#define MISC_REG_MISC_PRTY_MASK \
- 0xa398UL
-#define MISC_REG_MISC_PRTY_STS_CLR \
- 0xa390UL
-#define MISC_REG_PORT4MODE_EN \
- 0xa750UL
-#define MISC_REG_PORT4MODE_EN_OVWR \
- 0xa720UL
-#define MISC_REG_RESET_REG_1 \
- 0xa580UL
-#define MISC_REG_RESET_REG_2 \
- 0xa590UL
-#define MISC_REG_SHARED_MEM_ADDR \
- 0xa2b4UL
-#define MISC_REG_SPIO \
- 0xa4fcUL
-#define MISC_REG_SPIO_EVENT_EN \
- 0xa2b8UL
-#define MISC_REG_SPIO_INT \
- 0xa500UL
-#define MISC_REG_TWO_PORT_PATH_SWAP \
- 0xa758UL
-#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \
- 0xa72cUL
-#define MISC_REG_UNPREPARED \
- 0xa424UL
-#define MISC_REG_WC0_CTRL_PHY_ADDR \
- 0xa9ccUL
-#define MISC_REG_WC0_RESET \
- 0xac30UL
-#define MISC_REG_XMAC_CORE_PORT_MODE \
- 0xa964UL
-#define MISC_REG_XMAC_PHY_PORT_MODE \
- 0xa960UL
-#define MSTAT_REG_RX_STAT_GR64_LO \
- 0x200UL
-#define MSTAT_REG_TX_STAT_GTXPOK_LO \
- 0UL
-#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \
- (0x1<<0)
-#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \
- (0x1<<0)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \
- (0x1<<0)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \
- (0x1<<9)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \
- (0x1<<15)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \
- (0xf<<18)
-#define NIG_REG_BMAC0_IN_EN \
- 0x100acUL
-#define NIG_REG_BMAC0_OUT_EN \
- 0x100e0UL
-#define NIG_REG_BMAC0_PAUSE_OUT_EN \
- 0x10110UL
-#define NIG_REG_BMAC0_REGS_OUT_EN \
- 0x100e8UL
-#define NIG_REG_BRB0_PAUSE_IN_EN \
- 0x100c4UL
-#define NIG_REG_BRB1_PAUSE_IN_EN \
- 0x100c8UL
-#define NIG_REG_DEBUG_PACKET_LB \
- 0x10800UL
-#define NIG_REG_EGRESS_DRAIN0_MODE \
- 0x10060UL
-#define NIG_REG_EGRESS_EMAC0_OUT_EN \
- 0x10120UL
-#define NIG_REG_EGRESS_EMAC0_PORT \
- 0x10058UL
-#define NIG_REG_EMAC0_IN_EN \
- 0x100a4UL
-#define NIG_REG_EMAC0_PAUSE_OUT_EN \
- 0x10118UL
-#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \
- 0x10494UL
-#define NIG_REG_INGRESS_BMAC0_MEM \
- 0x10c00UL
-#define NIG_REG_INGRESS_BMAC1_MEM \
- 0x11000UL
-#define NIG_REG_INGRESS_EOP_LB_EMPTY \
- 0x104e0UL
-#define NIG_REG_INGRESS_EOP_LB_FIFO \
- 0x104e4UL
-#define NIG_REG_LATCH_BC_0 \
- 0x16210UL
-#define NIG_REG_LATCH_STATUS_0 \
- 0x18000UL
-#define NIG_REG_LED_10G_P0 \
- 0x10320UL
-#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \
- 0x10318UL
-#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \
- 0x10310UL
-#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \
- 0x10308UL
-#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \
- 0x102f8UL
-#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \
- 0x10300UL
-#define NIG_REG_LED_MODE_P0 \
- 0x102f0UL
-#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \
- 0x16070UL
-#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \
- 0x16074UL
-#define NIG_REG_LLFC_ENABLE_0 \
- 0x16208UL
-#define NIG_REG_LLFC_ENABLE_1 \
- 0x1620cUL
-#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \
- 0x16058UL
-#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \
- 0x1605cUL
-#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \
- 0x16060UL
-#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \
- 0x16064UL
-#define NIG_REG_LLFC_OUT_EN_0 \
- 0x160c8UL
-#define NIG_REG_LLFC_OUT_EN_1 \
- 0x160ccUL
-#define NIG_REG_LLH0_BRB1_DRV_MASK \
- 0x10244UL
-#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \
- 0x16048UL
-#define NIG_REG_LLH0_BRB1_NOT_MCP \
- 0x1025cUL
-#define NIG_REG_LLH0_CLS_TYPE \
- 0x16080UL
-#define NIG_REG_LLH0_FUNC_EN \
- 0x160fcUL
-#define NIG_REG_LLH0_FUNC_MEM \
- 0x16180UL
-#define NIG_REG_LLH0_FUNC_MEM_ENABLE \
- 0x16140UL
-#define NIG_REG_LLH0_FUNC_VLAN_ID \
- 0x16100UL
-#define NIG_REG_LLH0_XCM_MASK \
- 0x10130UL
-#define NIG_REG_LLH1_BRB1_NOT_MCP \
- 0x102dcUL
-#define NIG_REG_LLH1_CLS_TYPE \
- 0x16084UL
-#define NIG_REG_LLH1_FUNC_MEM \
- 0x161c0UL
-#define NIG_REG_LLH1_FUNC_MEM_ENABLE \
- 0x16160UL
-#define NIG_REG_LLH1_FUNC_MEM_SIZE \
- 16
-#define NIG_REG_LLH1_MF_MODE \
- 0x18614UL
-#define NIG_REG_LLH1_XCM_MASK \
- 0x10134UL
-#define NIG_REG_LLH_E1HOV_MODE \
- 0x160d8UL
-#define NIG_REG_LLH_MF_MODE \
- 0x16024UL
-#define NIG_REG_MASK_INTERRUPT_PORT0 \
- 0x10330UL
-#define NIG_REG_MASK_INTERRUPT_PORT1 \
- 0x10334UL
-#define NIG_REG_NIG_EMAC0_EN \
- 0x1003cUL
-#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \
- 0x10044UL
-#define NIG_REG_NIG_INT_STS_CLR_0 \
- 0x103b4UL
-#define NIG_REG_NIG_PRTY_MASK \
- 0x103dcUL
-#define NIG_REG_NIG_PRTY_MASK_0 \
- 0x183c8UL
-#define NIG_REG_NIG_PRTY_MASK_1 \
- 0x183d8UL
-#define NIG_REG_NIG_PRTY_STS_CLR \
- 0x103d4UL
-#define NIG_REG_NIG_PRTY_STS_CLR_0 \
- 0x183c0UL
-#define NIG_REG_NIG_PRTY_STS_CLR_1 \
- 0x183d0UL
-#define NIG_REG_P0_HDRS_AFTER_BASIC \
- 0x18038UL
-#define NIG_REG_P0_HWPFC_ENABLE \
- 0x18078UL
-#define NIG_REG_P0_LLH_FUNC_MEM2 \
- 0x18480UL
-#define NIG_REG_P0_MAC_IN_EN \
- 0x185acUL
-#define NIG_REG_P0_MAC_OUT_EN \
- 0x185b0UL
-#define NIG_REG_P0_MAC_PAUSE_OUT_EN \
- 0x185b4UL
-#define NIG_REG_P0_PKT_PRIORITY_TO_COS \
- 0x18054UL
-#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \
- 0x18058UL
-#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \
- 0x1805cUL
-#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \
- 0x186b0UL
-#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \
- 0x186b4UL
-#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \
- 0x186b8UL
-#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \
- 0x186bcUL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \
- 0x180f0UL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
- 0x18688UL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
- 0x1868cUL
-#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \
- 0x180e8UL
-#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
- 0x180ecUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \
- 0x1810cUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \
- 0x18110UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \
- 0x18114UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \
- 0x18118UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \
- 0x1811cUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \
- 0x186a0UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \
- 0x186a4UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \
- 0x186a8UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \
- 0x186acUL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \
- 0x180f8UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \
- 0x180fcUL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \
- 0x18100UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \
- 0x18104UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \
- 0x18108UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \
- 0x18690UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \
- 0x18694UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \
- 0x18698UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \
- 0x1869cUL
-#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \
- 0x180f4UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \
- 0x180e4UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \
- 0x18680UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \
- 0x18684UL
-#define NIG_REG_P1_HDRS_AFTER_BASIC \
- 0x1818cUL
-#define NIG_REG_P1_HWPFC_ENABLE \
- 0x181d0UL
-#define NIG_REG_P1_LLH_FUNC_MEM2 \
- 0x184c0UL
-#define NIG_REG_P1_MAC_IN_EN \
- 0x185c0UL
-#define NIG_REG_P1_MAC_OUT_EN \
- 0x185c4UL
-#define NIG_REG_P1_MAC_PAUSE_OUT_EN \
- 0x185c8UL
-#define NIG_REG_P1_PKT_PRIORITY_TO_COS \
- 0x181a8UL
-#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \
- 0x181acUL
-#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \
- 0x181b0UL
-#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \
- 0x186f8UL
-#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
- 0x186e8UL
-#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
- 0x186ecUL
-#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \
- 0x18234UL
-#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
- 0x18238UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \
- 0x18258UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \
- 0x1825cUL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \
- 0x18260UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \
- 0x18264UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \
- 0x18268UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \
- 0x186f4UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \
- 0x18244UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \
- 0x18248UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \
- 0x1824cUL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \
- 0x18250UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \
- 0x18254UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \
- 0x186f0UL
-#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \
- 0x18240UL
-#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \
- 0x186e0UL
-#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \
- 0x186e4UL
-#define NIG_REG_PAUSE_ENABLE_0 \
- 0x160c0UL
-#define NIG_REG_PAUSE_ENABLE_1 \
- 0x160c4UL
-#define NIG_REG_PORT_SWAP \
- 0x10394UL
-#define NIG_REG_PPP_ENABLE_0 \
- 0x160b0UL
-#define NIG_REG_PPP_ENABLE_1 \
- 0x160b4UL
-#define NIG_REG_PRS_REQ_IN_EN \
- 0x100b8UL
-#define NIG_REG_SERDES0_CTRL_MD_DEVAD \
- 0x10370UL
-#define NIG_REG_SERDES0_CTRL_MD_ST \
- 0x1036cUL
-#define NIG_REG_SERDES0_CTRL_PHY_ADDR \
- 0x10374UL
-#define NIG_REG_SERDES0_STATUS_LINK_STATUS \
- 0x10578UL
-#define NIG_REG_STAT0_BRB_DISCARD \
- 0x105f0UL
-#define NIG_REG_STAT0_BRB_TRUNCATE \
- 0x105f8UL
-#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \
- 0x10750UL
-#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \
- 0x10760UL
-#define NIG_REG_STAT1_BRB_DISCARD \
- 0x10628UL
-#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \
- 0x107a0UL
-#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \
- 0x107b0UL
-#define NIG_REG_STAT2_BRB_OCTET \
- 0x107e0UL
-#define NIG_REG_STATUS_INTERRUPT_PORT0 \
- 0x10328UL
-#define NIG_REG_STRAP_OVERRIDE \
- 0x10398UL
-#define NIG_REG_XCM0_OUT_EN \
- 0x100f0UL
-#define NIG_REG_XCM1_OUT_EN \
- 0x100f4UL
-#define NIG_REG_XGXS0_CTRL_MD_DEVAD \
- 0x1033cUL
-#define NIG_REG_XGXS0_CTRL_MD_ST \
- 0x10338UL
-#define NIG_REG_XGXS0_CTRL_PHY_ADDR \
- 0x10340UL
-#define NIG_REG_XGXS0_STATUS_LINK10G \
- 0x10680UL
-#define NIG_REG_XGXS0_STATUS_LINK_STATUS \
- 0x10684UL
-#define NIG_REG_XGXS_LANE_SEL_P0 \
- 0x102e8UL
-#define NIG_REG_XGXS_SERDES0_MODE_SEL \
- 0x102e0UL
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \
- (0x1<<0)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \
- (0x1<<9)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \
- (0x1<<15)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \
- (0xf<<18)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \
- 18
-#define PBF_REG_COS0_UPPER_BOUND \
- 0x15c05cUL
-#define PBF_REG_COS0_UPPER_BOUND_P0 \
- 0x15c2ccUL
-#define PBF_REG_COS0_UPPER_BOUND_P1 \
- 0x15c2e4UL
-#define PBF_REG_COS0_WEIGHT \
- 0x15c054UL
-#define PBF_REG_COS0_WEIGHT_P0 \
- 0x15c2a8UL
-#define PBF_REG_COS0_WEIGHT_P1 \
- 0x15c2c0UL
-#define PBF_REG_COS1_UPPER_BOUND \
- 0x15c060UL
-#define PBF_REG_COS1_WEIGHT \
- 0x15c058UL
-#define PBF_REG_COS1_WEIGHT_P0 \
- 0x15c2acUL
-#define PBF_REG_COS1_WEIGHT_P1 \
- 0x15c2c4UL
-#define PBF_REG_COS2_WEIGHT_P0 \
- 0x15c2b0UL
-#define PBF_REG_COS2_WEIGHT_P1 \
- 0x15c2c8UL
-#define PBF_REG_COS3_WEIGHT_P0 \
- 0x15c2b4UL
-#define PBF_REG_COS4_WEIGHT_P0 \
- 0x15c2b8UL
-#define PBF_REG_COS5_WEIGHT_P0 \
- 0x15c2bcUL
-#define PBF_REG_CREDIT_LB_Q \
- 0x140338UL
-#define PBF_REG_CREDIT_Q0 \
- 0x14033cUL
-#define PBF_REG_CREDIT_Q1 \
- 0x140340UL
-#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \
- 0x14005cUL
-#define PBF_REG_DISABLE_PF \
- 0x1402e8UL
-#define PBF_REG_DISABLE_VF \
- 0x1402ecUL
-#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \
- 0x15c288UL
-#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \
- 0x15c28cUL
-#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \
- 0x15c278UL
-#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \
- 0x15c27cUL
-#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \
- 0x15c280UL
-#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \
- 0x15c284UL
-#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \
- 0x15c2a0UL
-#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \
- 0x15c2a4UL
-#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \
- 0x15c270UL
-#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \
- 0x15c274UL
-#define PBF_REG_ETS_ENABLED \
- 0x15c050UL
-#define PBF_REG_HDRS_AFTER_BASIC \
- 0x15c0a8UL
-#define PBF_REG_HDRS_AFTER_TAG_0 \
- 0x15c0b8UL
-#define PBF_REG_HIGH_PRIORITY_COS_NUM \
- 0x15c04cUL
-#define PBF_REG_INIT_CRD_LB_Q \
- 0x15c248UL
-#define PBF_REG_INIT_CRD_Q0 \
- 0x15c230UL
-#define PBF_REG_INIT_CRD_Q1 \
- 0x15c234UL
-#define PBF_REG_INIT_P0 \
- 0x140004UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \
- 0x140354UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \
- 0x140358UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \
- 0x14035cUL
-#define PBF_REG_MUST_HAVE_HDRS \
- 0x15c0c4UL
-#define PBF_REG_NUM_STRICT_ARB_SLOTS \
- 0x15c064UL
-#define PBF_REG_P0_ARB_THRSH \
- 0x1400e4UL
-#define PBF_REG_P0_CREDIT \
- 0x140200UL
-#define PBF_REG_P0_INIT_CRD \
- 0x1400d0UL
-#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \
- 0x140308UL
-#define PBF_REG_P0_PAUSE_ENABLE \
- 0x140014UL
-#define PBF_REG_P0_TQ_LINES_FREED_CNT \
- 0x1402f0UL
-#define PBF_REG_P0_TQ_OCCUPANCY \
- 0x1402fcUL
-#define PBF_REG_P1_CREDIT \
- 0x140208UL
-#define PBF_REG_P1_INIT_CRD \
- 0x1400d4UL
-#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \
- 0x14030cUL
-#define PBF_REG_P1_TQ_LINES_FREED_CNT \
- 0x1402f4UL
-#define PBF_REG_P1_TQ_OCCUPANCY \
- 0x140300UL
-#define PBF_REG_P4_CREDIT \
- 0x140210UL
-#define PBF_REG_P4_INIT_CRD \
- 0x1400e0UL
-#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \
- 0x140310UL
-#define PBF_REG_P4_TQ_LINES_FREED_CNT \
- 0x1402f8UL
-#define PBF_REG_P4_TQ_OCCUPANCY \
- 0x140304UL
-#define PBF_REG_PBF_INT_MASK \
- 0x1401d4UL
-#define PBF_REG_PBF_PRTY_MASK \
- 0x1401e4UL
-#define PBF_REG_PBF_PRTY_STS_CLR \
- 0x1401dcUL
-#define PBF_REG_TAG_ETHERTYPE_0 \
- 0x15c090UL
-#define PBF_REG_TAG_LEN_0 \
- 0x15c09cUL
-#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \
- 0x14038cUL
-#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \
- 0x140390UL
-#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \
- 0x140394UL
-#define PBF_REG_TQ_OCCUPANCY_LB_Q \
- 0x1403a8UL
-#define PBF_REG_TQ_OCCUPANCY_Q0 \
- 0x1403acUL
-#define PBF_REG_TQ_OCCUPANCY_Q1 \
- 0x1403b0UL
-#define PB_REG_PB_INT_MASK \
- 0x28UL
-#define PB_REG_PB_PRTY_MASK \
- 0x38UL
-#define PB_REG_PB_PRTY_STS_CLR \
- 0x30UL
-#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \
- (0x1<<0)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \
- (0x1<<8)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \
- (0x1<<1)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \
- (0x1<<6)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \
- (0x1<<7)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \
- (0x1<<4)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \
- (0x1<<3)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \
- (0x1<<5)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \
- (0x1<<2)
-#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \
- 0x9418UL
-#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
- 0x9478UL
-#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR \
- 0x947cUL
-#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR \
- 0x9480UL
-#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR \
- 0x9474UL
-#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
- 0x942cUL
-#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
- 0x9430UL
-#define PGLUE_B_REG_INTERNAL_VFID_ENABLE \
- 0x9438UL
-#define PGLUE_B_REG_PGLUE_B_INT_STS \
- 0x9298UL
-#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \
- 0x929cUL
-#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \
- 0x92b4UL
-#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \
- 0x92acUL
-#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \
- 0x9458UL
-#define PGLUE_B_REG_TAGS_63_32 \
- 0x9244UL
-#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \
- 0x9470UL
-#define PRS_REG_A_PRSU_20 \
- 0x40134UL
-#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \
- 0x4011cUL
-#define PRS_REG_E1HOV_MODE \
- 0x401c8UL
-#define PRS_REG_HDRS_AFTER_BASIC \
- 0x40238UL
-#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \
- 0x40270UL
-#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \
- 0x40290UL
-#define PRS_REG_HDRS_AFTER_TAG_0 \
- 0x40248UL
-#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \
- 0x40280UL
-#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \
- 0x402a0UL
-#define PRS_REG_MUST_HAVE_HDRS \
- 0x40254UL
-#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \
- 0x4028cUL
-#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \
- 0x402acUL
-#define PRS_REG_NIC_MODE \
- 0x40138UL
-#define PRS_REG_NUM_OF_PACKETS \
- 0x40124UL
-#define PRS_REG_PRS_PRTY_MASK \
- 0x401a4UL
-#define PRS_REG_PRS_PRTY_STS_CLR \
- 0x4019cUL
-#define PRS_REG_TAG_ETHERTYPE_0 \
- 0x401d4UL
-#define PRS_REG_TAG_LEN_0 \
- 0x4022cUL
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \
- (0x1<<19)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \
- (0x1<<20)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \
- (0x1<<22)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \
- (0x1<<23)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \
- (0x1<<24)
-#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \
- (0x1<<7)
-#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \
- (0x1<<7)
-#define PXP2_REG_PGL_ADDR_88_F0 \
- 0x120534UL
-#define PXP2_REG_PGL_ADDR_88_F1 \
- 0x120544UL
-#define PXP2_REG_PGL_ADDR_8C_F0 \
- 0x120538UL
-#define PXP2_REG_PGL_ADDR_8C_F1 \
- 0x120548UL
-#define PXP2_REG_PGL_ADDR_90_F0 \
- 0x12053cUL
-#define PXP2_REG_PGL_ADDR_90_F1 \
- 0x12054cUL
-#define PXP2_REG_PGL_ADDR_94_F0 \
- 0x120540UL
-#define PXP2_REG_PGL_ADDR_94_F1 \
- 0x120550UL
-#define PXP2_REG_PGL_EXP_ROM2 \
- 0x120808UL
-#define PXP2_REG_PGL_PRETEND_FUNC_F0 \
- 0x120674UL
-#define PXP2_REG_PGL_PRETEND_FUNC_F1 \
- 0x120678UL
-#define PXP2_REG_PGL_TAGS_LIMIT \
- 0x1205a8UL
-#define PXP2_REG_PSWRQ_BW_ADD1 \
- 0x1201c0UL
-#define PXP2_REG_PSWRQ_BW_ADD10 \
- 0x1201e4UL
-#define PXP2_REG_PSWRQ_BW_ADD11 \
- 0x1201e8UL
-#define PXP2_REG_PSWRQ_BW_ADD2 \
- 0x1201c4UL
-#define PXP2_REG_PSWRQ_BW_ADD28 \
- 0x120228UL
-#define PXP2_REG_PSWRQ_BW_ADD3 \
- 0x1201c8UL
-#define PXP2_REG_PSWRQ_BW_ADD6 \
- 0x1201d4UL
-#define PXP2_REG_PSWRQ_BW_ADD7 \
- 0x1201d8UL
-#define PXP2_REG_PSWRQ_BW_ADD8 \
- 0x1201dcUL
-#define PXP2_REG_PSWRQ_BW_ADD9 \
- 0x1201e0UL
-#define PXP2_REG_PSWRQ_BW_L1 \
- 0x1202b0UL
-#define PXP2_REG_PSWRQ_BW_L10 \
- 0x1202d4UL
-#define PXP2_REG_PSWRQ_BW_L11 \
- 0x1202d8UL
-#define PXP2_REG_PSWRQ_BW_L2 \
- 0x1202b4UL
-#define PXP2_REG_PSWRQ_BW_L28 \
- 0x120318UL
-#define PXP2_REG_PSWRQ_BW_L3 \
- 0x1202b8UL
-#define PXP2_REG_PSWRQ_BW_L6 \
- 0x1202c4UL
-#define PXP2_REG_PSWRQ_BW_L7 \
- 0x1202c8UL
-#define PXP2_REG_PSWRQ_BW_L8 \
- 0x1202ccUL
-#define PXP2_REG_PSWRQ_BW_L9 \
- 0x1202d0UL
-#define PXP2_REG_PSWRQ_BW_RD \
- 0x120324UL
-#define PXP2_REG_PSWRQ_BW_UB1 \
- 0x120238UL
-#define PXP2_REG_PSWRQ_BW_UB10 \
- 0x12025cUL
-#define PXP2_REG_PSWRQ_BW_UB11 \
- 0x120260UL
-#define PXP2_REG_PSWRQ_BW_UB2 \
- 0x12023cUL
-#define PXP2_REG_PSWRQ_BW_UB28 \
- 0x1202a0UL
-#define PXP2_REG_PSWRQ_BW_UB3 \
- 0x120240UL
-#define PXP2_REG_PSWRQ_BW_UB6 \
- 0x12024cUL
-#define PXP2_REG_PSWRQ_BW_UB7 \
- 0x120250UL
-#define PXP2_REG_PSWRQ_BW_UB8 \
- 0x120254UL
-#define PXP2_REG_PSWRQ_BW_UB9 \
- 0x120258UL
-#define PXP2_REG_PSWRQ_BW_WR \
- 0x120328UL
-#define PXP2_REG_PSWRQ_CDU0_L2P \
- 0x120000UL
-#define PXP2_REG_PSWRQ_QM0_L2P \
- 0x120038UL
-#define PXP2_REG_PSWRQ_SRC0_L2P \
- 0x120054UL
-#define PXP2_REG_PSWRQ_TM0_L2P \
- 0x12001cUL
-#define PXP2_REG_PXP2_INT_MASK_0 \
- 0x120578UL
-#define PXP2_REG_PXP2_INT_MASK_1 \
- 0x120614UL
-#define PXP2_REG_PXP2_INT_STS_0 \
- 0x12056cUL
-#define PXP2_REG_PXP2_INT_STS_1 \
- 0x120608UL
-#define PXP2_REG_PXP2_INT_STS_CLR_0 \
- 0x120570UL
-#define PXP2_REG_PXP2_PRTY_MASK_0 \
- 0x120588UL
-#define PXP2_REG_PXP2_PRTY_MASK_1 \
- 0x120598UL
-#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \
- 0x120580UL
-#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \
- 0x120590UL
-#define PXP2_REG_RD_BLK_CNT \
- 0x120418UL
-#define PXP2_REG_RD_CDURD_SWAP_MODE \
- 0x120404UL
-#define PXP2_REG_RD_DISABLE_INPUTS \
- 0x120374UL
-#define PXP2_REG_RD_INIT_DONE \
- 0x120370UL
-#define PXP2_REG_RD_PBF_SWAP_MODE \
- 0x1203f4UL
-#define PXP2_REG_RD_PORT_IS_IDLE_0 \
- 0x12041cUL
-#define PXP2_REG_RD_PORT_IS_IDLE_1 \
- 0x120420UL
-#define PXP2_REG_RD_QM_SWAP_MODE \
- 0x1203f8UL
-#define PXP2_REG_RD_SRC_SWAP_MODE \
- 0x120400UL
-#define PXP2_REG_RD_SR_CNT \
- 0x120414UL
-#define PXP2_REG_RD_START_INIT \
- 0x12036cUL
-#define PXP2_REG_RD_TM_SWAP_MODE \
- 0x1203fcUL
-#define PXP2_REG_RQ_BW_RD_ADD0 \
- 0x1201bcUL
-#define PXP2_REG_RQ_BW_RD_ADD12 \
- 0x1201ecUL
-#define PXP2_REG_RQ_BW_RD_ADD13 \
- 0x1201f0UL
-#define PXP2_REG_RQ_BW_RD_ADD14 \
- 0x1201f4UL
-#define PXP2_REG_RQ_BW_RD_ADD15 \
- 0x1201f8UL
-#define PXP2_REG_RQ_BW_RD_ADD16 \
- 0x1201fcUL
-#define PXP2_REG_RQ_BW_RD_ADD17 \
- 0x120200UL
-#define PXP2_REG_RQ_BW_RD_ADD18 \
- 0x120204UL
-#define PXP2_REG_RQ_BW_RD_ADD19 \
- 0x120208UL
-#define PXP2_REG_RQ_BW_RD_ADD20 \
- 0x12020cUL
-#define PXP2_REG_RQ_BW_RD_ADD22 \
- 0x120210UL
-#define PXP2_REG_RQ_BW_RD_ADD23 \
- 0x120214UL
-#define PXP2_REG_RQ_BW_RD_ADD24 \
- 0x120218UL
-#define PXP2_REG_RQ_BW_RD_ADD25 \
- 0x12021cUL
-#define PXP2_REG_RQ_BW_RD_ADD26 \
- 0x120220UL
-#define PXP2_REG_RQ_BW_RD_ADD27 \
- 0x120224UL
-#define PXP2_REG_RQ_BW_RD_ADD4 \
- 0x1201ccUL
-#define PXP2_REG_RQ_BW_RD_ADD5 \
- 0x1201d0UL
-#define PXP2_REG_RQ_BW_RD_L0 \
- 0x1202acUL
-#define PXP2_REG_RQ_BW_RD_L12 \
- 0x1202dcUL
-#define PXP2_REG_RQ_BW_RD_L13 \
- 0x1202e0UL
-#define PXP2_REG_RQ_BW_RD_L14 \
- 0x1202e4UL
-#define PXP2_REG_RQ_BW_RD_L15 \
- 0x1202e8UL
-#define PXP2_REG_RQ_BW_RD_L16 \
- 0x1202ecUL
-#define PXP2_REG_RQ_BW_RD_L17 \
- 0x1202f0UL
-#define PXP2_REG_RQ_BW_RD_L18 \
- 0x1202f4UL
-#define PXP2_REG_RQ_BW_RD_L19 \
- 0x1202f8UL
-#define PXP2_REG_RQ_BW_RD_L20 \
- 0x1202fcUL
-#define PXP2_REG_RQ_BW_RD_L22 \
- 0x120300UL
-#define PXP2_REG_RQ_BW_RD_L23 \
- 0x120304UL
-#define PXP2_REG_RQ_BW_RD_L24 \
- 0x120308UL
-#define PXP2_REG_RQ_BW_RD_L25 \
- 0x12030cUL
-#define PXP2_REG_RQ_BW_RD_L26 \
- 0x120310UL
-#define PXP2_REG_RQ_BW_RD_L27 \
- 0x120314UL
-#define PXP2_REG_RQ_BW_RD_L4 \
- 0x1202bcUL
-#define PXP2_REG_RQ_BW_RD_L5 \
- 0x1202c0UL
-#define PXP2_REG_RQ_BW_RD_UBOUND0 \
- 0x120234UL
-#define PXP2_REG_RQ_BW_RD_UBOUND12 \
- 0x120264UL
-#define PXP2_REG_RQ_BW_RD_UBOUND13 \
- 0x120268UL
-#define PXP2_REG_RQ_BW_RD_UBOUND14 \
- 0x12026cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND15 \
- 0x120270UL
-#define PXP2_REG_RQ_BW_RD_UBOUND16 \
- 0x120274UL
-#define PXP2_REG_RQ_BW_RD_UBOUND17 \
- 0x120278UL
-#define PXP2_REG_RQ_BW_RD_UBOUND18 \
- 0x12027cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND19 \
- 0x120280UL
-#define PXP2_REG_RQ_BW_RD_UBOUND20 \
- 0x120284UL
-#define PXP2_REG_RQ_BW_RD_UBOUND22 \
- 0x120288UL
-#define PXP2_REG_RQ_BW_RD_UBOUND23 \
- 0x12028cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND24 \
- 0x120290UL
-#define PXP2_REG_RQ_BW_RD_UBOUND25 \
- 0x120294UL
-#define PXP2_REG_RQ_BW_RD_UBOUND26 \
- 0x120298UL
-#define PXP2_REG_RQ_BW_RD_UBOUND27 \
- 0x12029cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND4 \
- 0x120244UL
-#define PXP2_REG_RQ_BW_RD_UBOUND5 \
- 0x120248UL
-#define PXP2_REG_RQ_BW_WR_ADD29 \
- 0x12022cUL
-#define PXP2_REG_RQ_BW_WR_ADD30 \
- 0x120230UL
-#define PXP2_REG_RQ_BW_WR_L29 \
- 0x12031cUL
-#define PXP2_REG_RQ_BW_WR_L30 \
- 0x120320UL
-#define PXP2_REG_RQ_BW_WR_UBOUND29 \
- 0x1202a4UL
-#define PXP2_REG_RQ_BW_WR_UBOUND30 \
- 0x1202a8UL
-#define PXP2_REG_RQ_CDU_ENDIAN_M \
- 0x1201a0UL
-#define PXP2_REG_RQ_CDU_FIRST_ILT \
- 0x12061cUL
-#define PXP2_REG_RQ_CDU_LAST_ILT \
- 0x120620UL
-#define PXP2_REG_RQ_CDU_P_SIZE \
- 0x120018UL
-#define PXP2_REG_RQ_CFG_DONE \
- 0x1201b4UL
-#define PXP2_REG_RQ_DBG_ENDIAN_M \
- 0x1201a4UL
-#define PXP2_REG_RQ_DISABLE_INPUTS \
- 0x120330UL
-#define PXP2_REG_RQ_DRAM_ALIGN \
- 0x1205b0UL
-#define PXP2_REG_RQ_DRAM_ALIGN_RD \
- 0x12092cUL
-#define PXP2_REG_RQ_DRAM_ALIGN_SEL \
- 0x120930UL
-#define PXP2_REG_RQ_HC_ENDIAN_M \
- 0x1201a8UL
-#define PXP2_REG_RQ_ONCHIP_AT \
- 0x122000UL
-#define PXP2_REG_RQ_ONCHIP_AT_B0 \
- 0x128000UL
-#define PXP2_REG_RQ_PDR_LIMIT \
- 0x12033cUL
-#define PXP2_REG_RQ_QM_ENDIAN_M \
- 0x120194UL
-#define PXP2_REG_RQ_QM_FIRST_ILT \
- 0x120634UL
-#define PXP2_REG_RQ_QM_LAST_ILT \
- 0x120638UL
-#define PXP2_REG_RQ_QM_P_SIZE \
- 0x120050UL
-#define PXP2_REG_RQ_RBC_DONE \
- 0x1201b0UL
-#define PXP2_REG_RQ_RD_MBS0 \
- 0x120160UL
-#define PXP2_REG_RQ_RD_MBS1 \
- 0x120168UL
-#define PXP2_REG_RQ_SRC_ENDIAN_M \
- 0x12019cUL
-#define PXP2_REG_RQ_SRC_FIRST_ILT \
- 0x12063cUL
-#define PXP2_REG_RQ_SRC_LAST_ILT \
- 0x120640UL
-#define PXP2_REG_RQ_SRC_P_SIZE \
- 0x12006cUL
-#define PXP2_REG_RQ_TM_ENDIAN_M \
- 0x120198UL
-#define PXP2_REG_RQ_TM_FIRST_ILT \
- 0x120644UL
-#define PXP2_REG_RQ_TM_LAST_ILT \
- 0x120648UL
-#define PXP2_REG_RQ_TM_P_SIZE \
- 0x120034UL
-#define PXP2_REG_RQ_WR_MBS0 \
- 0x12015cUL
-#define PXP2_REG_RQ_WR_MBS1 \
- 0x120164UL
-#define PXP2_REG_WR_CDU_MPS \
- 0x1205f0UL
-#define PXP2_REG_WR_CSDM_MPS \
- 0x1205d0UL
-#define PXP2_REG_WR_DBG_MPS \
- 0x1205e8UL
-#define PXP2_REG_WR_DMAE_MPS \
- 0x1205ecUL
-#define PXP2_REG_WR_HC_MPS \
- 0x1205c8UL
-#define PXP2_REG_WR_QM_MPS \
- 0x1205dcUL
-#define PXP2_REG_WR_SRC_MPS \
- 0x1205e4UL
-#define PXP2_REG_WR_TM_MPS \
- 0x1205e0UL
-#define PXP2_REG_WR_TSDM_MPS \
- 0x1205d4UL
-#define PXP2_REG_WR_USDMDP_TH \
- 0x120348UL
-#define PXP2_REG_WR_USDM_MPS \
- 0x1205ccUL
-#define PXP2_REG_WR_XSDM_MPS \
- 0x1205d8UL
-#define PXP_REG_HST_DISCARD_DOORBELLS \
- 0x1030a4UL
-#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \
- 0x1030a8UL
-#define PXP_REG_HST_ZONE_PERMISSION_TABLE \
- 0x103400UL
-#define PXP_REG_PXP_INT_MASK_0 \
- 0x103074UL
-#define PXP_REG_PXP_INT_MASK_1 \
- 0x103084UL
-#define PXP_REG_PXP_INT_STS_CLR_0 \
- 0x10306cUL
-#define PXP_REG_PXP_INT_STS_CLR_1 \
- 0x10307cUL
-#define PXP_REG_PXP_PRTY_MASK \
- 0x103094UL
-#define PXP_REG_PXP_PRTY_STS_CLR \
- 0x10308cUL
-#define QM_REG_BASEADDR \
- 0x168900UL
-#define QM_REG_BASEADDR_EXT_A \
- 0x16e100UL
-#define QM_REG_BYTECRDCMDQ_0 \
- 0x16e6e8UL
-#define QM_REG_CONNNUM_0 \
- 0x168020UL
-#define QM_REG_PF_EN \
- 0x16e70cUL
-#define QM_REG_PF_USG_CNT_0 \
- 0x16e040UL
-#define QM_REG_PTRTBL \
- 0x168a00UL
-#define QM_REG_PTRTBL_EXT_A \
- 0x16e200UL
-#define QM_REG_QM_INT_MASK \
- 0x168444UL
-#define QM_REG_QM_PRTY_MASK \
- 0x168454UL
-#define QM_REG_QM_PRTY_STS_CLR \
- 0x16844cUL
-#define QM_REG_QVOQIDX_0 \
- 0x1680f4UL
-#define QM_REG_SOFT_RESET \
- 0x168428UL
-#define QM_REG_VOQQMASK_0_LSB \
- 0x168240UL
-#define SEM_FAST_REG_PARITY_RST \
- 0x18840UL
-#define SRC_REG_COUNTFREE0 \
- 0x40500UL
-#define SRC_REG_FIRSTFREE0 \
- 0x40510UL
-#define SRC_REG_KEYSEARCH_0 \
- 0x40458UL
-#define SRC_REG_KEYSEARCH_1 \
- 0x4045cUL
-#define SRC_REG_KEYSEARCH_2 \
- 0x40460UL
-#define SRC_REG_KEYSEARCH_3 \
- 0x40464UL
-#define SRC_REG_KEYSEARCH_4 \
- 0x40468UL
-#define SRC_REG_KEYSEARCH_5 \
- 0x4046cUL
-#define SRC_REG_KEYSEARCH_6 \
- 0x40470UL
-#define SRC_REG_KEYSEARCH_7 \
- 0x40474UL
-#define SRC_REG_KEYSEARCH_8 \
- 0x40478UL
-#define SRC_REG_KEYSEARCH_9 \
- 0x4047cUL
-#define SRC_REG_LASTFREE0 \
- 0x40530UL
-#define SRC_REG_NUMBER_HASH_BITS0 \
- 0x40400UL
-#define SRC_REG_SOFT_RST \
- 0x4049cUL
-#define SRC_REG_SRC_PRTY_MASK \
- 0x404c8UL
-#define SRC_REG_SRC_PRTY_STS_CLR \
- 0x404c0UL
-#define TCM_REG_PRS_IFEN \
- 0x50020UL
-#define TCM_REG_TCM_INT_MASK \
- 0x501dcUL
-#define TCM_REG_TCM_PRTY_MASK \
- 0x501ecUL
-#define TCM_REG_TCM_PRTY_STS_CLR \
- 0x501e4UL
-#define TM_REG_EN_LINEAR0_TIMER \
- 0x164014UL
-#define TM_REG_LIN0_MAX_ACTIVE_CID \
- 0x164048UL
-#define TM_REG_LIN0_NUM_SCANS \
- 0x1640a0UL
-#define TM_REG_LIN0_SCAN_ON \
- 0x1640d0UL
-#define TM_REG_LIN0_SCAN_TIME \
- 0x16403cUL
-#define TM_REG_LIN0_VNIC_UC \
- 0x164128UL
-#define TM_REG_TM_INT_MASK \
- 0x1640fcUL
-#define TM_REG_TM_PRTY_MASK \
- 0x16410cUL
-#define TM_REG_TM_PRTY_STS_CLR \
- 0x164104UL
-#define TSDM_REG_ENABLE_IN1 \
- 0x42238UL
-#define TSDM_REG_TSDM_INT_MASK_0 \
- 0x4229cUL
-#define TSDM_REG_TSDM_INT_MASK_1 \
- 0x422acUL
-#define TSDM_REG_TSDM_PRTY_MASK \
- 0x422bcUL
-#define TSDM_REG_TSDM_PRTY_STS_CLR \
- 0x422b4UL
-#define TSEM_REG_FAST_MEMORY \
- 0x1a0000UL
-#define TSEM_REG_INT_TABLE \
- 0x180400UL
-#define TSEM_REG_PASSIVE_BUFFER \
- 0x181000UL
-#define TSEM_REG_PRAM \
- 0x1c0000UL
-#define TSEM_REG_TSEM_INT_MASK_0 \
- 0x180100UL
-#define TSEM_REG_TSEM_INT_MASK_1 \
- 0x180110UL
-#define TSEM_REG_TSEM_PRTY_MASK_0 \
- 0x180120UL
-#define TSEM_REG_TSEM_PRTY_MASK_1 \
- 0x180130UL
-#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \
- 0x180118UL
-#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \
- 0x180128UL
-#define TSEM_REG_VFPF_ERR_NUM \
- 0x180380UL
-#define UCM_REG_UCM_INT_MASK \
- 0xe01d4UL
-#define UCM_REG_UCM_PRTY_MASK \
- 0xe01e4UL
-#define UCM_REG_UCM_PRTY_STS_CLR \
- 0xe01dcUL
-#define UMAC_COMMAND_CONFIG_REG_HD_ENA \
- (0x1<<10)
-#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \
- (0x1<<28)
-#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \
- (0x1<<15)
-#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \
- (0x1<<24)
-#define UMAC_COMMAND_CONFIG_REG_PAD_EN \
- (0x1<<5)
-#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \
- (0x1<<8)
-#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \
- (0x1<<4)
-#define UMAC_COMMAND_CONFIG_REG_RX_ENA \
- (0x1<<1)
-#define UMAC_COMMAND_CONFIG_REG_SW_RESET \
- (0x1<<13)
-#define UMAC_COMMAND_CONFIG_REG_TX_ENA \
- (0x1<<0)
-#define UMAC_REG_COMMAND_CONFIG \
- 0x8UL
-#define UMAC_REG_EEE_WAKE_TIMER \
- 0x6cUL
-#define UMAC_REG_MAC_ADDR0 \
- 0xcUL
-#define UMAC_REG_MAC_ADDR1 \
- 0x10UL
-#define UMAC_REG_MAXFR \
- 0x14UL
-#define UMAC_REG_UMAC_EEE_CTRL \
- 0x64UL
-#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \
- (0x1<<3)
-#define USDM_REG_USDM_INT_MASK_0 \
- 0xc42a0UL
-#define USDM_REG_USDM_INT_MASK_1 \
- 0xc42b0UL
-#define USDM_REG_USDM_PRTY_MASK \
- 0xc42c0UL
-#define USDM_REG_USDM_PRTY_STS_CLR \
- 0xc42b8UL
-#define USEM_REG_FAST_MEMORY \
- 0x320000UL
-#define USEM_REG_INT_TABLE \
- 0x300400UL
-#define USEM_REG_PASSIVE_BUFFER \
- 0x302000UL
-#define USEM_REG_PRAM \
- 0x340000UL
-#define USEM_REG_USEM_INT_MASK_0 \
- 0x300110UL
-#define USEM_REG_USEM_INT_MASK_1 \
- 0x300120UL
-#define USEM_REG_USEM_PRTY_MASK_0 \
- 0x300130UL
-#define USEM_REG_USEM_PRTY_MASK_1 \
- 0x300140UL
-#define USEM_REG_USEM_PRTY_STS_CLR_0 \
- 0x300128UL
-#define USEM_REG_USEM_PRTY_STS_CLR_1 \
- 0x300138UL
-#define USEM_REG_VFPF_ERR_NUM \
- 0x300380UL
-#define VFC_MEMORIES_RST_REG_CAM_RST \
- (0x1<<0)
-#define VFC_MEMORIES_RST_REG_RAM_RST \
- (0x1<<1)
-#define VFC_REG_MEMORIES_RST \
- 0x1943cUL
-#define XCM_REG_XCM_INT_MASK \
- 0x202b4UL
-#define XCM_REG_XCM_PRTY_MASK \
- 0x202c4UL
-#define XCM_REG_XCM_PRTY_STS_CLR \
- 0x202bcUL
-#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \
- (0x1<<0)
-#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \
- (0x1<<1)
-#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \
- (0x1<<2)
-#define XMAC_CTRL_REG_RX_EN \
- (0x1<<1)
-#define XMAC_CTRL_REG_SOFT_RESET \
- (0x1<<6)
-#define XMAC_CTRL_REG_TX_EN \
- (0x1<<0)
-#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \
- (0x1<<7)
-#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \
- (0x1<<18)
-#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \
- (0x1<<17)
-#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \
- (0x1<<1)
-#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \
- (0x1<<0)
-#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \
- (0x1<<3)
-#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \
- (0x1<<4)
-#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \
- (0x1<<5)
-#define XMAC_REG_CLEAR_RX_LSS_STATUS \
- 0x60UL
-#define XMAC_REG_CTRL \
- 0UL
-#define XMAC_REG_CTRL_SA_HI \
- 0x2cUL
-#define XMAC_REG_CTRL_SA_LO \
- 0x28UL
-#define XMAC_REG_EEE_CTRL \
- 0xd8UL
-#define XMAC_REG_EEE_TIMERS_HI \
- 0xe4UL
-#define XMAC_REG_PAUSE_CTRL \
- 0x68UL
-#define XMAC_REG_PFC_CTRL \
- 0x70UL
-#define XMAC_REG_PFC_CTRL_HI \
- 0x74UL
-#define XMAC_REG_RX_LSS_CTRL \
- 0x50UL
-#define XMAC_REG_RX_LSS_STATUS \
- 0x58UL
-#define XMAC_REG_RX_MAX_SIZE \
- 0x40UL
-#define XMAC_REG_TX_CTRL \
- 0x20UL
-#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \
- (0x1<<0)
-#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \
- (0x1<<1)
-#define XSDM_REG_OPERATION_GEN \
- 0x1664c4UL
-#define XSDM_REG_XSDM_INT_MASK_0 \
- 0x16629cUL
-#define XSDM_REG_XSDM_INT_MASK_1 \
- 0x1662acUL
-#define XSDM_REG_XSDM_PRTY_MASK \
- 0x1662bcUL
-#define XSDM_REG_XSDM_PRTY_STS_CLR \
- 0x1662b4UL
-#define XSEM_REG_FAST_MEMORY \
- 0x2a0000UL
-#define XSEM_REG_INT_TABLE \
- 0x280400UL
-#define XSEM_REG_PASSIVE_BUFFER \
- 0x282000UL
-#define XSEM_REG_PRAM \
- 0x2c0000UL
-#define XSEM_REG_VFPF_ERR_NUM \
- 0x280380UL
-#define XSEM_REG_XSEM_INT_MASK_0 \
- 0x280110UL
-#define XSEM_REG_XSEM_INT_MASK_1 \
- 0x280120UL
-#define XSEM_REG_XSEM_PRTY_MASK_0 \
- 0x280130UL
-#define XSEM_REG_XSEM_PRTY_MASK_1 \
- 0x280140UL
-#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \
- 0x280128UL
-#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \
- 0x280138UL
-#define MCPR_ACCESS_LOCK_LOCK (1L<<31)
-#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
-#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
-#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
-#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
-#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
-#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
-#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
-#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
-#define MCPR_NVM_COMMAND_DOIT (1L<<4)
-#define MCPR_NVM_COMMAND_DONE (1L<<3)
-#define MCPR_NVM_COMMAND_FIRST (1L<<7)
-#define MCPR_NVM_COMMAND_LAST (1L<<8)
-#define MCPR_NVM_COMMAND_WR (1L<<5)
-#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
-#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
-#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
-
-
-#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
-#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
-#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
-#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
-#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
-#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
-#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
-#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
-#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
-#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
-#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
-#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
-#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
-#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
-#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
-#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
-#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
-#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
-#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
-#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
-#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
-#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
-#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
-#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
-#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
-#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
-#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
-#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
-#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
-#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
-#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
-
-
-#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
-#define EMAC_LED_100MB_OVERRIDE (1L<<2)
-#define EMAC_LED_10MB_OVERRIDE (1L<<3)
-#define EMAC_LED_OVERRIDE (1L<<0)
-#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
-#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
-#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
-#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
-#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
-#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
-#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
-#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
-#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
-#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
-#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
-#define EMAC_MDIO_STATUS_10MB (1L<<1)
-#define EMAC_MODE_25G_MODE (1L<<5)
-#define EMAC_MODE_HALF_DUPLEX (1L<<1)
-#define EMAC_MODE_PORT_GMII (2L<<2)
-#define EMAC_MODE_PORT_MII (1L<<2)
-#define EMAC_MODE_PORT_MII_10M (3L<<2)
-#define EMAC_MODE_RESET (1L<<0)
-#define EMAC_REG_EMAC_LED 0xc
-#define EMAC_REG_EMAC_MAC_MATCH 0x10
-#define EMAC_REG_EMAC_MDIO_COMM 0xac
-#define EMAC_REG_EMAC_MDIO_MODE 0xb4
-#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
-#define EMAC_REG_EMAC_MODE 0x0
-#define EMAC_REG_EMAC_RX_MODE 0xc8
-#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
-#define EMAC_REG_EMAC_RX_STAT_AC 0x180
-#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
-#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
-#define EMAC_REG_EMAC_TX_MODE 0xbc
-#define EMAC_REG_EMAC_TX_STAT_AC 0x280
-#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
-#define EMAC_REG_RX_PFC_MODE 0x320
-#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
-#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
-#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
-#define EMAC_REG_RX_PFC_PARAM 0x324
-#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
-#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
-#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
-#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
-#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
-#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
-#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
-#define EMAC_RX_MODE_FLOW_EN (1L<<2)
-#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
-#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
-#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
-#define EMAC_RX_MODE_RESET (1L<<0)
-#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
-#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
-#define EMAC_TX_MODE_FLOW_EN (1L<<4)
-#define EMAC_TX_MODE_RESET (1L<<0)
-
-
-#define MISC_REGISTERS_GPIO_0 0
-#define MISC_REGISTERS_GPIO_1 1
-#define MISC_REGISTERS_GPIO_2 2
-#define MISC_REGISTERS_GPIO_3 3
-#define MISC_REGISTERS_GPIO_CLR_POS 16
-#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
-#define MISC_REGISTERS_GPIO_FLOAT_POS 24
-#define MISC_REGISTERS_GPIO_HIGH 1
-#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
-#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
-#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
-#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
-#define MISC_REGISTERS_GPIO_INT_SET_POS 16
-#define MISC_REGISTERS_GPIO_LOW 0
-#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
-#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
-#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
-#define MISC_REGISTERS_GPIO_SET_POS 8
-#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
-#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \
- (0x1<<19)
-#define MISC_REGISTERS_RESET_REG_1_RST_HC \
- (0x1<<29)
-#define MISC_REGISTERS_RESET_REG_1_RST_PXP \
- (0x1<<26)
-#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \
- (0x1<<27)
-#define MISC_REGISTERS_RESET_REG_1_RST_QM \
- (0x1<<17)
-#define MISC_REGISTERS_RESET_REG_1_SET 0x584
-#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
-#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \
- (0x1<<24)
-#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \
- (0x1<<25)
-#define MISC_REGISTERS_RESET_REG_2_PGLC \
- (0x1<<19)
-#define MISC_REGISTERS_RESET_REG_2_RST_ATC \
- (0x1<<17)
-#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \
- (0x1<<14)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \
- (0x1<<15)
-#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
-#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \
- (0x1<<11)
-#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \
- (0x1<<13)
-#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \
- (0x1<<16)
-#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
-#define MISC_REGISTERS_RESET_REG_2_SET 0x594
-#define MISC_REGISTERS_RESET_REG_2_UMAC0 \
- (0x1<<20)
-#define MISC_REGISTERS_RESET_REG_2_UMAC1 \
- (0x1<<21)
-#define MISC_REGISTERS_RESET_REG_2_XMAC \
- (0x1<<22)
-#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \
- (0x1<<23)
-#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
-#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
-#define MISC_SPIO_CLR_POS 16
-#define MISC_SPIO_FLOAT (0xffL<<24)
-#define MISC_SPIO_FLOAT_POS 24
-#define MISC_SPIO_INPUT_HI_Z 2
-#define MISC_SPIO_INT_OLD_SET_POS 16
-#define MISC_SPIO_OUTPUT_HIGH 1
-#define MISC_SPIO_OUTPUT_LOW 0
-#define MISC_SPIO_SET_POS 8
-#define MISC_SPIO_SPIO4 0x10
-#define MISC_SPIO_SPIO5 0x20
-#define HW_LOCK_MAX_RESOURCE_VALUE 31
-#define HW_LOCK_RESOURCE_DRV_FLAGS 10
-#define HW_LOCK_RESOURCE_GPIO 1
-#define HW_LOCK_RESOURCE_MDIO 0
-#define HW_LOCK_RESOURCE_NVRAM 12
-#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
-#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
-#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
-#define HW_LOCK_RESOURCE_RECOVERY_REG 11
-#define HW_LOCK_RESOURCE_RESET 5
-#define HW_LOCK_RESOURCE_SPIO 2
-
-
-#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
-#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
-#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1U<<31)
-#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
-#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
-#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
-#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
-#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
-#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
-#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
-#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
-#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
-#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
-#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
-#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
-#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
-#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
-#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
-#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
-#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
-#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
-#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
-#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
-#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
-#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
-#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
-#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
-#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
-#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
-#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
-#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
-#define HW_PRTY_ASSERT_SET_0 \
-(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_1 \
-(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_2 \
-(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_3 \
-(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
-#define HW_PRTY_ASSERT_SET_4 \
-(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
-#define HW_INTERRUT_ASSERT_SET_0 \
-(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
-#define HW_INTERRUT_ASSERT_SET_1 \
-(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
-#define HW_INTERRUT_ASSERT_SET_2 \
-(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
-
-
+#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1 << 0)
+#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1 << 2)
+#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1 << 5)
+#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1 << 3)
+#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1 << 4)
+#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1 << 1)
+/* [R 1] ATC initalization done */
+#define ATC_REG_ATC_INIT_DONE 0x1100bc
+/* [RW 6] Interrupt mask register #0 read/write */
+#define ATC_REG_ATC_INT_MASK 0x1101c8
+/* [R 6] Interrupt register #0 read */
+#define ATC_REG_ATC_INT_STS 0x1101bc
+/* [RC 6] Interrupt register #0 read clear */
+#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
+/* [RW 5] Parity mask register #0 read/write */
+#define ATC_REG_ATC_PRTY_MASK 0x1101d8
+/* [R 5] Parity register #0 read */
+#define ATC_REG_ATC_PRTY_STS 0x1101cc
+/* [RC 5] Parity register #0 read clear */
+#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
+/* [RW 19] Interrupt mask register #0 read/write */
+#define BRB1_REG_BRB1_INT_MASK 0x60128
+/* [R 19] Interrupt register #0 read */
+#define BRB1_REG_BRB1_INT_STS 0x6011c
+/* [RC 19] Interrupt register #0 read clear */
+#define BRB1_REG_BRB1_INT_STS_CLR 0x60120
+/* [RW 4] Parity mask register #0 read/write */
+#define BRB1_REG_BRB1_PRTY_MASK 0x60138
+/* [R 4] Parity register #0 read */
+#define BRB1_REG_BRB1_PRTY_STS 0x6012c
+/* [RC 4] Parity register #0 read clear */
+#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
+/* [RW 11] The number of blocks guarantied for the MAC port. The register is
+ * applicable only when per_class_guaranty_mode is reset.
+ */
+#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
+#define BRB1_REG_MAC_GUARANTIED_1 0x60240
+/* [R 24] The number of full blocks. */
+#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
+/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
+#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
+/* [RW 10] Write client 0: Assert pause threshold. Not Functional */
+#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
+/* [R 24] The number of full blocks occpied by port. */
+#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
+/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
+#define CCM_REG_CAM_OCCUP 0xd0188
+/* [RW 11] Interrupt mask register #0 read/write */
+#define CCM_REG_CCM_INT_MASK 0xd01e4
+/* [R 11] Interrupt register #0 read */
+#define CCM_REG_CCM_INT_STS 0xd01d8
+/* [RC 11] Interrupt register #0 read clear */
+#define CCM_REG_CCM_INT_STS_CLR 0xd01dc
+/* [RW 27] Parity mask register #0 read/write */
+#define CCM_REG_CCM_PRTY_MASK 0xd01f4
+/* [R 27] Parity register #0 read */
+#define CCM_REG_CCM_PRTY_STS 0xd01e8
+/* [RC 27] Parity register #0 read clear */
+#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define CCM_REG_CFC_INIT_CRD 0xd0204
+/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define CCM_REG_CQM_INIT_CRD 0xd020c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the SDM interface is detected.
+ */
+#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
+/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define CCM_REG_FIC0_INIT_CRD 0xd0210
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define CCM_REG_FIC1_INIT_CRD 0xd0214
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the pbf interface is detected.
+ */
+#define CCM_REG_PBF_LENGTH_MIS 0xd0180
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the STORM interface is detected.
+ */
+#define CCM_REG_STORM_LENGTH_MIS 0xd016c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the tsem interface is detected.
+ */
+#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
+/* [RC 1] Set when message length mismatch (relative to last indication) at
+ * the usem interface is detected.
+ */
+#define CCM_REG_USEM_LENGTH_MIS 0xd017c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the xsem interface is detected.
+ */
+#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
+/* [RW 19] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - message length; [12:6] - message
+ * pointer; 18:13] - next pointer.
+ */
+#define CCM_REG_XX_DESCR_TABLE 0xd0300
+#define CCM_REG_XX_DESCR_TABLE_SIZE 24
+/* [R 7] Used to read the value of XX protection Free counter. */
+#define CCM_REG_XX_FREE 0xd0184
+#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
+/* [RW 7] Interrupt mask register #0 read/write */
+#define CDU_REG_CDU_INT_MASK 0x10103c
+/* [R 7] Interrupt register #0 read */
+#define CDU_REG_CDU_INT_STS 0x101030
+/* [RC 7] Interrupt register #0 read clear */
+#define CDU_REG_CDU_INT_STS_CLR 0x101034
+/* [RW 5] Parity mask register #0 read/write */
+#define CDU_REG_CDU_PRTY_MASK 0x10104c
+/* [R 5] Parity register #0 read */
+#define CDU_REG_CDU_PRTY_STS 0x101040
+/* [RC 5] Parity register #0 read clear */
+#define CDU_REG_CDU_PRTY_STS_CLR 0x101044
+/* [RW 32] logging of error data in case of a CDU load error:
+ * {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
+ * ype_error; ctual_active; ctual_compressed_context};
+ */
+#define CDU_REG_ERROR_DATA 0x101014
+/* [RW 13] activity counter ram access */
+#define CFC_REG_ACTIVITY_COUNTER 0x104400
+#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
+/* [R 1] indication the initializing the activity counter by the hardware
+ * was done.
+ */
+#define CFC_REG_AC_INIT_DONE 0x104078
+/* [R 1] indication the initializing the cams by the hardware was done. */
+#define CFC_REG_CAM_INIT_DONE 0x10407c
+/* [RW 2] Interrupt mask register #0 read/write */
+#define CFC_REG_CFC_INT_MASK 0x104108
+/* [R 2] Interrupt register #0 read */
+#define CFC_REG_CFC_INT_STS 0x1040fc
+/* [RC 2] Interrupt register #0 read clear */
+#define CFC_REG_CFC_INT_STS_CLR 0x104100
+/* [RW 6] Parity mask register #0 read/write */
+#define CFC_REG_CFC_PRTY_MASK 0x104118
+/* [R 6] Parity register #0 read */
+#define CFC_REG_CFC_PRTY_STS 0x10410c
+/* [RC 6] Parity register #0 read clear */
+#define CFC_REG_CFC_PRTY_STS_CLR 0x104110
+/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
+#define CFC_REG_CID_CAM 0x104800
+#define CFC_REG_DEBUG0 0x104050
+/* [R 16] CFC error vector. when the CFC detects an internal error it will
+ * set one of these bits. the bit description can be found in CFC
+ * specifications
+ */
+#define CFC_REG_ERROR_VECTOR 0x10403c
+/* [WB 97] LCID info ram access = {96-vpf; 5:93-pfid; 2:89-type;
+ * 8:85-action; 4-paddrv; 3:20-paddr; 9:4-rstates; -lsf; :0-lstate}
+ */
+#define CFC_REG_INFO_RAM 0x105000
+#define CFC_REG_INFO_RAM_SIZE 1024
+#define CFC_REG_INIT_REG 0x10404c
+/* [RW 22] Link List ram access; data = {prev_pfid; rev_lcid; ext_pfid;
+ * ext_lcid}
+ */
+#define CFC_REG_LINK_LIST 0x104c00
+#define CFC_REG_LINK_LIST_SIZE 256
+/* [R 1] indication the initializing the link list by the hardware was done. */
+#define CFC_REG_LL_INIT_DONE 0x104074
+/* [R 9] Number of allocated LCIDs which are at empty state */
+#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
+/* [R 9] Number of Arriving LCIDs in Link List Block */
+#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
+#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
+/* [R 9] Number of Leaving LCIDs in Link List Block */
+#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
+#define CFC_REG_STRONG_ENABLE_PF 0x104128
+#define CFC_REG_WEAK_ENABLE_PF 0x104124
+/* [RW 32] Interrupt mask register #0 read/write */
+#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
+#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
+/* [R 32] Interrupt register #0 read */
+#define CSDM_REG_CSDM_INT_STS_0 0xc2290
+#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
+/* [RC 32] Interrupt register #0 read clear */
+#define CSDM_REG_CSDM_INT_STS_CLR_0 0xc2294
+#define CSDM_REG_CSDM_INT_STS_CLR_1 0xc22a4
+/* [RW 11] Parity mask register #0 read/write */
+#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
+/* [R 11] Parity register #0 read */
+#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
+/* [RC 11] Parity register #0 read clear */
+#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define CSEM_REG_CSEM_INT_MASK_0 0x200110
+#define CSEM_REG_CSEM_INT_MASK_1 0x200120
+/* [R 32] Interrupt register #0 read */
+#define CSEM_REG_CSEM_INT_STS_0 0x200104
+#define CSEM_REG_CSEM_INT_STS_1 0x200114
+/* [RC 32] Interrupt register #0 read clear */
+#define CSEM_REG_CSEM_INT_STS_CLR_0 0x200108
+#define CSEM_REG_CSEM_INT_STS_CLR_1 0x200118
+/* [RW 32] Parity mask register #0 read/write */
+#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
+#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
+/* [R 32] Parity register #0 read */
+#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
+#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
+/* [RC 32] Parity register #0 read clear */
+#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
+#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each
+ * SEM_FAST register offset.
+ */
+#define CSEM_REG_FAST_MEMORY 0x220000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define CSEM_REG_INT_TABLE 0x200400
+/* [WB 128] Debug only. Passive buffer memory */
+#define CSEM_REG_PASSIVE_BUFFER 0x202000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define CSEM_REG_PRAM 0x240000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
+ */
+#define CSEM_REG_VFPF_ERR_NUM 0x200380
+/* [RW 2] Interrupt mask register #0 read/write */
+#define DBG_REG_DBG_INT_MASK 0xc098
+/* [R 2] Interrupt register #0 read */
+#define DBG_REG_DBG_INT_STS 0xc08c
+/* [RC 2] Interrupt register #0 read clear */
+#define DBG_REG_DBG_INT_STS_CLR 0xc090
+/* [RW 1] Parity mask register #0 read/write */
+#define DBG_REG_DBG_PRTY_MASK 0xc0a8
+/* [R 1] Parity register #0 read */
+#define DBG_REG_DBG_PRTY_STS 0xc09c
+/* [RC 1] Parity register #0 read clear */
+#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
+/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
+ * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID = 0;
+ * 4.Completion function=0; 5.Error handling = 0
+ */
+#define DMAE_REG_BACKWARD_COMP_EN 0x10207c
+/* [RW 32] Commands memory. The address to command X; row Y is to calculated
+ * as 14 * X+Y.
+ */
+#define DMAE_REG_CMD_MEM 0x102400
+#define DMAE_REG_CMD_MEM_SIZE 224
+/* [RW 2] Interrupt mask register #0 read/write */
+#define DMAE_REG_DMAE_INT_MASK 0x102054
+/* [R 2] Interrupt register #0 read */
+#define DMAE_REG_DMAE_INT_STS 0x102048
+/* [RC 2] Interrupt register #0 read clear */
+#define DMAE_REG_DMAE_INT_STS_CLR 0x10204c
+/* [RW 4] Parity mask register #0 read/write */
+#define DMAE_REG_DMAE_PRTY_MASK 0x102064
+/* [R 4] Parity register #0 read */
+#define DMAE_REG_DMAE_PRTY_STS 0x102058
+/* [RC 4] Parity register #0 read clear */
+#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
+/* [RW 1] Command 0 go. */
+#define DMAE_REG_GO_C0 0x102080
+/* [RW 1] Command 1 go. */
+#define DMAE_REG_GO_C1 0x102084
+/* [RW 1] Command 10 go. */
+#define DMAE_REG_GO_C10 0x102088
+/* [RW 1] Command 11 go. */
+#define DMAE_REG_GO_C11 0x10208c
+/* [RW 1] Command 12 go. */
+#define DMAE_REG_GO_C12 0x102090
+/* [RW 1] Command 13 go. */
+#define DMAE_REG_GO_C13 0x102094
+/* [RW 1] Command 14 go. */
+#define DMAE_REG_GO_C14 0x102098
+/* [RW 1] Command 15 go. */
+#define DMAE_REG_GO_C15 0x10209c
+/* [RW 1] Command 2 go. */
+#define DMAE_REG_GO_C2 0x1020a0
+/* [RW 1] Command 3 go. */
+#define DMAE_REG_GO_C3 0x1020a4
+/* [RW 1] Command 4 go. */
+#define DMAE_REG_GO_C4 0x1020a8
+/* [RW 1] Command 5 go. */
+#define DMAE_REG_GO_C5 0x1020ac
+/* [RW 1] Command 6 go. */
+#define DMAE_REG_GO_C6 0x1020b0
+/* [RW 1] Command 7 go. */
+#define DMAE_REG_GO_C7 0x1020b4
+/* [RW 1] Command 8 go. */
+#define DMAE_REG_GO_C8 0x1020b8
+/* [RW 1] Command 9 go. */
+#define DMAE_REG_GO_C9 0x1020bc
+/* [RW 32] Doorbell address for RBC doorbells (function 0). */
+#define DORQ_REG_DB_ADDR0 0x17008c
+/* [RW 6] Interrupt mask register #0 read/write */
+#define DORQ_REG_DORQ_INT_MASK 0x170180
+/* [R 6] Interrupt register #0 read */
+#define DORQ_REG_DORQ_INT_STS 0x170174
+/* [RC 6] Interrupt register #0 read clear */
+#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
+/* [RW 2] Parity mask register #0 read/write */
+#define DORQ_REG_DORQ_PRTY_MASK 0x170190
+/* [R 2] Parity register #0 read */
+#define DORQ_REG_DORQ_PRTY_STS 0x170184
+/* [RC 2] Parity register #0 read clear */
+#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
+/* [R 13] Current value of the DQ FIFO fill level according to following
+ * pointer. The range is 0 - 256 FIFO rows; where each row stands for the
+ * doorbell.
+ */
+#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
+/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
+ * equal to full threshold; reset on full clear.
+ */
+#define DORQ_REG_DQ_FULL_ST 0x1700c0
+#define DORQ_REG_MAX_RVFID_SIZE 0x1701ec
+#define DORQ_REG_MODE_ACT 0x170008
+/* [RW 5] The normal mode CID extraction offset. */
+#define DORQ_REG_NORM_CID_OFST 0x17002c
+#define DORQ_REG_PF_USAGE_CNT 0x1701d0
+/* [R 4] Current value of response A counter credit. Initial credit is
+ * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+ * register.
+ */
+#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
+/* [R 4] Current value of response B counter credit. Initial credit is
+ * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+ * register.
+ */
+#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
+#define DORQ_REG_VF_NORM_CID_BASE 0x1701a0
+#define DORQ_REG_VF_NORM_CID_OFST 0x1701f4
+#define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4
+#define DORQ_REG_VF_NORM_VF_BASE 0x1701a8
+/* [RW 10] VF type validation mask value */
+#define DORQ_REG_VF_TYPE_MASK_0 0x170218
+/* [RW 17] VF type validation Min MCID value */
+#define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8
+/* [RW 17] VF type validation Max MCID value */
+#define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298
+/* [RW 10] VF type validation comp value */
+#define DORQ_REG_VF_TYPE_VALUE_0 0x170258
+#define DORQ_REG_VF_USAGE_CNT 0x170320
+#define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340
+#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1 << 4)
+#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1 << 0)
+#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1 << 3)
+#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1 << 7)
+#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1 << 2)
+#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1 << 1)
+#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1 << 0)
+#define HC_REG_AGG_INT_0 0x108050
+#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
+#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
+#define HC_REG_COMMAND_REG 0x108180
+#define HC_REG_CONFIG_0 0x108000
+#define HC_REG_CONFIG_1 0x108004
+/* [RW 7] Interrupt mask register #0 read/write */
+#define HC_REG_HC_INT_MASK 0x108090
+/* [R 7] Interrupt register #0 read */
+#define HC_REG_HC_INT_STS 0x108084
+/* [RC 7] Interrupt register #0 read clear */
+#define HC_REG_HC_INT_STS_CLR 0x108088
+/* [RW 3] Parity mask register #0 read/write */
+#define HC_REG_HC_PRTY_MASK 0x1080a0
+/* [R 3] Parity register #0 read */
+#define HC_REG_HC_PRTY_STS 0x108094
+/* [RC 3] Parity register #0 read clear */
+#define HC_REG_HC_PRTY_STS_CLR 0x108098
+#define HC_REG_INT_MASK 0x108108
+#define HC_REG_LEADING_EDGE_0 0x108040
+#define HC_REG_MAIN_MEMORY 0x108800
+#define HC_REG_MAIN_MEMORY_SIZE 152
+#define HC_REG_TRAILING_EDGE_0 0x108044
+#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1 << 1)
+#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1 << 0)
+#define IGU_REG_ATTENTION_ACK_BITS 0x130108
+/* [R 4] Debug: attn_fsm */
+#define IGU_REG_ATTN_FSM 0x130054
+#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
+#define IGU_REG_ATTN_MSG_ADDR_L 0x130120
+/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
+ * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
+ * write done didn't receive.
+ */
+#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
+#define IGU_REG_BLOCK_CONFIGURATION 0x130000
+#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
+#define IGU_REG_COMMAND_REG_CTRL 0x13012c
+/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
+ * is clear. The bits in this registers are set and clear via the producer
+ * command. Data valid only in addresses 0-4. all the rest are zero.
+ */
+#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
+/* [R 5] Debug: ctrl_fsm */
+#define IGU_REG_CTRL_FSM 0x130064
+/* [R 1] data available for error memory. If this bit is clear do not red
+ * from error_handling_memory.
+ */
+#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
+/* [RW 11] Interrupt mask register #0 read/write */
+#define IGU_REG_IGU_INT_MASK 0x130098
+/* [R 11] Interrupt register #0 read */
+#define IGU_REG_IGU_INT_STS 0x13008c
+/* [RC 11] Interrupt register #0 read clear */
+#define IGU_REG_IGU_INT_STS_CLR 0x130090
+/* [RW 11] Parity mask register #0 read/write */
+#define IGU_REG_IGU_PRTY_MASK 0x1300a8
+/* [R 11] Parity register #0 read */
+#define IGU_REG_IGU_PRTY_STS 0x13009c
+/* [RC 11] Parity register #0 read clear */
+#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
+/* [R 4] Debug: int_handle_fsm */
+#define IGU_REG_INT_HANDLE_FSM 0x130050
+#define IGU_REG_LEADING_EDGE_LATCH 0x130134
+/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
+ * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
+ * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number);
+ */
+#define IGU_REG_MAPPING_MEMORY 0x131000
+#define IGU_REG_MAPPING_MEMORY_SIZE 136
+#define IGU_REG_PBA_STATUS_LSB 0x130138
+#define IGU_REG_PBA_STATUS_MSB 0x13013c
+#define IGU_REG_PCI_PF_MSIX_EN 0x130144
+#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
+#define IGU_REG_PCI_PF_MSI_EN 0x130140
+/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
+ * pending; 1 = pending. Pendings means interrupt was asserted; and write
+ * done was not received. Data valid only in addresses 0-4. all the rest are
+ * zero.
+ */
+#define IGU_REG_PENDING_BITS_STATUS 0x130300
+#define IGU_REG_PF_CONFIGURATION 0x130154
+/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
+ * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
+ * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
+ * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
+ * - In backward compatible mode; for non default SB; each even line in the
+ * memory holds the U producer and each odd line hold the C producer. The
+ * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
+ * last 20 producers are for the DSB for each PF. each PF has five segments
+ * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
+ * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods;
+ */
+#define IGU_REG_PROD_CONS_MEMORY 0x132000
+/* [R 3] Debug: pxp_arb_fsm */
+#define IGU_REG_PXP_ARB_FSM 0x130068
+/* [RW 6] Write one for each bit will reset the appropriate memory. When the
+ * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
+ * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
+ * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics;
+ */
+#define IGU_REG_RESET_MEMORIES 0x130158
+/* [R 4] Debug: sb_ctrl_fsm */
+#define IGU_REG_SB_CTRL_FSM 0x13004c
+#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
+#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
+#define IGU_REG_SB_MASK_LSB 0x130164
+#define IGU_REG_SB_MASK_MSB 0x130168
+/* [RW 16] Number of command that were dropped without causing an interrupt
+ * due to: read access for WO BAR address; or write access for RO BAR
+ * address or any access for reserved address or PCI function error is set
+ * and address is not MSIX; PBA or cleanup
+ */
+#define IGU_REG_SILENT_DROP 0x13016c
+/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
+ * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
+ * PF; 68-71 number of ATTN messages per PF
+ */
+#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
+#define IGU_REG_TRAILING_EDGE_LATCH 0x130104
+#define IGU_REG_VF_CONFIGURATION 0x130170
+/* [WB_R 32] Each bit represent write done pending bits status for that SB
+ * (MSI/MSIX message was sent and write done was not received yet). 0 =
+ * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero.
+ */
+#define IGU_REG_WRITE_DONE_PENDING 0x130480
+#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
+#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
+#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
+#define MCP_REG_MCPR_GP_INPUTS 0x800c0
+#define MCP_REG_MCPR_GP_OENABLE 0x800c8
+#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
+#define MCP_REG_MCPR_IMC_COMMAND 0x85900
+#define MCP_REG_MCPR_IMC_DATAREG0 0x85920
+#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
+#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
+#define MCP_REG_MCPR_NVM_ADDR 0x8640c
+#define MCP_REG_MCPR_NVM_CFG4 0x8642c
+#define MCP_REG_MCPR_NVM_COMMAND 0x86400
+#define MCP_REG_MCPR_NVM_READ 0x86410
+#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
+#define MCP_REG_MCPR_NVM_WRITE 0x86408
+#define MCP_REG_MCPR_SCRATCH 0xa0000
+#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1 << 1)
+#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1 << 0)
+/* [R 32] read first 32 bit after inversion of function 0. mapped as
+ * follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
+ * [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
+ * GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
+ * glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
+ * [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
+ * MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
+ * Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
+ * interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
+ * error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
+ * interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30]
+ * PBClient Parity error; [31] PBClient Hw interrupt;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
+/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
+ * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+ * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+ * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+ * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+ * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+ * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+ * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+ * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+ * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+ * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+ * Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31]
+ * PBClient Hw interrupt;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
+/* [R 32] read second 32 bit after inversion of function 0. mapped as
+ * follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error;
+ * [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
+ * [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
+ * XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+ * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+ * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+ * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+ * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+ * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+ * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+ * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
+/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
+ * PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw
+ * interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
+ * Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
+ * interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+ * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+ * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+ * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+ * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+ * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+ * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+ * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
+/* [R 32] read third 32 bit after inversion of function 0. mapped as
+ * follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
+ * error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
+ * PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+ * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+ * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+ * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+ * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+ * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+ * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+ * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+ * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+ * attn1;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
+/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
+ * CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
+ * Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
+ * Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
+ * error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
+ * interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
+ * MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
+ * Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
+ * timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
+ * func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
+ * func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
+ * timers attn_4 func1; [30] General attn0; [31] General attn1;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
+/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
+ * follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
+/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
+ * General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
+ * [4] General attn6; [5] General attn7; [6] General attn8; [7] General
+ * attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
+ * General attn13; [12] General attn14; [13] General attn15; [14] General
+ * attn16; [15] General attn17; [16] General attn18; [17] General attn19;
+ * [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
+ * RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
+ * RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
+ * attention; [27] GRC Latched reserved access attention; [28] MCP Latched
+ * rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
+ * ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
+/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
+ * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
+/* [W 14] write to this register results with the clear of the latched
+ * signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
+ * d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
+ * latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
+ * GRC Latched reserved access attention; one in d7 clears Latched
+ * rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
+ * Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
+ * ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
+ * pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
+ * from this register return zero
+ */
+#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
+/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+ * 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw
+ * interrupt;
+ */
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
+/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
+ * 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw
+ * interrupt;
+ */
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
+/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
+/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
+/* [RW 32] fourth 32b for enabling the output for close the gate nig. Mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
+#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
+/* [RW 32] fourth 32b for enabling the output for close the gate pxp. Mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
+#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
+/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
+ * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved;
+ */
+#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
+/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
+ * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved;
+ */
+#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
+/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
+ * 128 bit vector
+ */
+#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
+#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
+#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
+#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
+#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
+#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
+#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
+#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
+#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
+#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
+#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
+#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
+#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
+#define MISC_REG_AEU_GENERAL_MASK 0xa61c
+/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
+ * [9:8] = reserved. 0 = mask; 1 = unmask
+ */
+#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
+#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
+/* [RW 1] If set a system kill occurred. Reset on POR reset. */
+#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
+/* [RW 32] Represent the status of the input vector to the AEU when a system
+ * kill occurred. The register is reset in por reset. Mapped as follows: [0]
+ * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+ * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+ * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+ * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+ * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+ * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+ * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+ * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+ * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+ * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+ * Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31]
+ * PBClient Hw interrupt. Reset on POR reset.
+ */
+#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
+#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
+#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
+#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
+/* [R 32] This field indicates the type of the device. '0' - 2 Ports; '1' -
+ * 1 Port. Global register.
+ */
+#define MISC_REG_BOND_ID 0xa400
+/* [R 16] These bits indicate the part number for the chip. Global register. */
+#define MISC_REG_CHIP_NUM 0xa408
+/* [R 4] These bits indicate the base revision of the chip. This value
+ * starts at 0x0 for the A0 tape-out and increments by one for each
+ * all-layer tape-out. Global register.
+ */
+#define MISC_REG_CHIP_REV 0xa40c
+/* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
+ * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
+ * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1].
+ */
+#define MISC_REG_CHIP_TYPE 0xac60
+#define MISC_REG_CHIP_TYPE_57811_MASK (1 << 1)
+#define MISC_REG_CPMU_LP_DR_ENABLE 0xa858
+/* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
+ * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
+ * 25MHz. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c
+/* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
+ * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0
+/* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
+ * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
+ * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
+ * the FW command that all Queues are empty is disabled. When 0 indicates
+ * that the FW command that all Queues are empty is enabled. [2] - FW Early
+ * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early
+ * Exit command is disabled. When 0 indicates that the FW Early Exit command
+ * is enabled. This bit applicable only in the EXIT Events Mask registers.
+ * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
+ * is disabled. When 0 indicates that the PBF Request indication is enabled.
+ * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
+ * Request indication is disabled. When 0 indicates that the Tx Other Than
+ * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
+ * indicates that the RX EEE LPI Status indication is disabled. When 0
+ * indicates that the RX EEE LPI Status indication is enabled. In the EXIT
+ * Events Masks registers; this bit masks the falling edge detect of the LPI
+ * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
+ * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
+ * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
+ * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
+ * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
+ * IDLE indication is disabled. When 0 indicates that the QM IDLE indication
+ * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
+ * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
+ * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
+ * Status Mask. When 1 indicates that the L1 Status indication from the PCIE
+ * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
+ * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this
+ * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
+ * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
+ * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
+ * indicates that the P0 EEE LPI REQ indication is disabled. When =0
+ * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
+ * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
+ * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
+ * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
+ * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
+ * REQ indication is disabled. When =0 indicates that the L1 indication is
+ * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
+ * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx
+ * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
+ * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
+ * bit is applicable only in the EXIT Events Masks registers. [17] - L1
+ * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling
+ * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
+ * When =0 indicates that the L1 Status Falling Edge Detect indication from
+ * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
+ * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880
+/* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
+ * that the Vmain SM end state is disabled. When 0 indicates that the Vmain
+ * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
+ * that the FW command that all Queues are empty is disabled. When 0
+ * indicates that the FW command that all Queues are empty is enabled. [2] -
+ * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW
+ * Early Exit command is disabled. When 0 indicates that the FW Early Exit
+ * command is enabled. This bit applicable only in the EXIT Events Mask
+ * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
+ * indication is disabled. When 0 indicates that the PBF Request indication
+ * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
+ * Than PBF Request indication is disabled. When 0 indicates that the Tx
+ * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
+ * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.
+ * When 0 indicates that the RX LPI Status indication is enabled. In the
+ * EXIT Events Masks registers; this bit masks the falling edge detect of
+ * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
+ * indicates that the Tx Pause indication is disabled. When 0 indicates that
+ * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
+ * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
+ * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
+ * indicates that the QM IDLE indication is disabled. When 0 indicates that
+ * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]
+ * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
+ * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
+ * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
+ * Status indication from the PCIE CORE is disabled. When 0 indicates that
+ * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the
+ * EXIT Events Masks registers; this bit masks the falling edge detect of
+ * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
+ * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
+ * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
+ * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
+ * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
+ * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
+ * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
+ * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
+ * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
+ * indicates that the L1 REQ indication is disabled. When =0 indicates that
+ * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
+ * When =1 indicates that the RX EEE LPI Status Falling Edge Detect
+ * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
+ * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE
+ * LPI is on - off). This bit is applicable only in the EXIT Events Masks
+ * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
+ * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled
+ * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
+ * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
+ * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.
+ * Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888
+/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
+ * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
+ * register. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
+/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
+ * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
+ * register. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
+/* [RW 32] The following driver registers(1...16) represent 16 drivers and
+ * 32 clients. Each client can be controlled by one driver only. One in each
+ * bit represent that this driver control the appropriate client (Ex: bit 5
+ * is set means this driver control client number 5). addr1 = set; addr0 =
+ * clear; read from both addresses will give the same result = status. write
+ * to address 1 will set a request to control all the clients that their
+ * appropriate bit (in the write command) is set. if the client is free (the
+ * appropriate bit in all the other drivers is clear) one will be written to
+ * that driver register; if the client isn't free the bit will remain zero.
+ * if the appropriate bit is set (the driver request to gain control on a
+ * client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
+ * interrupt will be asserted). write to address 0 will set a request to
+ * free all the clients that their appropriate bit (in the write command) is
+ * set. if the appropriate bit is clear (the driver request to free a client
+ * it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
+ * be asserted).
+ */
+#define MISC_REG_DRIVER_CONTROL_1 0xa510
+#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
+/* [R 1] Status of four port mode path swap input pin. */
+#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
+/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
+ * the path_swap output is equal to 4 port mode path swap input pin; if it
+ * is 1 - the path_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the path_swap output. Reset on Hard reset.
+ */
+#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
+/* [R 1] Status of 4 port mode port swap input pin. */
+#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
+/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
+ * the port_swap output is equal to 4 port mode port swap input pin; if it
+ * is 1 - the port_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the port_swap output. Reset on Hard reset.
+ */
+#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
+/* [RW 32] Debug only: spare RW register reset by core reset. Global
+ * register. Reset on core reset.
+ */
+#define MISC_REG_GENERIC_CR_0 0xa460
+#define MISC_REG_GENERIC_CR_1 0xa464
+/* [RW 32] Debug only: spare RW register reset by por reset. Global
+ * register. Reset on POR reset.
+ */
+#define MISC_REG_GENERIC_POR_1 0xa474
+/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
+ * use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
+ * can not be configured as an output. Each output has its output enable in
+ * the MCP register space; but this bit needs to be set to make use of that.
+ * Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
+ * set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
+ * When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
+ * the i/o to an output and will drive the TimeSync output. Bit[31:7]:
+ * spare. Global register. Reset by hard reset.
+ */
+#define MISC_REG_GEN_PURP_HWG 0xa9a0
+/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
+ * these bits is written as a '1'; the corresponding GPIO bit will turn off
+ * it's drivers and become an input. This is the reset state of all GPIO
+ * pins. The read value of these bits will be a '1' if that last command
+ * (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
+ * [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
+ * as a '1'; the corresponding GPIO bit will drive low. The read value of
+ * these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
+ * this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
+ * SET When any of these bits is written as a '1'; the corresponding GPIO
+ * bit will drive high (if it has that capability). The read value of these
+ * bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
+ * bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
+ * RO; These bits indicate the read value of each of the eight GPIO pins.
+ * This is the result value of the pin; not the drive value. Writing these
+ * bits will have not effect. Global register.
+ */
+#define MISC_REG_GPIO 0xa490
+/* [RW 8] These bits enable the GPIO_INTs to signals event to the
+ * IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
+ * p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
+ * [7] p1_gpio_3; Global register.
+ */
+#define MISC_REG_GPIO_EVENT_EN 0xa2bc
+/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
+ * '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
+ * This will acknowledge an interrupt on the falling edge of corresponding
+ * GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
+ * Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
+ * register. This will acknowledge an interrupt on the rising edge of
+ * corresponding GPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
+ * OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
+ * value. When the ~INT_STATE bit is set; this bit indicates the OLD value
+ * of the pin such that if ~INT_STATE is set and this bit is '0'; then the
+ * interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
+ * is '1'; then the interrupt is due to a high to low edge (reset value 0).
+ * [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
+ * current GPIO interrupt state for each GPIO pin. This bit is cleared when
+ * the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
+ * set when the GPIO input does not match the current value in #OLD_VALUE
+ * (reset value 0). Global register.
+ */
+#define MISC_REG_GPIO_INT 0xa494
+/* [R 28] this field hold the last information that caused reserved
+ * attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ * [27:24] the master that caused the attention - according to the following
+ * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+ * dbu; 8 = dmae
+ */
+#define MISC_REG_GRC_RSV_ATTN 0xa3c0
+/* [R 28] this field hold the last information that caused timeout
+ * attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ * [27:24] the master that caused the attention - according to the following
+ * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+ * dbu; 8 = dmae
+ */
+#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
+/* [R 10] Holds the last FID that caused timeout attention. Need to be used
+ * in conjunction with ~misc_registers_timeout_attn; where 3 bits of
+ * function (3 lsb) are also represented. Bit[2:0] - PFID; bit[3] - VFID
+ * valid; bit[9:4] - VFID. Global register.
+ */
+#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa714
+/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
+ * reset.
+ */
+#define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
+/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
+#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
+/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
+ * reset.
+ */
+#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
+/* [RW 8] Interrupt mask register #0 read/write */
+#define MISC_REG_MISC_INT_MASK 0xa388
+/* [R 8] Interrupt register #0 read */
+#define MISC_REG_MISC_INT_STS 0xa37c
+/* [RC 8] Interrupt register #0 read clear */
+#define MISC_REG_MISC_INT_STS_CLR 0xa380
+/* [RW 1] Parity mask register #0 read/write */
+#define MISC_REG_MISC_PRTY_MASK 0xa398
+/* [R 1] Parity register #0 read */
+#define MISC_REG_MISC_PRTY_STS 0xa38c
+/* [RC 1] Parity register #0 read clear */
+#define MISC_REG_MISC_PRTY_STS_CLR 0xa390
+/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
+ * assertion. Global register.
+ */
+#define MISC_REG_PCIE_HOT_RESET 0xa618
+/* [R 1] Status of 4 port mode enable input pin. */
+#define MISC_REG_PORT4MODE_EN 0xa750
+/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
+ * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
+ * the port4mode_en output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the port4mode_en output. Reset on Hard reset.
+ */
+#define MISC_REG_PORT4MODE_EN_OVWR 0xa720
+/* [RW 32] reset reg#1; rite/read one = the specific block is out of reset;
+ * write/read zero = the specific block is in reset; addr 0-wr- the write
+ * value will be written to the register; addr 1-set - one will be written
+ * to all the bits that have the value of one in the data written (bits that
+ * have the value of zero will not be change) ; addr 2-clear - zero will be
+ * written to all the bits that have the value of one in the data written
+ * (bits that have the value of zero will not be change); addr 3-ignore;
+ * read ignore from all addr except addr 00; inside order of the bits is:
+ * [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5]
+ * rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10]
+ * rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15]
+ * rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20]
+ * rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25]
+ * rst_cfc; [26] rst_pxp_hst; [27] rst_pxpv (global register); [28]
+ * rst_rbcp; [29] rst_hc; [30] rst_dmae; [31] rst_semi_rtc;
+ */
+#define MISC_REG_RESET_REG_1 0xa580
+#define MISC_REG_RESET_REG_2 0xa590
+/* [RW 22] 22 bit GRC address where the scratch-pad of the MCP that is
+ * shared with the driver resides
+ */
+#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
+/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
+ * the corresponding SPIO bit will turn off it's drivers and become an
+ * input. This is the reset state of all SPIO pins. The read value of these
+ * bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
+ * bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
+ * is written as a '1'; the corresponding SPIO bit will drive low. The read
+ * value of these bits will be a '1' if that last command (#SET; #CLR; or
+ * #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
+ * these bits is written as a '1'; the corresponding SPIO bit will drive
+ * high (if it has that capability). The read value of these bits will be a
+ * '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
+ * (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
+ * each of the eight SPIO pins. This is the result value of the pin; not the
+ * drive value. Writing these bits will have not effect. Each 8 bits field
+ * is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
+ * from VAUX. (This is an output pin only; the FLOAT field is not applicable
+ * for this pin); [1] VAUX Disable; when pulsed low; disables supply form
+ * VAUX. (This is an output pin only; FLOAT field is not applicable for this
+ * pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
+ * select VAUX supply. (This is an output pin only; it is not controlled by
+ * the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
+ * field is not applicable for this pin; only the VALUE fields is relevant -
+ * it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
+ * Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
+ * device ID select; read by UMP firmware. Global register.
+ */
+#define MISC_REG_SPIO 0xa4fc
+/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
+ * according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
+ * [7:6] reserved. Global register.
+ */
+#define MISC_REG_SPIO_EVENT_EN 0xa2b8
+/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
+ * corresponding bit in the #OLD_VALUE register. This will acknowledge an
+ * interrupt on the falling edge of corresponding SPIO input (reset value
+ * 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
+ * in the #OLD_VALUE register. This will acknowledge an interrupt on the
+ * rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
+ * RO; These bits indicate the old value of the SPIO input value. When the
+ * ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
+ * that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
+ * to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
+ * interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
+ * RO; These bits indicate the current SPIO interrupt state for each SPIO
+ * pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
+ * command bit is written. This bit is set when the SPIO input does not
+ * match the current value in #OLD_VALUE (reset value 0). Global register.
+ */
+#define MISC_REG_SPIO_INT 0xa500
+/* [R 1] Status of two port mode path swap input pin. */
+#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
+/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
+ * path_swap output is equal to 2 port mode path swap input pin; if it is 1
+ * - the path_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the path_swap output. Reset on Hard reset.
+ */
+#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
+/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
+ * loaded; 0-prepare; -unprepare. Global register. Reset on hard reset.
+ */
+#define MISC_REG_UNPREPARED 0xa424
+/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
+ * not it is the recipient of the message on the MDIO interface. The value
+ * is compared to the value on ctrl_md_devad. Drives output
+ * misc_xgxs0_phy_addr. Global register.
+ */
+#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
+/* [RW 10] reset reg#3; rite/read one = the specific block is out of reset;
+ * write/read zero = the specific block is in reset; addr 0-wr- the write
+ * value will be written to the register; addr 1-set - one will be written
+ * to all the bits that have the value of one in the data written (bits that
+ * have the value of zero will not be change) ; addr 2-clear - zero will be
+ * written to all the bits that have the value of one in the data written
+ * (bits that have the value of zero will not be change); addr 3-ignore;
+ * read ignore from all addr except addr 00. [0]: rstb_hw: Active low reset
+ * which when asserted drives entire WC into the reset state. All flops
+ * which within WC are driven into an initial state; as well as the analog
+ * core. Output clocks txck_out; rxck0_10g; and clk_25 will be driven to 0
+ * upon its assertion. [1]: iddq. Enables iddq testing where the supply
+ * current (Idd) is measured in the quiescent state. [2]: pwrdwn: Active
+ * high control which forces the analog core of the WC into power-down mode;
+ * and forces digital logic of the WC into reset. Output clock (refclk)
+ * remains active. [3]: pwrdwn_sd: Power down signal detect. [4]:
+ * txd10g_fifo_rstb: Transmit 10Gbps FIFO reset; active low. Used to reset
+ * the transmit FIFO used in xlgmii operation. [8:5]: txd1g_fifo_rstb:
+ * Transmit 1Gbps FIFO reset; active low. Used to reset the per-lane
+ * transmit FIFOs used in the mii/gmii operation. [9]:
+ * txd10g_fifo_rstb_dxgxs1: Transmit 10Gbps DXGXS FIFO reset; active low.
+ * Used to reset the transmit FIFO used in the DXGXS logic in xlgmii
+ * operation. Global register.
+ */
+#define MISC_REG_WC0_RESET 0xac30
+/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
+ * side. This should be less than or equal to phy_port_mode; if some of the
+ * ports are not used. This enables reduction of frequency on the core side.
+ * This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
+ * Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
+ * input for the XMAC_MP core; and should be changed only while reset is
+ * held low. Reset on Hard reset.
+ */
+#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
+/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
+ * Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
+ * 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
+ * XMAC_MP core; and should be changed only while reset is held low. Reset
+ * on Hard reset.
+ */
+#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
+/* [RW 1] Interrupt mask register #0 read/write */
+#define MSTAT_REG_MSTAT_INT_MASK 0x7fc
+/* [R 1] Interrupt register #0 read */
+#define MSTAT_REG_MSTAT_INT_STS 0x7f0
+/* [RC 1] Interrupt register #0 read clear */
+#define MSTAT_REG_MSTAT_INT_STS_CLR 0x7f4
+/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
+ * Reads from this register will clear bits 31:0.
+ */
+#define MSTAT_REG_RX_STAT_GR64_LO 0x200
+/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
+ * 31:0. Reads from this register will clear bits 31:0.
+ */
+#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
+#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1 << 0)
+#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1 << 0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1 << 0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1 << 9)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1 << 15)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf << 18)
+/* [R 1] Input enable for RX_BMAC0 IF */
+#define NIG_REG_BMAC0_IN_EN 0x100ac
+/* [R 1] output enable for TX_BMAC0 IF */
+#define NIG_REG_BMAC0_OUT_EN 0x100e0
+/* [R 1] output enable for TX BMAC pause port 0 IF */
+#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
+/* [R 1] output enable for RX_BMAC0_REGS IF */
+#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
+/* [RW 1] output enable for RX BRB1 port0 IF */
+#define NIG_REG_BRB0_OUT_EN 0x100f8
+/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
+#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
+/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
+#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
+/* [WB_W 90] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
+ * error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
+ * 72:73]-vnic_num; 89:74]-sideband_info
+ */
+#define NIG_REG_DEBUG_PACKET_LB 0x10800
+/* [R 1] FIFO empty in DEBUG_FIFO in NIG_TX_DBG */
+#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418
+/* [R 1] FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT0 */
+#define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420
+/* [R 1] FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT1 */
+#define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862c
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638
+/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
+ * packets from PBFare not forwarded to the MAC and just deleted from FIFO.
+ * First packet may be deleted from the middle. And last packet will be
+ * always deleted till the end.
+ */
+#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
+/* [R 1] Output enable to EMAC0 */
+#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
+/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
+ * to emac for port0; other way to bmac for port0
+ */
+#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
+/* [R 1] FIFO empty in MNG_FIFO in NIG_TX_PORT0 */
+#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460
+/* [R 1] FIFO empty in MNG_FIFO in NIG_TX_PORT1 */
+#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474
+/* [RW 1] Input enable for TX UMP management packet port0 IF */
+#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
+/* [R 1] Input enable for RX_EMAC0 IF */
+#define NIG_REG_EMAC0_IN_EN 0x100a4
+/* [R 1] output enable for TX EMAC pause port 0 IF */
+#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
+/* [R 1] status from emac0. This bit is set when MDINT from either the
+ * EXT_MDINT pin or from the Copper PHY is driven low. This condition must
+ * be cleared in the attached PHY device that is driving the MINT pin.
+ */
+#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
+/* [R 48] This address space contains BMAC0 registers. The BMAC registers
+ * are described in appendix A. In order to access the BMAC0 registers; the
+ * base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
+ * added to each BMAC register offset
+ */
+#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
+/* [R 48] This address space contains BMAC1 registers. The BMAC registers
+ * are described in appendix A. In order to access the BMAC0 registers; the
+ * base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
+ * added to each BMAC register offset
+ */
+#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
+/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
+/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
+ * packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16]
+ */
+#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
+/* [R 1] FIFO empty in EOP descriptor FIFO of port 0 in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ec
+/* [R 1] FIFO empty in EOP descriptor FIFO of port 1 in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8
+/* [R 1] FIFO empty in PBF_DELAY_lb_FIFO in NIG_RX_lb */
+#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508
+/* [R 1] FIFO empty in dscr_fifo in NIG_RX_RMP block */
+#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530
+/* [R 1] FIFO empty in dscr_fifo in NIG_RX_RMP block */
+#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538
+/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
+ * logic for interrupts must be used. Enable per bit of interrupt of
+ * ~latch_status.latch_status
+ */
+#define NIG_REG_LATCH_BC_0 0x16210
+/* [RW 27] Latch for each interrupt from Unicore.b[0]
+ * status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
+ * b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
+ * b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
+ * b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
+ * b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
+ * b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
+ * b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
+ * b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
+ * b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
+ * b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
+ * b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
+ * b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs
+ */
+#define NIG_REG_LATCH_STATUS_0 0x18000
+/* [RW 1] led 10g for port 0 */
+#define NIG_REG_LED_10G_P0 0x10320
+/* [RW 1] Port0: This bit is set to enable the use of the
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
+ * defined below. If this bit is cleared; then the blink rate will be about
+ * 8Hz.
+ */
+#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
+/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
+ * Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
+ * is reset to 0x080; giving a default blink period of approximately 8Hz.
+ */
+#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
+/* [RW 1] Port0: If set along with the
+ * s_led_control_override_traffic_p0.led_control_override_traffic_p0
+ * bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
+ * bit; the Traffic LED will blink with the blink rate specified in
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+ * ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+ * fields.
+ */
+#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
+/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
+ * Traffic LED will then be controlled via bit ~nig_registers_
+ * led_control_traffic_p0.led_control_traffic_p0 and bit
+ * ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0
+ */
+#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
+/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
+ * turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
+ * set; the LED will blink with blink rate specified in
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+ * ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+ * fields.
+ */
+#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
+/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
+ * 9-11PHY7; 12 MAC4; 13-15 PHY10;
+ */
+#define NIG_REG_LED_MODE_P0 0x102f0
+/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
+ * tsdm enable; b2- usdm enable
+ */
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
+/* [RW 1] SAFC enable for port0. This register may get 1 only when
+ * ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
+ * port
+ */
+#define NIG_REG_LLFC_ENABLE_0 0x16208
+#define NIG_REG_LLFC_ENABLE_1 0x1620c
+/* [RW 16] classes are high-priority for port0 */
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
+/* [RW 16] classes are low-priority for port0 */
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
+/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
+#define NIG_REG_LLFC_OUT_EN_0 0x160c8
+#define NIG_REG_LLFC_OUT_EN_1 0x160cc
+#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
+#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
+#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
+#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
+/* [RW 2] Determine the classification participants. 0: no classification.1:
+ * classification upon VLAN id. 2: classification upon MAC address. 3:
+ * classification upon both VLAN id & MAC addr.
+ */
+#define NIG_REG_LLH0_CLS_TYPE 0x16080
+#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
+#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
+/* [RW 16] destination TCP address 1. The LLH will look for this address in
+ * all incoming packets.
+ */
+#define NIG_REG_LLH0_DEST_TCP_0 0x10220
+/* [RW 16] destination UDP address 1 The LLH will look for this address in
+ * all incoming packets.
+ */
+#define NIG_REG_LLH0_DEST_UDP_0 0x10214
+/* [R 1] FIFO empty in LLH port0 */
+#define NIG_REG_LLH0_FIFO_EMPTY 0x10548
+#define NIG_REG_LLH0_FUNC_EN 0x160fc
+#define NIG_REG_LLH0_FUNC_MEM 0x16180
+#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
+#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
+/* [RW 1] Determine the IP version to look for in
+ * ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4
+ */
+#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
+/* [RW 1] t bit for llh0 */
+#define NIG_REG_LLH0_T_BIT 0x10074
+/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
+#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
+#define NIG_REG_LLH0_XCM_MASK 0x10130
+#define NIG_REG_LLH1_BRB1_DRV_MASK_MF 0x1604c
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
+/* [RW 2] Determine the classification participants. 0: no classification.1:
+ * classification upon VLAN id. 2: classification upon MAC address. 3:
+ * classification upon both VLAN id & MAC addr.
+ */
+#define NIG_REG_LLH1_CLS_TYPE 0x16084
+/* [R 1] FIFO empty in LLH port1 */
+#define NIG_REG_LLH1_FIFO_EMPTY 0x10558
+#define NIG_REG_LLH1_FUNC_EN 0x16104
+#define NIG_REG_LLH1_FUNC_MEM 0x161c0
+#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
+#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
+/* [RW 1] When this bit is set; the LLH will classify the packet before
+ * sending it to the BRB or calculating WoL on it. This bit controls port 1
+ * only. The legacy llh_multi_function_mode bit controls port 0.
+ */
+#define NIG_REG_LLH1_MF_MODE 0x18614
+#define NIG_REG_LLH1_XCM_MASK 0x10134
+/* [RW 1] When this bit is set; the LLH will expect all packets to be with
+ * outer VLAN. This is not applicable to E2.
+ */
+#define NIG_REG_LLH_E1HOV_MODE 0x160d8
+/* [RW 16] Outer VLAN type identifier for multi-function mode. In non
+ * multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
+ */
+#define NIG_REG_LLH_E1HOV_TYPE_1 0x16028
+/* [RW 1] When this bit is set; the LLH will classify the packet before
+ * sending it to the BRB or calculating WoL on it. This bit is applicable to
+ * both ports 0 and 1 for E2. This bit only controls port 0 in E3.
+ */
+#define NIG_REG_LLH_MF_MODE 0x16024
+#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
+#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
+/* [R 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
+#define NIG_REG_NIG_EMAC0_EN 0x1003c
+/* [R 1] Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0
+ * to strip the CRC from the ingress packets.
+ */
+#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
+/* [RW 32] Interrupt mask register #0 read/write */
+#define NIG_REG_NIG_INT_MASK_0 0x103bc
+#define NIG_REG_NIG_INT_MASK_1 0x103cc
+/* [R 32] Interrupt register #0 read */
+#define NIG_REG_NIG_INT_STS_0 0x103b0
+#define NIG_REG_NIG_INT_STS_1 0x103c0
+/* [RC 32] Interrupt register #0 read clear */
+#define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
+#define NIG_REG_NIG_INT_STS_CLR_1 0x103c4
+/* [R 32] Legacy E1 and E1H location for parity error mask register. */
+#define NIG_REG_NIG_PRTY_MASK 0x103dc
+/* [RW 32] Parity mask register #0 read/write */
+#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
+#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
+/* [R 32] Legacy E1 and E1H location for parity error status register. */
+#define NIG_REG_NIG_PRTY_STS 0x103d0
+/* [R 32] Parity register #0 read */
+#define NIG_REG_NIG_PRTY_STS_0 0x183bc
+#define NIG_REG_NIG_PRTY_STS_1 0x183cc
+/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
+#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
+/* [RC 32] Parity register #0 read clear */
+#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
+#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
+/* [R 1] Indication that HBUF descriptor FIFO is empty. */
+#define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header.
+ */
+#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
+/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
+ * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
+ * disabled when this bit is set.
+ */
+#define NIG_REG_P0_HWPFC_ENABLE 0x18078
+#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
+/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Writing a 1 to bit 16
+ * will clear the buffer.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
+ * packets only and require that the packet is IPv4 for the rules to match.
+ * Note that rules 4-7 are for IPv6 packets only and require that the packet
+ * is IPv6 for the rules to match.
+ */
+#define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4
+/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
+#define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac
+/* [RW 1] Input enable for RX MAC interface. */
+#define NIG_REG_P0_MAC_IN_EN 0x185ac
+/* [RW 1] Output enable for TX MAC interface */
+#define NIG_REG_P0_MAC_OUT_EN 0x185b0
+/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
+#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
+/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
+ * future expansion) each priority is to be mapped to. Bits 3:0 specify the
+ * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
+ * priority field is extracted from the outer-most VLAN in receive packet.
+ * Only COS 0 and COS 1 are supported in E2.
+ */
+#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
+/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
+ * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
+ * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
+ * frame format in timesync event detection on RX side. Bit 3 enables
+ * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
+ * detection on TX side. Bit 5 enables V2 frame format in timesync event
+ * detection on TX side. Note that for HW to detect PTP packet and extract
+ * data from the packet, at least one of the version bits of that traffic
+ * direction has to be enabled.
+ */
+#define NIG_REG_P0_PTP_EN 0x18788
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
+ * priority is mapped to COS 0 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
+ * priority is mapped to COS 1 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
+ * priority is mapped to COS 2 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
+ * priority is mapped to COS 3 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
+ * priority is mapped to COS 4 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
+ * priority is mapped to COS 5 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
+/* [R 1] RX FIFO for receiving data from MAC is empty. */
+#define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570
+/* [R 1] TLLH FIFO is empty. */
+#define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308
+/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Bit 17 indicates that
+ * the sequence ID is valid and it is waiting for the TX timestamp value.
+ * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
+ * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules.
+ */
+#define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4
+/* [R 15] Specify which of the credit registers the client is to be mapped
+ * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
+ * clients that are not subject to WFQ credit blocking - their
+ * specifications here are not used.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
+/* [RW 32] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
+/* [RW 4] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
+/* [RW 9] Specify whether the client competes directly in the strict
+ * priority arbiter. The bits are mapped according to client ID (client IDs
+ * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
+ * Default value is set to enable strict priorities for all clients.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
+/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
+ * bits are mapped according to client ID (client IDs are defined in
+ * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
+ * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
+ * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
+ * 0 for not using WFQ credit blocking.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
+/* [RW 32] Specify the upper bound that credit register 0 is allowed to
+ * reach.
+ */
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
+/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
+ * when it is time to increment.
+ */
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
+/* [RW 12] Specify the number of strict priority arbitration slots between
+ * two round-robin arbitration slots to avoid starvation. A value of 0 means
+ * no strict priority cycles - the strict priority with anti-starvation
+ * arbiter becomes a round-robin arbiter.
+ */
+#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
+/* [R 15] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
+ * are for priority 0 client; bits [14:12] are for priority 4 client. The
+ * clients are assigned the following IDs: 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
+ * for management at priority 0; debug traffic at priorities 1 and 2; COS0
+ * traffic at priority 3; and COS1 traffic at priority 4.
+ */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
+/* [RW 32] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter.
+ */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
+/* [RW 4] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter.
+ */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
+/* [R 1] TX FIFO for transmitting data to MAC is empty. */
+#define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578
+/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
+ * packets to BRB LB interface to forward the packet to the host. All
+ * packets from MCP are forwarded to the network when this bit is cleared -
+ * regardless of the configured destination in tx_mng_destination register.
+ * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
+ * for BRB LB interface is bypassed and PBF LB traffic is always selected to
+ * send to BRB LB.
+ */
+#define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4
+/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
+ * forwarded to the host.
+ */
+#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8
+/* [R 1] Indication that HBUF descriptor FIFO is empty. */
+#define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header.
+ */
+#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
+/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
+ * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
+ * disabled when this bit is set.
+ */
+#define NIG_REG_P1_HWPFC_ENABLE 0x181d0
+#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
+/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Writing a 1 to bit 16
+ * will clear the buffer.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
+ * packets only and require that the packet is IPv4 for the rules to match.
+ * Note that rules 4-7 are for IPv6 packets only and require that the packet
+ * is IPv6 for the rules to match.
+ */
+#define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc
+/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
+#define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4
+/* [RW 1] Input enable for RX MAC interface. */
+#define NIG_REG_P1_MAC_IN_EN 0x185c0
+/* [RW 1] Output enable for TX MAC interface */
+#define NIG_REG_P1_MAC_OUT_EN 0x185c4
+/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
+#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
+/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
+ * future expansion) each priority is to be mapped to. Bits 3:0 specify the
+ * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
+ * priority field is extracted from the outer-most VLAN in receive packet.
+ * Only COS 0 and COS 1 are supported in E2.
+ */
+#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
+/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
+ * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
+ * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
+ * frame format in timesync event detection on RX side. Bit 3 enables
+ * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
+ * detection on TX side. Bit 5 enables V2 frame format in timesync event
+ * detection on TX side. Note that for HW to detect PTP packet and extract
+ * data from the packet, at least one of the version bits of that traffic
+ * direction has to be enabled.
+ */
+#define NIG_REG_P1_PTP_EN 0x187b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
+ * priority is mapped to COS 0 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
+ * priority is mapped to COS 1 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
+ * priority is mapped to COS 2 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
+/* [R 1] RX FIFO for receiving data from MAC is empty. */
+#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
+/* [R 1] TLLH FIFO is empty. */
+#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
+/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Bit 17 indicates that
+ * the sequence ID is valid and it is waiting for the TX timestamp value.
+ * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
+ * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules.
+ */
+#define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc
+/* [RW 32] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients. Note also that there are
+ * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
+ * credit registers 0-5 are valid. This register should be configured
+ * appropriately before enabling WFQ.
+ */
+#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
+/* [RW 4] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients. Note also that there are
+ * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
+ * credit registers 0-5 are valid. This register should be configured
+ * appropriately before enabling WFQ.
+ */
+#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
+/* [RW 9] Specify whether the client competes directly in the strict
+ * priority arbiter. The bits are mapped according to client ID (client IDs
+ * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
+ * Default value is set to enable strict priorities for all clients.
+ */
+#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
+/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
+ * bits are mapped according to client ID (client IDs are defined in
+ * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
+ * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
+ * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
+ * 0 for not using WFQ credit blocking.
+ */
+#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
+/* [RW 32] Specify the upper bound that credit register 0 is allowed to
+ * reach.
+ */
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
+/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
+ * when it is time to increment.
+ */
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
+/* [RW 12] Specify the number of strict priority arbitration slots between
+ * two round-robin arbitration slots to avoid starvation. A value of 0 means
+ * no strict priority cycles - the strict priority with anti-starvation
+ * arbiter becomes a round-robin arbiter.
+ */
+#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
+/* [RW 32] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter. Note that this register
+ * is the same as the one for port 0, except that port 1 only has COS 0-2
+ * traffic. There is no traffic for COS 3-5 of port 1.
+ */
+#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
+/* [RW 4] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter. Note that this register
+ * is the same as the one for port 0, except that port 1 only has COS 0-2
+ * traffic. There is no traffic for COS 3-5 of port 1.
+ */
+#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
+/* [R 1] TX FIFO for transmitting data to MAC is empty. */
+#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
+/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
+ * packets to BRB LB interface to forward the packet to the host. All
+ * packets from MCP are forwarded to the network when this bit is cleared -
+ * regardless of the configured destination in tx_mng_destination register.
+ */
+#define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8
+/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
+ * forwarded to the host.
+ */
+#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
+/* [RW 1] Pause enable for port0. This register may get 1 only when
+ * ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
+ * port
+ */
+#define NIG_REG_PAUSE_ENABLE_0 0x160c0
+#define NIG_REG_PAUSE_ENABLE_1 0x160c4
+/* [RW 1] Value of this register will be transmitted to port swap when
+ * ~nig_registers_strap_override.strap_override =1
+ */
+#define NIG_REG_PORT_SWAP 0x10394
+/* [RW 1] PPP enable for port0. This register may get 1 only when
+ * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
+ * same port
+ */
+#define NIG_REG_PPP_ENABLE_0 0x160b0
+#define NIG_REG_PPP_ENABLE_1 0x160b4
+/* [RW 1] Input enable for RX parser request IF */
+#define NIG_REG_PRS_REQ_IN_EN 0x100b8
+/* [R 5] control to serdes - CL45 DEVAD */
+#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
+/* [R 1] control to serdes; 0 - clause 45; 1 - clause 22 */
+#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
+/* [R 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
+#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
+/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
+#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
+/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
+ * for port 0 COS0
+ */
+#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
+/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
+ * for port 0 COS0
+ */
+#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
+/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
+ * between 1024 and 1522 bytes for port0
+ */
+#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
+/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
+ * between 1523 bytes and above for port0
+ */
+#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
+/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
+ * for port 1 COS0
+ */
+#define NIG_REG_STAT1_BRB_DISCARD 0x10628
+/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
+ * between 1024 and 1522 bytes for port1
+ */
+#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
+/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
+ * between 1523 bytes and above for port1
+ */
+#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
+/* [WB_R 64] Rx statistics : User octets received for LP */
+#define NIG_REG_STAT2_BRB_OCTET 0x107e0
+#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
+/* [RW 1] port swap mux selection. If this register equal to 0 then port
+ * swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
+ * ort swap is equal to ~nig_registers_port_swap.port_swap
+ */
+#define NIG_REG_STRAP_OVERRIDE 0x10398
+/* [WB 64] Addresses for TimeSync related registers in the timesync
+ * generator sub-module.
+ */
+#define NIG_REG_TIMESYNC_GEN_REG 0x18800
+/* [RW 1] output enable for RX_XCM0 IF */
+#define NIG_REG_XCM0_OUT_EN 0x100f0
+/* [RW 1] output enable for RX_XCM1 IF */
+#define NIG_REG_XCM1_OUT_EN 0x100f4
+/* [R 1] control to xgxs - remote PHY in-band MDIO */
+#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
+/* [R 5] control to xgxs - CL45 DEVAD */
+#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
+/* [R 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
+#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
+/* [R 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
+#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
+/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
+#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
+/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
+#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
+/* [R 2] selection for XGXS lane of port 0 in NIG_MUX block */
+#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
+/* [R 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
+#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1 << 0)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1 << 9)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1 << 15)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf << 18)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
+/* [RW 1] Interrupt mask register #0 read/write */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_MASK 0xcc
+/* [R 1] Interrupt register #0 read */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS 0xc0
+/* [RC 1] Interrupt register #0 read clear */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS_CLR 0xc4
+/* [R 31] Removed for E3 B0 -The upper bound of the weight of COS0 in the
+ * ETS command arbiter.
+ */
+#define PBF_REG_COS0_UPPER_BOUND 0x15c05c
+/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
+ * of port 0.
+ */
+#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
+/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
+ * of port 1.
+ */
+#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
+/* [R 31] Removed for E3 B0 - The weight of COS0 in the ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT 0x15c054
+/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
+/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
+/* [R 31] Removed for E3 B0 -The upper bound of the weight of COS1 in the
+ * ETS command arbiter.
+ */
+#define PBF_REG_COS1_UPPER_BOUND 0x15c060
+/* [R 31] Removed for E3 B0 - The weight of COS1 in the ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT 0x15c058
+/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
+/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
+/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
+#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
+/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
+#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
+/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
+#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
+/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
+#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
+/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
+#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
+/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_LB_Q 0x140338
+/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q0 0x14033c
+/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q1 0x140340
+/* [R 11] Current credit for queue 2 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q2 0x140344
+/* [R 11] Current credit for queue 3 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q3 0x140348
+/* [R 11] Current credit for queue 4 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q4 0x14034c
+/* [R 11] Current credit for queue 5 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q5 0x140350
+/* [R 1] Removed for E3 B0 - Disable processing further tasks from port 0
+ * (after ending the current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
+/* [R 1] Removed for E3 B0 - Disable processing further tasks from port 1
+ * (after ending the current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bc
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1cc
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0
+#define PBF_REG_DISABLE_PF 0x1402e8
+#define PBF_REG_DISABLE_VF 0x1402ec
+/* [RW 18] For port 0: For each client that is subject to WFQ (the
+ * corresponding bit is 1); indicates to which of the credit registers this
+ * client is mapped. For clients which are not credit blocked; their mapping
+ * is dont care.
+ */
+#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
+/* [RW 9] For port 1: For each client that is subject to WFQ (the
+ * corresponding bit is 1); indicates to which of the credit registers this
+ * client is mapped. For clients which are not credit blocked; their mapping
+ * is dont care.
+ */
+#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
+/* [RW 6] For port 0: Bit per client to indicate if the client competes in
+ * the strict priority arbiter directly (corresponding bit = 1); or first
+ * goes to the RR arbiter (corresponding bit = 0); and then competes in the
+ * lowest priority in the strict-priority arbiter.
+ */
+#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
+/* [RW 3] For port 1: Bit per client to indicate if the client competes in
+ * the strict priority arbiter directly (corresponding bit = 1); or first
+ * goes to the RR arbiter (corresponding bit = 0); and then competes in the
+ * lowest priority in the strict-priority arbiter.
+ */
+#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
+/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
+ * WFQ credit blocking (corresponding bit = 1).
+ */
+#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
+/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
+ * WFQ credit blocking (corresponding bit = 1).
+ */
+#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
+/* [RW 16] For port 0: The number of strict priority arbitration slots
+ * between 2 RR arbitration slots. A value of 0 means no strict priority
+ * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
+ * arbiter.
+ */
+#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
+/* [RW 16] For port 1: The number of strict priority arbitration slots
+ * between 2 RR arbitration slots. A value of 0 means no strict priority
+ * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
+ * arbiter.
+ */
+#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
+/* [RW 18] For port 0: Indicates which client is connected to each priority
+ * in the strict-priority arbiter. Priority 0 is the highest priority, and
+ * priority 5 is the lowest; to which the RR output is connected to (this is
+ * not configurable).
+ */
+#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
+/* [RW 9] For port 1: Indicates which client is connected to each priority
+ * in the strict-priority arbiter. Priority 0 is the highest priority, and
+ * priority 5 is the lowest; to which the RR output is connected to (this is
+ * not configurable).
+ */
+#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
+/* [R 1] Removed for E3 B0 - Indicates that ETS is performed between the
+ * COSes in the command arbiter. If reset strict priority w/ anti-starvation
+ * will be performed w/o WFQ.
+ */
+#define PBF_REG_ETS_ENABLED 0x15c050
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header.
+ */
+#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
+#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
+/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
+ * priority in the command arbiter.
+ */
+#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
+/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_LB_Q 0x15c248
+/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q0 0x15c230
+/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q1 0x15c234
+/* [RW 11] Initial credit for queue 2 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q2 0x15c238
+/* [RW 11] Initial credit for queue 3 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q3 0x15c23c
+/* [RW 11] Initial credit for queue 4 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q4 0x15c240
+/* [RW 11] Initial credit for queue 5 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q5 0x15c244
+/* [R 1] Removed for E3 B0 - Init bit for port 0. When set the initial
+ * credit of port 0 is copied to the credit register. Should be set and then
+ * reset after the configuration of the port has ended.
+ */
+#define PBF_REG_INIT_P0 0x140004
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * the LB queue. Reset upon init.
+ */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * queue 0. Reset upon init.
+ */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * queue 1. Reset upon init.
+ */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
+/* [RW 1] Enable for mac interface 0. */
+#define PBF_REG_MAC_IF0_ENABLE 0x140030
+/* [RW 6] Bit-map indicating which headers must appear in the packet */
+#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
+/* [R 16] Removed for E3 B0 - The number of strict priority arbitration
+ * slots between 2 RR arbitration slots. A value of 0 means no strict
+ * priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a
+ * RR arbiter.
+ */
+#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
+/* [R 11] Removed for E3 B0 - Port 0 threshold used by arbiter in 16 byte
+ * lines used when pause not suppoterd.
+ */
+#define PBF_REG_P0_ARB_THRSH 0x1400e4
+/* [R 11] Removed for E3 B0 - Current credit for port 0 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P0_CREDIT 0x140200
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P0_INIT_CRD 0x1400d0
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 0. Reset upon init.
+ */
+#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
+/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
+#define PBF_REG_P0_PAUSE_ENABLE 0x140014
+/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
+#define PBF_REG_P0_TASK_CNT 0x140204
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 0. Reset upon init.
+ */
+#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
+#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
+/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P1_CREDIT 0x140208
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P1_INIT_CRD 0x1400d4
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 1. Reset upon init.
+ */
+#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
+/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
+#define PBF_REG_P1_TASK_CNT 0x14020c
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 1. Reset upon init.
+ */
+#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
+#define PBF_REG_P1_TQ_OCCUPANCY 0x140300
+/* [R 11] Removed for E3 B0 - Current credit for port 4 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P4_CREDIT 0x140210
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P4_INIT_CRD 0x1400e0
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 4. Reset upon init.
+ */
+#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
+/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
+#define PBF_REG_P4_TASK_CNT 0x140214
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 4. Reset upon init.
+ */
+#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
+#define PBF_REG_P4_TQ_OCCUPANCY 0x140304
+/* [RW 7] Interrupt mask register #0 read/write */
+#define PBF_REG_PBF_INT_MASK 0x1401d4
+/* [R 7] Interrupt register #0 read */
+#define PBF_REG_PBF_INT_STS 0x1401c8
+/* [RC 7] Interrupt register #0 read clear */
+#define PBF_REG_PBF_INT_STS_CLR 0x1401cc
+/* [RW 28] Parity mask register #0 read/write */
+#define PBF_REG_PBF_PRTY_MASK 0x1401e4
+/* [R 28] Parity register #0 read */
+#define PBF_REG_PBF_PRTY_STS 0x1401d8
+/* [RC 28] Parity register #0 read clear */
+#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
+/* [RW 16] The Ethernet type value for L2 tag 0 */
+#define PBF_REG_TAG_ETHERTYPE_0 0x15c090
+/* [RW 4] The length of the info field for L2 tag 0. The length is between
+ * 2B and 14B; in 2B granularity
+ */
+#define PBF_REG_TAG_LEN_0 0x15c09c
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_LB_Q 0x140370
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q0 0x140374
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q1 0x140378
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q2 0x14037c
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q3 0x140380
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q4 0x140384
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q5 0x140388
+/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
+ * queue. Reset upon init.
+ */
+#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
+/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
+ * queue 0. Reset upon init.
+ */
+#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
+/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
+ * Reset upon init.
+ */
+#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
+/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
+ * queue.
+ */
+#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
+/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
+#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
+/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
+#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
+/* [RW 16] One of 8 values that should be compared to type in Ethernet
+ * parsing. If there is a match; the field after Ethernet is the first VLAN.
+ * Reset value is 0x8100 which is the standard VLAN type. Note that when
+ * checking second VLAN; type is compared only to 0x8100.
+ */
+#define PBF_REG_VLAN_TYPE_0 0x15c06c
+/* [RW 2] Interrupt mask register #0 read/write */
+#define PB_REG_PB_INT_MASK 0x28
+/* [R 2] Interrupt register #0 read */
+#define PB_REG_PB_INT_STS 0x1c
+/* [RC 2] Interrupt register #0 read clear */
+#define PB_REG_PB_INT_STS_CLR 0x20
+/* [RW 4] Parity mask register #0 read/write */
+#define PB_REG_PB_PRTY_MASK 0x38
+/* [R 4] Parity register #0 read */
+#define PB_REG_PB_PRTY_STS 0x2c
+/* [RC 4] Parity register #0 read clear */
+#define PB_REG_PB_PRTY_STS_CLR 0x30
+#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1 << 0)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1 << 8)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1 << 1)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1 << 6)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1 << 7)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1 << 4)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1 << 3)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1 << 5)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1 << 2)
+/* [R 8] Config space A attention dirty bits. Each bit indicates that the
+ * corresponding PF generates config space A attention. Set by PXP. Reset by
+ * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
+ * from both paths.
+ */
+#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
+/* [R 8] Config space B attention dirty bits. Each bit indicates that the
+ * corresponding PF generates config space B attention. Set by PXP. Reset by
+ * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
+ * from both paths.
+ */
+#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
+/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
+ * that the FLR register of the corresponding PF was set. Set by PXP. Reset
+ * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
+ * from both paths.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
+/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
+ * to a bit in this register in order to clear the corresponding bit in
+ * flr_request_pf_7_0 register. Note: register contains bits from both
+ * paths.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
+/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
+/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
+/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
+/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
+/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
+ * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
+ * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
+ * arrived with a correctable error. Bit 3 - Configuration RW arrived with
+ * an uncorrectable error. Bit 4 - Completion with Configuration Request
+ * Retry Status. Bit 5 - Expansion ROM access received with a write request.
+ * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
+ * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
+ * and pcie_rx_last not asserted.
+ */
+#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
+/* [W 7] Writing 1 to each bit in this register clears a corresponding error
+ * details register and enables logging new error details. Bit 0 - clears
+ * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears
+ * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS
+ * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32
+ * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -
+ * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears
+ * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6
+ * - clears TCPL_IN_TWO_RCBS_DETAILS.
+ */
+#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c
+/* [RW 11] Interrupt mask register #0 read/write */
+#define PGLUE_B_REG_PGLUE_B_INT_MASK 0x92a4
+/* [R 11] Interrupt register #0 read */
+#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
+/* [RC 11] Interrupt register #0 read clear */
+#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
+/* [RW 2] Parity mask register #0 read/write */
+#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
+/* [R 2] Parity register #0 read */
+#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
+/* [RC 2] Parity register #0 read clear */
+#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
+/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
+ * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
+ * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
+ * completer abort. 3 - Illegal value for this field. [12] valid - indicates
+ * if there was a completion error since the last time this register was
+ * cleared.
+ */
+#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
+/* [R 18] Details of first ATS Translation Completion request received with
+ * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
+ * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
+ * unsupported request. 2 - completer abort. 3 - Illegal value for this
+ * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
+ * completion error since the last time this register was cleared.
+ */
+#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
+/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
+ * a bit in this register in order to clear the corresponding bit in
+ * shadow_bme_pf_7_0 register. MCP should never use this unless a
+ * work-around is needed. Note: register contains bits from both paths.
+ */
+#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
+/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
+ * VF enable register of the corresponding PF is written to 0 and was
+ * previously 1. Set by PXP. Reset by MCP writing 1 to
+ * sr_iov_disabled_request_clr. Note: register contains bits from both
+ * paths.
+ */
+#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
+/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
+ * completion did not return yet. 1 - tag is unused. Same functionality as
+ * pxp2_registers_pgl_exp_rom_data2 for tags 0-31.
+ */
+#define PGLUE_B_REG_TAGS_63_32 0x9244
+/* [R 32] Address [31:0] of first read request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
+/* [R 32] Address [63:32] of first read request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
+/* [R 31] Details of first read request not submitted due to error. [4:0]
+ * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
+ * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
+ * VFID.
+ */
+#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
+/* [R 26] Details of first read request not submitted due to error. [15:0]
+ * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
+ * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
+ * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
+ * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
+ * indicates if there was a request not submitted due to error since the
+ * last time this register was cleared.
+ */
+#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
+/* [R 32] Address [31:0] of first write request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
+/* [R 32] Address [63:32] of first write request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
+/* [R 31] Details of first write request not submitted due to error. [4:0]
+ * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
+ * - VFID.
+ */
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
+/* [R 26] Details of first write request not submitted due to error. [15:0]
+ * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
+ * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
+ * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
+ * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
+ * indicates if there was a request not submitted due to error since the
+ * last time this register was cleared.
+ */
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
+/* [R 26] Details of first target VF request accessing VF GRC space that
+ * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
+ * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
+ * request accessing VF GRC space that failed permission check since the
+ * last time this register was cleared. Permission checks are: function
+ * permission; R/W permission; address range permission.
+ */
+#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
+/* [R 31] Details of first target VF request with length violation (too many
+ * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
+ * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
+ * valid - indicates if there was a request with length violation since the
+ * last time this register was cleared. Length violations: length of more
+ * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
+ * length is more than 1 DW.
+ */
+#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
+/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
+ * that there was a completion with uncorrectable error for the
+ * corresponding PF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_pf_7_0_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
+/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
+ * to a bit in this register in order to clear the corresponding bit in
+ * flr_request_pf_7_0 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
+/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_127_96_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
+/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
+ * writes 1 to a bit in this register in order to clear the corresponding
+ * bit in was_error_vf_127_96 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
+/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_31_0_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
+/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_31_0 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
+/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_63_32_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
+/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_63_32 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
+/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_95_64_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
+/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_95_64 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
+#define PRS_REG_A_PRSU_20 0x40134
+/* [R 8] debug only: CFC load request current credit. Transaction based. */
+#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
+/* [R 8] debug only: CFC search request current credit. Transaction based. */
+#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
+/* [RW 6] The initial credit for the search message to the CFC interface.
+ * Credit is transaction based.
+ */
+#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
+/* [RW 24] CID for port 0 if no match */
+#define PRS_REG_CID_PORT_0 0x400fc
+/* [RW 1] Indicates if in outer vlan mode. 0=non-outer-vlan mode; 1 = outer
+ * vlan mode.
+ */
+#define PRS_REG_E1HOV_MODE 0x401c8
+/* [R 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header.
+ */
+#define PRS_REG_HDRS_AFTER_BASIC 0x40238
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header for port 0 packets.
+ */
+#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
+#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
+/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
+#define PRS_REG_HDRS_AFTER_TAG_0 0x40248
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
+ * port 0 packets
+ */
+#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
+#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
+/* [R 6] Bit-map indicating which headers must appear in the packet */
+#define PRS_REG_MUST_HAVE_HDRS 0x40254
+/* [RW 6] Bit-map indicating which headers must appear in the packet for
+ * port 0 packets
+ */
+#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
+#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
+#define PRS_REG_NIC_MODE 0x40138
+/* [ST 24] The number of input packets */
+#define PRS_REG_NUM_OF_PACKETS 0x40124
+/* [R 2] debug only: Number of pending requests for CAC on port 0. */
+#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
+/* [R 2] debug only: Number of pending requests for header parsing. */
+#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
+/* [RW 1] Interrupt mask register #0 read/write */
+#define PRS_REG_PRS_INT_MASK 0x40194
+/* [R 1] Interrupt register #0 read */
+#define PRS_REG_PRS_INT_STS 0x40188
+/* [RC 1] Interrupt register #0 read clear */
+#define PRS_REG_PRS_INT_STS_CLR 0x4018c
+/* [RW 8] Parity mask register #0 read/write */
+#define PRS_REG_PRS_PRTY_MASK 0x401a4
+/* [R 8] Parity register #0 read */
+#define PRS_REG_PRS_PRTY_STS 0x40198
+/* [RC 8] Parity register #0 read clear */
+#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
+/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
+ * serail number was released by SDM but cannot be used because a previous
+ * serial number was not released.
+ */
+#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
+/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
+ * serail number was released by SDM but cannot be used because a previous
+ * serial number was not released.
+ */
+#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
+/* [R 4] debug only: SRC current credit. Transaction based. */
+#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
+/* [RW 16] The Ethernet type value for L2 tag 0 */
+#define PRS_REG_TAG_ETHERTYPE_0 0x401d4
+/* [RW 4] The length of the info field for L2 tag 0. The length is between
+ * 2B and 14B; in 2B granularity
+ */
+#define PRS_REG_TAG_LEN_0 0x4022c
+/* [R 8] debug only: TCM current credit. Cycle based. */
+#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
+/* [R 8] debug only: TSDM current credit. Transaction based. */
+#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
+/* [RW 16] One of 8 values that should be compared to type in Ethernet
+ * parsing. If there is a match; the field after Ethernet is the first VLAN.
+ * Reset value is 0x8100 which is the standard VLAN type. Note that when
+ * checking second VLAN; type is compared only to 0x8100.
+ */
+#define PRS_REG_VLAN_TYPE_0 0x401a8
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1 << 19)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1 << 20)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1 << 22)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1 << 23)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1 << 24)
+#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1 << 7)
+#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1 << 7)
+/* [R 7] Debug only: Number of used entries in the data FIFO */
+#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
+/* [R 7] Debug only: Number of used entries in the header FIFO */
+#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
+#define PXP2_REG_PGL_ADDR_88_F0 0x120534
+/* [R 32] GRC address for configuration access to PCIE config address 0x88.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register
+ */
+#define PXP2_REG_PGL_ADDR_88_F1 0x120544
+#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
+/* [R 32] GRC address for configuration access to PCIE config address 0x8c.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register
+ */
+#define PXP2_REG_PGL_ADDR_8C_F1 0x120548
+#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
+/* [R 32] GRC address for configuration access to PCIE config address 0x90.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register
+ */
+#define PXP2_REG_PGL_ADDR_90_F1 0x12054c
+#define PXP2_REG_PGL_ADDR_94_F0 0x120540
+/* [R 32] GRC address for configuration access to PCIE config address 0x94.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register
+ */
+#define PXP2_REG_PGL_ADDR_94_F1 0x120550
+/* [RW 32] third dword data of expansion rom request. this register is
+ * special. reading from it provides a vector outstanding read requests. if
+ * a bit is zero it means that a read request on the corresponding tag did
+ * not finish yet (not all completions have arrived for it)
+ */
+#define PXP2_REG_PGL_EXP_ROM2 0x120808
+/* [RW 16] this field allows one function to pretend being another function
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated. Bits [15] - force. Bits [14] - path
+ * ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits
+ * [2:0] - PFID.
+ */
+#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
+/* [RW 16] this field allows one function to pretend being another function
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated. Bits [15] - force. Bits [14] - path
+ * ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits
+ * [2:0] - PFID.
+ */
+#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
+/* [R 1] this bit indicates that a read request was blocked because of
+ * bus_master_en was deasserted
+ */
+#define PXP2_REG_PGL_READ_BLOCKED 0x120568
+#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
+/* [R 21] debug only */
+#define PXP2_REG_PGL_TXW_CDTS 0x12052c
+/* [R 1] this bit indicates that a write request was blocked because of
+ * bus_master_en was deasserted
+ */
+#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
+#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
+#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
+#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
+#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
+#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
+#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
+#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
+#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
+#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
+#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
+#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
+#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
+#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
+#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
+#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
+#define PXP2_REG_PSWRQ_BW_L28 0x120318
+#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
+#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
+#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
+#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
+#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
+#define PXP2_REG_PSWRQ_BW_RD 0x120324
+#define PXP2_REG_PSWRQ_BW_UB1 0x120238
+#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
+#define PXP2_REG_PSWRQ_BW_UB11 0x120260
+#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
+#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
+#define PXP2_REG_PSWRQ_BW_UB3 0x120240
+#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
+#define PXP2_REG_PSWRQ_BW_UB7 0x120250
+#define PXP2_REG_PSWRQ_BW_UB8 0x120254
+#define PXP2_REG_PSWRQ_BW_UB9 0x120258
+#define PXP2_REG_PSWRQ_BW_WR 0x120328
+#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
+#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
+#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
+#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
+#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define PXP2_REG_PXP2_INT_MASK_0 0x120578
+#define PXP2_REG_PXP2_INT_MASK_1 0x120614
+/* [R 32] Interrupt register #0 read */
+#define PXP2_REG_PXP2_INT_STS_0 0x12056c
+#define PXP2_REG_PXP2_INT_STS_1 0x120608
+/* [RC 32] Interrupt register #0 read clear */
+#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
+#define PXP2_REG_PXP2_INT_STS_CLR_1 0x12060c
+/* [RW 32] Parity mask register #0 read/write */
+#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
+#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
+/* [R 32] Parity register #0 read */
+#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
+#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
+/* [RC 32] Parity register #0 read clear */
+#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
+#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
+/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
+ * indication about backpressure)
+ */
+#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
+/* [R 8] Debug only: The blocks counter - number of unused block ids */
+#define PXP2_REG_RD_BLK_CNT 0x120418
+/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
+ * Must be bigger than 6. Normally should not be changed.
+ */
+#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
+/* [RW 2] CDU byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
+/* [R 29] Details of first request with error on receive side: [15:0] - Echo
+ * ID. [28:16] - sub-request length plus start_offset_2_0 minus 1.
+ */
+#define PXP2_REG_RD_CPL_ERR_DETAILS 0x120778
+/* [R 10] Details of first request with error on receive side: [4:0] - VQ
+ * ID. [8:5] - client ID. [9] - valid - indicates if there was a completion
+ * error since the last time this register was read.
+ */
+#define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077c
+/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
+#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
+/* [R 1] PSWRD internal memories initialization is done */
+#define PXP2_REG_RD_INIT_DONE 0x120370
+/* [R 1] Debug only: Indication if delivery ports are idle */
+#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
+#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
+/* [RW 2] QM byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
+/* [RW 2] SRC byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
+/* [R 7] Debug only: The SR counter - number of unused sub request ids */
+#define PXP2_REG_RD_SR_CNT 0x120414
+/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
+ * be bigger than 1. Normally should not be changed.
+ */
+#define PXP2_REG_RD_SR_NUM_CFG 0x120408
+/* [RW 1] Signals the PSWRD block to start initializing internal memories */
+#define PXP2_REG_RD_START_INIT 0x12036c
+/* [RW 2] TM byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
+/* [RW 10] Bandwidth addition to VQ0 write requests */
+#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
+/* [RW 10] Bandwidth addition to VQ12 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
+/* [RW 10] Bandwidth addition to VQ13 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
+/* [RW 10] Bandwidth addition to VQ14 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
+/* [RW 10] Bandwidth addition to VQ15 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
+/* [RW 10] Bandwidth addition to VQ16 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
+/* [RW 10] Bandwidth addition to VQ17 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
+/* [RW 10] Bandwidth addition to VQ18 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
+/* [RW 10] Bandwidth addition to VQ19 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
+/* [RW 10] Bandwidth addition to VQ20 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
+/* [RW 10] Bandwidth addition to VQ22 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
+/* [RW 10] Bandwidth addition to VQ23 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
+/* [RW 10] Bandwidth addition to VQ24 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
+/* [RW 10] Bandwidth addition to VQ25 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
+/* [RW 10] Bandwidth addition to VQ26 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
+/* [RW 10] Bandwidth addition to VQ27 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
+/* [RW 10] Bandwidth addition to VQ4 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
+/* [RW 10] Bandwidth addition to VQ5 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
+/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
+#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
+/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
+#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
+/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
+#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
+/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
+#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
+/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
+#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
+/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
+#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
+/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
+#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
+/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
+#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
+/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
+#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
+/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
+#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
+/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
+#define PXP2_REG_RQ_BW_RD_L22 0x120300
+/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
+#define PXP2_REG_RQ_BW_RD_L23 0x120304
+/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
+#define PXP2_REG_RQ_BW_RD_L24 0x120308
+/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
+#define PXP2_REG_RQ_BW_RD_L25 0x12030c
+/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
+#define PXP2_REG_RQ_BW_RD_L26 0x120310
+/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
+#define PXP2_REG_RQ_BW_RD_L27 0x120314
+/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
+#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
+/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
+#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
+/* [RW 7] Bandwidth upper bound for VQ0 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
+/* [RW 7] Bandwidth upper bound for VQ12 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
+/* [RW 7] Bandwidth upper bound for VQ13 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
+/* [RW 7] Bandwidth upper bound for VQ14 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
+/* [RW 7] Bandwidth upper bound for VQ15 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
+/* [RW 7] Bandwidth upper bound for VQ16 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
+/* [RW 7] Bandwidth upper bound for VQ17 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
+/* [RW 7] Bandwidth upper bound for VQ18 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
+/* [RW 7] Bandwidth upper bound for VQ19 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
+/* [RW 7] Bandwidth upper bound for VQ20 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
+/* [RW 7] Bandwidth upper bound for VQ22 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
+/* [RW 7] Bandwidth upper bound for VQ23 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
+/* [RW 7] Bandwidth upper bound for VQ24 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
+/* [RW 7] Bandwidth upper bound for VQ25 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
+/* [RW 7] Bandwidth upper bound for VQ26 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
+/* [RW 7] Bandwidth upper bound for VQ27 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
+/* [RW 7] Bandwidth upper bound for VQ4 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
+/* [RW 7] Bandwidth upper bound for VQ5 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
+/* [RW 10] Bandwidth addition to VQ29 write requests */
+#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
+/* [RW 10] Bandwidth addition to VQ30 write requests */
+#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
+/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
+#define PXP2_REG_RQ_BW_WR_L29 0x12031c
+/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
+#define PXP2_REG_RQ_BW_WR_L30 0x120320
+/* [RW 7] Bandwidth upper bound for VQ29 */
+#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
+/* [RW 7] Bandwidth upper bound for VQ30 */
+#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
+/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
+#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
+/* [RW 2] Endian mode for cdu */
+#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
+#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
+#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
+/* [RW 4] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M
+ */
+#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
+/* [R 1] 1' indicates that the requester has finished its internal
+ * configuration
+ */
+#define PXP2_REG_RQ_CFG_DONE 0x1201b4
+/* [RW 2] Endian mode for debug */
+#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
+/* [RW 1] When '1'; requests will enter input buffers but wont get out
+ * towards the glue
+ */
+#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
+/* [RW 4] Determines alignment of write SRs when a request is split into
+ * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
+ * aligned. 4 - 512B aligned.
+ */
+#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
+/* [RW 4] Determines alignment of read SRs when a request is split into
+ * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
+ * aligned. 4 - 512B aligned.
+ */
+#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
+/* [RW 1] when set the new alignment method (E2) will be applied; when reset
+ * the original alignment method (E1 E1H) will be applied
+ */
+#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
+/* [R 32] Status signals in pswrq_garb module */
+#define PXP2_REG_RQ_GARB 0x120748
+/* [RW 2] Endian mode for hc */
+#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
+/* [WB 53] Onchip address table */
+#define PXP2_REG_RQ_ONCHIP_AT 0x122000
+/* [WB 53] Onchip address table - B0 */
+#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
+/* [RW 13] Pending read limiter threshold; in Dwords */
+#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
+/* [RW 2] Endian mode for qm */
+#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
+#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
+#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
+/* [RW 4] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M
+ */
+#define PXP2_REG_RQ_QM_P_SIZE 0x120050
+/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
+#define PXP2_REG_RQ_RBC_DONE 0x1201b0
+/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
+ * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K
+ */
+#define PXP2_REG_RQ_RD_MBS0 0x120160
+/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
+ * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K
+ */
+#define PXP2_REG_RQ_RD_MBS1 0x120168
+/* [RW 2] Endian mode for src */
+#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
+#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
+#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
+/* [RW 4] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M
+ */
+#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
+/* [RW 2] Endian mode for tm */
+#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
+#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
+#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
+/* [RW 4] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M
+ */
+#define PXP2_REG_RQ_TM_P_SIZE 0x120034
+/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
+#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
+/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
+#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
+/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
+#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
+/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
+#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
+/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
+#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
+/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
+#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
+/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
+#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
+/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
+#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
+/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
+#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
+/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
+#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
+/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
+#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
+/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
+#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
+/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
+#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
+/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
+#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
+/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
+#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
+/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
+#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
+/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
+#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
+/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
+#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
+/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
+#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
+/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
+#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
+/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
+#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
+/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
+#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
+/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
+#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
+/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
+#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
+/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
+#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
+/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
+#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
+/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
+#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
+/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
+#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
+/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
+#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
+/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
+#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
+/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
+#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
+/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
+#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
+/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
+#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
+/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
+#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
+/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
+ * 001:256B; 010: 512B;
+ */
+#define PXP2_REG_RQ_WR_MBS0 0x12015c
+/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
+ * 001:256B; 010: 512B;
+ */
+#define PXP2_REG_RQ_WR_MBS1 0x120164
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_CDU_MPS 0x1205f0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_CSDM_MPS 0x1205d0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_DBG_MPS 0x1205e8
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_DMAE_MPS 0x1205ec
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_HC_MPS 0x1205c8
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_QM_MPS 0x1205dc
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_SRC_MPS 0x1205e4
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_TM_MPS 0x1205e0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_TSDM_MPS 0x1205d4
+/* [RW 9] a. When pxp2.wr_th_mode_usdmdp = 0 (E1.5-65 mode) should be
+ * initialized to (MPS/32); b. When pxp2.wr_th_mode_usdmdp = 1 (E1.5-90;
+ * enhanced mode) and pxp2.wr_usdmdp_outst_req is different than default (3)
+ * should be initialized to (pxp2.wr_usdmdp_outst_req x MPS/32); when
+ * pxp2.wr_usdmdp_outst_req is 3 the reset value is the correct
+ * configuration
+ */
+#define PXP2_REG_WR_USDMDP_TH 0x120348
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_USDM_MPS 0x1205cc
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_XSDM_MPS 0x1205d8
+/* [R 1] debug only: Indication if PSWHST arbiter is idle */
+#define PXP_REG_HST_ARB_IS_IDLE 0x103004
+/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
+ * this client is waiting for the arbiter.
+ */
+#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
+/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
+ * block. Should be used for close the gates.
+ */
+#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
+/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
+ * should update according to 'hst_discard_doorbells' register when the state
+ * machine is idle
+ */
+#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
+/* [RW 1] When 1; new internal writes arriving to the block are discarded.
+ * Should be used for close the gates.
+ */
+#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
+/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
+ * means this PSWHST is discarding inputs from this client. Each bit should
+ * update according to 'hst_discard_internal_writes' register when the state
+ * machine is idle.
+ */
+#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
+/* [R 1] 1 - An incorrect access is logged. The valid bit is reset when the
+ * relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
+ */
+#define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030cc
+/* [R 1] 1- permission violation data is logged. The valid bit is reset when
+ * the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
+ */
+#define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0
+/* [R 15] The FID of the first access to a disabled VF; the format is
+ * [14:12] - pfid; [11:6] - vfid; [5] - vf_valid; [4:1] - client (0 USDM; 1
+ * CSDM; 2 XSDM; 3 TSDM; 4 HC; 5 GRC; 6 DQ; 7 RESERVED SPACE; 8 ATC); [0] -
+ * w_nr(0-read req; 1- write req). The data is written only when the valid
+ * bit is reset. and it is stays stable until it is reset by the read from
+ * interrupt_clr register
+ */
+#define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b8
+/* [R 1] 1 - An error request is logged and wasn't handled yet. The valid
+ * bit is reset when the relevant interrupt register is read
+ * (PXP_REG_INT_STS_CLR_1)
+ */
+#define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bc
+/* [RW 7] Indirect access to the permission table. The fields are : {Valid;
+ * VFID[5:0]}
+ */
+#define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400
+/* [RW 32] Interrupt mask register #0 read/write */
+#define PXP_REG_PXP_INT_MASK_0 0x103074
+#define PXP_REG_PXP_INT_MASK_1 0x103084
+/* [R 32] Interrupt register #0 read */
+#define PXP_REG_PXP_INT_STS_0 0x103068
+#define PXP_REG_PXP_INT_STS_1 0x103078
+/* [RC 32] Interrupt register #0 read clear */
+#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
+#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
+/* [RW 27] Parity mask register #0 read/write */
+#define PXP_REG_PXP_PRTY_MASK 0x103094
+/* [R 27] Parity register #0 read */
+#define PXP_REG_PXP_PRTY_STS 0x103088
+/* [RC 27] Parity register #0 read clear */
+#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
+/* [RW 32] The base logical address (in bytes) of each physical queue. The
+ * index I represents the physical queue number. The 12 lsbs are ignore and
+ * considered zero so practically there are only 20 bits in this register;
+ * queues 63-0
+ */
+#define QM_REG_BASEADDR 0x168900
+/* [R 32] NOT USED */
+#define QM_REG_BASEADDR_EXT_A 0x16e100
+/* [R 18] The credit value for byte credit 0. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD0 0x16e6fc
+/* [R 18] The credit value for byte credit 1. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD1 0x16e700
+/* [R 18] The credit value for byte credit 2. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD2 0x16e704
+/* [R 18] The credit value for byte credit 3. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD3 0x16e7ac
+/* [R 18] The credit value for byte credit 4. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD4 0x16e7b0
+/* [R 18] The credit value for byte credit 5. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD5 0x16e7b4
+/* [R 18] The credit value for byte credit 6. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD6 0x16e7b8
+/* [R 32] NOT USED - removed for E3 B0 */
+#define QM_REG_BYTECRDCMDQ_0 0x16e6e8
+/* [RC 32] byte credit update error register; b2-b0: byte credit id (pbf
+ * error); b3 - reserved (zero filled); b6-b4: byte credit id (storm
+ * increment error); b7 - reserved (zero filled); b10-b8: byte credit id
+ * (storm decrement error); b11 - reserved (zero filled); b12: pbf error
+ * valid; b13: storm increment error valid; b14: storm decrement error
+ * valid; b15: reserved; b22-b16: byte credit warning (warning = decremented
+ * below zero). mask bit per voq counter; b31-b23: reserved; NOTE: VOQ id-s
+ * represent HW
+ */
+#define QM_REG_BYTECRDERRREG 0x16e708
+/* [RW 17] The initial byte credit value for all counters */
+#define QM_REG_BYTECRDINITVAL 0x168238
+/* [RW 20] The number of connections divided by 16 which dictates the size
+ * of each queue which belongs to even function number.
+ */
+#define QM_REG_CONNNUM_0 0x168020
+/* [R 6] Keep the fill level of the fifo from write client 4 */
+#define QM_REG_CQM_WRC_FIFOLVL 0x168018
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ0
+ */
+#define QM_REG_FWVOQ0TOHWVOQ 0x16e7bc
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ1
+ */
+#define QM_REG_FWVOQ1TOHWVOQ 0x16e7c0
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ2
+ */
+#define QM_REG_FWVOQ2TOHWVOQ 0x16e7c4
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ3
+ */
+#define QM_REG_FWVOQ3TOHWVOQ 0x16e7c8
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ4
+ */
+#define QM_REG_FWVOQ4TOHWVOQ 0x16e7cc
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ5
+ */
+#define QM_REG_FWVOQ5TOHWVOQ 0x16e7d0
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ6
+ */
+#define QM_REG_FWVOQ6TOHWVOQ 0x16e7d4
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ7
+ */
+#define QM_REG_FWVOQ7TOHWVOQ 0x16e7d8
+/* [RC 1] A flag to indicate that overflow error occurred in one of the
+ * queues.
+ */
+#define QM_REG_OVFERROR 0x16805c
+/* [RC 6] the Q were the qverflow occurs */
+#define QM_REG_OVFQNUM 0x168058
+/* [R 16] Pause state for physical queues 15-0 */
+#define QM_REG_PAUSESTATE0 0x168410
+/* [R 16] Pause state for physical queues 31-16 */
+#define QM_REG_PAUSESTATE1 0x168414
+/* [R 16] Pause state for physical queues 47-32 */
+#define QM_REG_PAUSESTATE2 0x16e684
+/* [R 16] Pause state for physical queues 63-48 */
+#define QM_REG_PAUSESTATE3 0x16e688
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE4 0x16e68c
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE5 0x16e690
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE6 0x16e694
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE7 0x16e698
+#define QM_REG_PF_EN 0x16e70c
+/* [R 24] The number of tasks stored in the QM for the PF. only even
+ * functions are valid in E2 (odd I registers will be hard wired to 0)
+ */
+#define QM_REG_PF_USG_CNT_0 0x16e040
+/* [R 16] NOT USED */
+#define QM_REG_PORT0BYTECRD 0x168300
+/* [R 16] NOT USED */
+#define QM_REG_PORT1BYTECRD 0x168304
+/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
+ * ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
+ * bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;
+ */
+#define QM_REG_PTRTBL 0x168a00
+/* [R 54] NOT USED */
+#define QM_REG_PTRTBL_EXT_A 0x16e200
+/* [RW 14] Interrupt mask register #0 read/write */
+#define QM_REG_QM_INT_MASK 0x168444
+/* [R 14] Interrupt register #0 read */
+#define QM_REG_QM_INT_STS 0x168438
+/* [RC 14] Interrupt register #0 read clear */
+#define QM_REG_QM_INT_STS_CLR 0x16843c
+/* [RW 12] Parity mask register #0 read/write */
+#define QM_REG_QM_PRTY_MASK 0x168454
+/* [R 12] Parity register #0 read */
+#define QM_REG_QM_PRTY_STS 0x168448
+/* [RC 12] Parity register #0 read clear */
+#define QM_REG_QM_PRTY_STS_CLR 0x16844c
+/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
+#define QM_REG_QSTATUS_HIGH 0x16802c
+/* [R 32] NOT USED */
+#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
+/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
+#define QM_REG_QSTATUS_LOW 0x168028
+/* [R 32] NOT USED */
+#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
+/* [R 24] The number of tasks queued for each queue; queues 63-0 */
+#define QM_REG_QTASKCTR_0 0x168308
+/* [R 24] NOT USED */
+#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
+/* [RW 4] Queue tied to VOQ */
+#define QM_REG_QVOQIDX_0 0x1680f4
+/* [RW 1] Initialization bit command */
+#define QM_REG_SOFT_RESET 0x168428
+/* [R 6] Keep the fill level of the fifo from write client 3 */
+#define QM_REG_TQM_WRC_FIFOLVL 0x168010
+/* [R 6] Keep the fill level of the fifo from write client 2 */
+#define QM_REG_UQM_WRC_FIFOLVL 0x168008
+/* [RC 32] VOQ credit update error register; b3-b0: voq id (pbf error);
+ * b7-b4: voq id (storm increment error); b11-b8: voq id (storm decrement
+ * error); b12: pbf error valid; b13: storm increment error valid; b14:
+ * storm decrement error valid; b15: reserved; b27-b16: voq warning
+ * (warning = decremented below zero). mask bit per voq counter; b31-b28:
+ * reserved; NOTE: VOQ id-s represent HW VOQ id
+ */
+#define QM_REG_VOQCRDERRREG 0x168408
+/* [R 17] The credit value for each VOQ. The value is 2s complement value
+ * (i.e. msb is used for the sign).
+ */
+#define QM_REG_VOQCREDIT_0 0x1682d0
+#define QM_REG_VOQCREDIT_1 0x1682d4
+#define QM_REG_VOQCREDIT_2 0x1682d8
+#define QM_REG_VOQCREDIT_3 0x1682dc
+#define QM_REG_VOQCREDIT_4 0x1682e0
+#define QM_REG_VOQCREDIT_5 0x1682e4
+#define QM_REG_VOQCREDIT_6 0x1682e8
+/* [RW 16] The init and maximum credit for each VoQ */
+#define QM_REG_VOQINITCREDIT_0 0x168060
+#define QM_REG_VOQINITCREDIT_1 0x168064
+#define QM_REG_VOQINITCREDIT_2 0x168068
+#define QM_REG_VOQINITCREDIT_3 0x16806c
+#define QM_REG_VOQINITCREDIT_4 0x168070
+#define QM_REG_VOQINITCREDIT_5 0x168074
+#define QM_REG_VOQINITCREDIT_6 0x168078
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_0_LSB 0x168240
+/* [R 6] Keep the fill level of the fifo from write client 1 */
+#define QM_REG_XQM_WRC_FIFOLVL 0x168000
+/* [W 1] reset to parity interrupt */
+#define SEM_FAST_REG_PARITY_RST 0x18840
+/* [RW 1] Interrupt mask register #0 read/write */
+#define SEM_FAST_REG_SEM_FAST_INT_MASK 0x1fff0
+/* [R 1] Interrupt register #0 read */
+#define SEM_FAST_REG_SEM_FAST_INT_STS 0x1fffc
+/* [RC 1] Interrupt register #0 read clear */
+#define SEM_FAST_REG_SEM_FAST_INT_STS_CLR 0x1fff8
+/* [RW 1] Parity mask register #0 read/write */
+#define SEM_FAST_REG_SEM_FAST_PRTY_MASK 0x1ffe0
+/* [R 1] Parity register #0 read */
+#define SEM_FAST_REG_SEM_FAST_PRTY_STS 0x1ffec
+/* [RC 1] Parity register #0 read clear */
+#define SEM_FAST_REG_SEM_FAST_PRTY_STS_CLR 0x1ffe8
+#define SRC_REG_COUNTFREE0 0x40500
+#define SRC_REG_FIRSTFREE0 0x40510
+#define SRC_REG_KEYRSS0_0 0x40408
+#define SRC_REG_KEYRSS0_7 0x40424
+#define SRC_REG_KEYSEARCH_0 0x40458
+#define SRC_REG_KEYSEARCH_1 0x4045c
+#define SRC_REG_KEYSEARCH_2 0x40460
+#define SRC_REG_KEYSEARCH_3 0x40464
+#define SRC_REG_KEYSEARCH_4 0x40468
+#define SRC_REG_KEYSEARCH_5 0x4046c
+#define SRC_REG_KEYSEARCH_6 0x40470
+#define SRC_REG_KEYSEARCH_7 0x40474
+#define SRC_REG_KEYSEARCH_8 0x40478
+#define SRC_REG_KEYSEARCH_9 0x4047c
+#define SRC_REG_LASTFREE0 0x40530
+#define SRC_REG_NUMBER_HASH_BITS0 0x40400
+/* [RW 1] Reset internal state machines. */
+#define SRC_REG_SOFT_RST 0x4049c
+/* [RW 3] Interrupt mask register #0 read/write */
+#define SRC_REG_SRC_INT_MASK 0x404b8
+/* [R 3] Interrupt register #0 read */
+#define SRC_REG_SRC_INT_STS 0x404ac
+/* [RC 3] Interrupt register #0 read clear */
+#define SRC_REG_SRC_INT_STS_CLR 0x404b0
+/* [RW 3] Parity mask register #0 read/write */
+#define SRC_REG_SRC_PRTY_MASK 0x404c8
+/* [R 3] Parity register #0 read */
+#define SRC_REG_SRC_PRTY_STS 0x404bc
+/* [RC 3] Parity register #0 read clear */
+#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
+/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
+#define TCM_REG_CAM_OCCUP 0x5017c
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define TCM_REG_CFC_INIT_CRD 0x50204
+/* [RC 1] Message length mismatch (relative to last indication) at the In#9
+ * interface.
+ */
+#define TCM_REG_CSEM_LENGTH_MIS 0x50174
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define TCM_REG_FIC0_INIT_CRD 0x5020c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define TCM_REG_FIC1_INIT_CRD 0x50210
+/* [RC 1] Message length mismatch (relative to last indication) at the In#7
+ * interface.
+ */
+#define TCM_REG_PBF_LENGTH_MIS 0x5016c
+/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define TCM_REG_PRS_IFEN 0x50020
+/* [RC 1] Message length mismatch (relative to last indication) at the In#6
+ * interface.
+ */
+#define TCM_REG_PRS_LENGTH_MIS 0x50168
+/* [RC 1] Message length mismatch (relative to last indication) at the STORM
+ * interface.
+ */
+#define TCM_REG_STORM_LENGTH_MIS 0x50160
+/* [RW 11] Interrupt mask register #0 read/write */
+#define TCM_REG_TCM_INT_MASK 0x501dc
+/* [R 11] Interrupt register #0 read */
+#define TCM_REG_TCM_INT_STS 0x501d0
+/* [RC 11] Interrupt register #0 read clear */
+#define TCM_REG_TCM_INT_STS_CLR 0x501d4
+/* [RW 27] Parity mask register #0 read/write */
+#define TCM_REG_TCM_PRTY_MASK 0x501ec
+/* [R 27] Parity register #0 read */
+#define TCM_REG_TCM_PRTY_STS 0x501e0
+/* [RC 27] Parity register #0 read clear */
+#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define TCM_REG_TQM_INIT_CRD 0x5021c
+/* [RC 1] Message length mismatch (relative to last indication) at the SDM
+ * interface.
+ */
+#define TCM_REG_TSDM_LENGTH_MIS 0x50164
+/* [RC 1] Message length mismatch (relative to last indication) at the In#8
+ * interface.
+ */
+#define TCM_REG_USEM_LENGTH_MIS 0x50170
+/* [RW 21] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - length of the message; 15:6] - message
+ * pointer; 20:16] - next pointer.
+ */
+#define TCM_REG_XX_DESCR_TABLE 0x50280
+#define TCM_REG_XX_DESCR_TABLE_SIZE 29
+/* [R 6] Use to read the value of XX protection Free counter. */
+#define TCM_REG_XX_FREE 0x50178
+#define TM_REG_EN_LINEAR0_TIMER 0x164014
+/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
+#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
+/* [ST 16] Linear0 Number of scans counter. */
+#define TM_REG_LIN0_NUM_SCANS 0x1640a0
+#define TM_REG_LIN0_SCAN_ON 0x1640d0
+/* [RW 24] Linear0 array scan timeout. */
+#define TM_REG_LIN0_SCAN_TIME 0x16403c
+#define TM_REG_LIN0_VNIC_UC 0x164128
+/* [RW 1] Interrupt mask register #0 read/write */
+#define TM_REG_TM_INT_MASK 0x1640fc
+/* [R 1] Interrupt register #0 read */
+#define TM_REG_TM_INT_STS 0x1640f0
+/* [RC 1] Interrupt register #0 read clear */
+#define TM_REG_TM_INT_STS_CLR 0x1640f4
+/* [RW 7] Parity mask register #0 read/write */
+#define TM_REG_TM_PRTY_MASK 0x16410c
+/* [R 7] Parity register #0 read */
+#define TM_REG_TM_PRTY_STS 0x164100
+/* [RC 7] Parity register #0 read clear */
+#define TM_REG_TM_PRTY_STS_CLR 0x164104
+#define TSDM_REG_ENABLE_IN1 0x42238
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
+#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
+/* [R 32] Interrupt register #0 read */
+#define TSDM_REG_TSDM_INT_STS_0 0x42290
+#define TSDM_REG_TSDM_INT_STS_1 0x422a0
+/* [RC 32] Interrupt register #0 read clear */
+#define TSDM_REG_TSDM_INT_STS_CLR_0 0x42294
+#define TSDM_REG_TSDM_INT_STS_CLR_1 0x422a4
+/* [RW 11] Parity mask register #0 read/write */
+#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
+/* [R 11] Parity register #0 read */
+#define TSDM_REG_TSDM_PRTY_STS 0x422b0
+/* [RC 11] Parity register #0 read clear */
+#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each
+ * SEM_FAST register offset.
+ */
+#define TSEM_REG_FAST_MEMORY 0x1a0000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define TSEM_REG_INT_TABLE 0x180400
+/* [WB 128] Debug only. Passive buffer memory */
+#define TSEM_REG_PASSIVE_BUFFER 0x181000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define TSEM_REG_PRAM 0x1c0000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define TSEM_REG_TSEM_INT_MASK_0 0x180100
+#define TSEM_REG_TSEM_INT_MASK_1 0x180110
+/* [R 32] Interrupt register #0 read */
+#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
+#define TSEM_REG_TSEM_INT_STS_1 0x180104
+/* [RC 32] Interrupt register #0 read clear */
+#define TSEM_REG_TSEM_INT_STS_CLR_0 0x1800f8
+#define TSEM_REG_TSEM_INT_STS_CLR_1 0x180108
+/* [RW 32] Parity mask register #0 read/write */
+#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
+#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
+/* [R 32] Parity register #0 read */
+#define TSEM_REG_TSEM_PRTY_STS_0 0x180114
+#define TSEM_REG_TSEM_PRTY_STS_1 0x180124
+/* [RC 32] Parity register #0 read clear */
+#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
+#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
+ */
+#define TSEM_REG_VFPF_ERR_NUM 0x180380
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define UCM_REG_CAM_OCCUP 0xe0170
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define UCM_REG_CFC_INIT_CRD 0xe0204
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the csem interface is detected.
+ */
+#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the dorq interface is detected.
+ */
+#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define UCM_REG_FIC0_INIT_CRD 0xe020c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define UCM_REG_FIC1_INIT_CRD 0xe0210
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the STORM interface is detected.
+ */
+#define UCM_REG_STORM_LENGTH_MIS 0xe0154
+/* [RW 4] Timers output initial credit. Max credit available - 15.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 4 at start-up.
+ */
+#define UCM_REG_TM_INIT_CRD 0xe021c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the tsem interface is detected.
+ */
+#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
+/* [RW 11] Interrupt mask register #0 read/write */
+#define UCM_REG_UCM_INT_MASK 0xe01d4
+/* [R 11] Interrupt register #0 read */
+#define UCM_REG_UCM_INT_STS 0xe01c8
+/* [RC 11] Interrupt register #0 read clear */
+#define UCM_REG_UCM_INT_STS_CLR 0xe01cc
+/* [RW 27] Parity mask register #0 read/write */
+#define UCM_REG_UCM_PRTY_MASK 0xe01e4
+/* [R 27] Parity register #0 read */
+#define UCM_REG_UCM_PRTY_STS 0xe01d8
+/* [RC 27] Parity register #0 read clear */
+#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define UCM_REG_UQM_INIT_CRD 0xe0220
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the SDM interface is detected.
+ */
+#define UCM_REG_USDM_LENGTH_MIS 0xe0158
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the xsem interface isdetected.
+ */
+#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
+/* [RW 20] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are:[5:0] - message length; 14:6] - message
+ * pointer; 19:15] - next pointer.
+ */
+#define UCM_REG_XX_DESCR_TABLE 0xe0280
+#define UCM_REG_XX_DESCR_TABLE_SIZE 27
+/* [R 6] Use to read the XX protection Free counter. */
+#define UCM_REG_XX_FREE 0xe016c
+#define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1 << 10)
+#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1 << 28)
+#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1 << 15)
+#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1 << 24)
+#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1 << 5)
+#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1 << 8)
+#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1 << 4)
+#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1 << 1)
+#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1 << 13)
+#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1 << 0)
+#define UMAC_REG_COMMAND_CONFIG 0x8
+/* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE
+ * state from LPI state when it receives packet for transmission. The
+ * decrement unit is 1 micro-second.
+ */
+#define UMAC_REG_EEE_WAKE_TIMER 0x6c
+/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
+ * to bit 17 of the MAC address etc.
+ */
+#define UMAC_REG_MAC_ADDR0 0xc
+/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
+ * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved.
+ */
+#define UMAC_REG_MAC_ADDR1 0x10
+/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
+ * logic to check frames.
+ */
+#define UMAC_REG_MAXFR 0x14
+#define UMAC_REG_UMAC_EEE_CTRL 0x64
+#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1 << 3)
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
+/* [R 1] parser fifo empty in sdm_sync block */
+#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
+/* [RW 32] Interrupt mask register #0 read/write */
+#define USDM_REG_USDM_INT_MASK_0 0xc42a0
+#define USDM_REG_USDM_INT_MASK_1 0xc42b0
+/* [R 32] Interrupt register #0 read */
+#define USDM_REG_USDM_INT_STS_0 0xc4294
+#define USDM_REG_USDM_INT_STS_1 0xc42a4
+/* [RC 32] Interrupt register #0 read clear */
+#define USDM_REG_USDM_INT_STS_CLR_0 0xc4298
+#define USDM_REG_USDM_INT_STS_CLR_1 0xc42a8
+/* [RW 11] Parity mask register #0 read/write */
+#define USDM_REG_USDM_PRTY_MASK 0xc42c0
+/* [R 11] Parity register #0 read */
+#define USDM_REG_USDM_PRTY_STS 0xc42b4
+/* [RC 11] Parity register #0 read clear */
+#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each
+ * SEM_FAST register offset.
+ */
+#define USEM_REG_FAST_MEMORY 0x320000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define USEM_REG_INT_TABLE 0x300400
+/* [WB 128] Debug only. Passive buffer memory */
+#define USEM_REG_PASSIVE_BUFFER 0x302000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define USEM_REG_PRAM 0x340000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define USEM_REG_USEM_INT_MASK_0 0x300110
+#define USEM_REG_USEM_INT_MASK_1 0x300120
+/* [R 32] Interrupt register #0 read */
+#define USEM_REG_USEM_INT_STS_0 0x300104
+#define USEM_REG_USEM_INT_STS_1 0x300114
+/* [RC 32] Interrupt register #0 read clear */
+#define USEM_REG_USEM_INT_STS_CLR_0 0x300108
+#define USEM_REG_USEM_INT_STS_CLR_1 0x300118
+/* [RW 32] Parity mask register #0 read/write */
+#define USEM_REG_USEM_PRTY_MASK_0 0x300130
+#define USEM_REG_USEM_PRTY_MASK_1 0x300140
+/* [R 32] Parity register #0 read */
+#define USEM_REG_USEM_PRTY_STS_0 0x300124
+#define USEM_REG_USEM_PRTY_STS_1 0x300134
+/* [RC 32] Parity register #0 read clear */
+#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
+#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
+ */
+#define USEM_REG_VFPF_ERR_NUM 0x300380
+#define VFC_MEMORIES_RST_REG_CAM_RST (0x1 << 0)
+#define VFC_MEMORIES_RST_REG_RAM_RST (0x1 << 1)
+#define VFC_REG_MEMORIES_RST 0x1943c
+/* [RW 1] Interrupt mask register #0 read/write */
+#define VFC_REG_VFC_INT_MASK 0x194f0
+/* [R 1] Interrupt register #0 read */
+#define VFC_REG_VFC_INT_STS 0x194fc
+/* [RC 1] Interrupt register #0 read clear */
+#define VFC_REG_VFC_INT_STS_CLR 0x194f8
+/* [RW 1] Parity mask register #0 read/write */
+#define VFC_REG_VFC_PRTY_MASK 0x194e0
+/* [R 1] Parity register #0 read */
+#define VFC_REG_VFC_PRTY_STS 0x194ec
+/* [RC 1] Parity register #0 read clear */
+#define VFC_REG_VFC_PRTY_STS_CLR 0x194e8
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define XCM_REG_CAM_OCCUP 0x20244
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define XCM_REG_CFC_INIT_CRD 0x20404
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the csem interface.
+ */
+#define XCM_REG_CSEM_LENGTH_MIS 0x20228
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the dorq interface.
+ */
+#define XCM_REG_DORQ_LENGTH_MIS 0x20230
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define XCM_REG_FIC0_INIT_CRD 0x2040c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define XCM_REG_FIC1_INIT_CRD 0x20410
+#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the nig0 interface.
+ */
+#define XCM_REG_NIG0_LENGTH_MIS 0x20238
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the nig1 interface.
+ */
+#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the pbf interface.
+ */
+#define XCM_REG_PBF_LENGTH_MIS 0x20234
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the STORM interface.
+ */
+#define XCM_REG_STORM_LENGTH_MIS 0x2021c
+/* [RW 4] Timers output initial credit. Max credit available - 15.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 4 at start-up.
+ */
+#define XCM_REG_TM_INIT_CRD 0x2041c
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the tsem interface.
+ */
+#define XCM_REG_TSEM_LENGTH_MIS 0x20224
+/* [RC 1] Message length mismatch (relative to last indication) at the usem
+ * interface.
+ */
+#define XCM_REG_USEM_LENGTH_MIS 0x2022c
+#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
+#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
+/* [RW 14] Interrupt mask register #0 read/write */
+#define XCM_REG_XCM_INT_MASK 0x202b4
+/* [R 14] Interrupt register #0 read */
+#define XCM_REG_XCM_INT_STS 0x202a8
+/* [RC 14] Interrupt register #0 read clear */
+#define XCM_REG_XCM_INT_STS_CLR 0x202ac
+/* [RW 30] Parity mask register #0 read/write */
+#define XCM_REG_XCM_PRTY_MASK 0x202c4
+/* [R 30] Parity register #0 read */
+#define XCM_REG_XCM_PRTY_STS 0x202b8
+/* [RC 30] Parity register #0 read clear */
+#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define XCM_REG_XQM_INIT_CRD 0x20420
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the SDM interface.
+ */
+#define XCM_REG_XSDM_LENGTH_MIS 0x20220
+/* [RW 17] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - message length; 11:6] - message
+ * pointer; 16:12] - next pointer.
+ */
+#define XCM_REG_XX_DESCR_TABLE 0x20480
+#define XCM_REG_XX_DESCR_TABLE_SIZE 32
+/* [R 6] Used to read the XX protection Free counter. */
+#define XCM_REG_XX_FREE 0x20240
+#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1 << 0)
+#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1 << 1)
+#define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1 << 2)
+#define XMAC_CTRL_REG_RX_EN (0x1 << 1)
+#define XMAC_CTRL_REG_SOFT_RESET (0x1 << 6)
+#define XMAC_CTRL_REG_TX_EN (0x1 << 0)
+#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1 << 7)
+#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1 << 18)
+#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1 << 17)
+#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1 << 1)
+#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1 << 0)
+#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1 << 3)
+#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1 << 4)
+#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1 << 5)
+#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
+#define XMAC_REG_CTRL 0
+/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
+ * packets transmitted by the MAC
+ */
+#define XMAC_REG_CTRL_SA_HI 0x2c
+/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
+ * packets transmitted by the MAC
+ */
+#define XMAC_REG_CTRL_SA_LO 0x28
+#define XMAC_REG_EEE_CTRL 0xd8
+#define XMAC_REG_EEE_TIMERS_HI 0xe4
+#define XMAC_REG_PAUSE_CTRL 0x68
+#define XMAC_REG_PFC_CTRL 0x70
+#define XMAC_REG_PFC_CTRL_HI 0x74
+#define XMAC_REG_RX_LSS_CTRL 0x50
+#define XMAC_REG_RX_LSS_STATUS 0x58
+/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
+ * CRC in strip mode
+ */
+#define XMAC_REG_RX_MAX_SIZE 0x40
+#define XMAC_REG_TX_CTRL 0x20
+#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1 << 0)
+#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1 << 1)
+/* [W 17] Generate an operation after completion; bit-16 is
+ * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
+ * bits 4:0 are the T124Param[4:0]
+ */
+#define XSDM_REG_OPERATION_GEN 0x1664c4
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
+#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
+/* [R 32] Interrupt register #0 read */
+#define XSDM_REG_XSDM_INT_STS_0 0x166290
+#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
+/* [RC 32] Interrupt register #0 read clear */
+#define XSDM_REG_XSDM_INT_STS_CLR_0 0x166294
+#define XSDM_REG_XSDM_INT_STS_CLR_1 0x1662a4
+/* [RW 11] Parity mask register #0 read/write */
+#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
+/* [R 11] Parity register #0 read */
+#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
+/* [RC 11] Parity register #0 read clear */
+#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each
+ * SEM_FAST register offset.
+ */
+#define XSEM_REG_FAST_MEMORY 0x2a0000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define XSEM_REG_INT_TABLE 0x280400
+/* [WB 128] Debug only. Passive buffer memory */
+#define XSEM_REG_PASSIVE_BUFFER 0x282000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define XSEM_REG_PRAM 0x2c0000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
+ */
+#define XSEM_REG_VFPF_ERR_NUM 0x280380
+/* [RW 32] Interrupt mask register #0 read/write */
+#define XSEM_REG_XSEM_INT_MASK_0 0x280110
+#define XSEM_REG_XSEM_INT_MASK_1 0x280120
+/* [R 32] Interrupt register #0 read */
+#define XSEM_REG_XSEM_INT_STS_0 0x280104
+#define XSEM_REG_XSEM_INT_STS_1 0x280114
+/* [RC 32] Interrupt register #0 read clear */
+#define XSEM_REG_XSEM_INT_STS_CLR_0 0x280108
+#define XSEM_REG_XSEM_INT_STS_CLR_1 0x280118
+/* [RW 32] Parity mask register #0 read/write */
+#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
+#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
+/* [R 32] Parity register #0 read */
+#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
+#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
+/* [RC 32] Parity register #0 read clear */
+#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
+#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
+#define MCPR_ACCESS_LOCK_LOCK (1L << 31)
+#define MCPR_IMC_COMMAND_ENABLE (1L << 31)
+#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
+#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
+#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
+#define MCPR_NVM_ACCESS_ENABLE_EN (1L << 0)
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L << 1)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL << 0)
+#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L << 0)
+#define MCPR_NVM_COMMAND_DOIT (1L << 4)
+#define MCPR_NVM_COMMAND_DONE (1L << 3)
+#define MCPR_NVM_COMMAND_FIRST (1L << 7)
+#define MCPR_NVM_COMMAND_LAST (1L << 8)
+#define MCPR_NVM_COMMAND_WR (1L << 5)
+#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L << 9)
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L << 5)
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L << 1)
+#define BIGMAC_REGISTER_BMAC_CONTROL (0x00 << 3)
+#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01 << 3)
+#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05 << 3)
+#define BIGMAC_REGISTER_RX_CONTROL (0x21 << 3)
+#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46 << 3)
+#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43 << 3)
+#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23 << 3)
+#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26 << 3)
+#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42 << 3)
+#define BIGMAC_REGISTER_TX_CONTROL (0x07 << 3)
+#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09 << 3)
+#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A << 3)
+#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08 << 3)
+#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20 << 3)
+#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C << 3)
+#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00 << 3)
+#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01 << 3)
+#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05 << 3)
+#define BIGMAC2_REGISTER_PFC_CONTROL (0x06 << 3)
+#define BIGMAC2_REGISTER_RX_CONTROL (0x3A << 3)
+#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62 << 3)
+#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E << 3)
+#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C << 3)
+#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40 << 3)
+#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f << 3)
+#define BIGMAC2_REGISTER_TX_CONTROL (0x1C << 3)
+#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E << 3)
+#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20 << 3)
+#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D << 3)
+#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39 << 3)
+#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22 << 3)
+#define EMAC_LED_1000MB_OVERRIDE (1L << 1)
+#define EMAC_LED_100MB_OVERRIDE (1L << 2)
+#define EMAC_LED_10MB_OVERRIDE (1L << 3)
+#define EMAC_LED_OVERRIDE (1L << 0)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L << 26)
+#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L << 26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L << 26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L << 26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L << 26)
+#define EMAC_MDIO_COMM_DATA (0xffffL << 0)
+#define EMAC_MDIO_COMM_START_BUSY (1L << 29)
+#define EMAC_MDIO_MODE_AUTO_POLL (1L << 4)
+#define EMAC_MDIO_MODE_CLAUSE_45 (1L << 31)
+#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL << 16)
+#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
+#define EMAC_MDIO_STATUS_10MB (1L << 1)
+#define EMAC_MODE_25G_MODE (1L << 5)
+#define EMAC_MODE_HALF_DUPLEX (1L << 1)
+#define EMAC_MODE_PORT_GMII (2L << 2)
+#define EMAC_MODE_PORT_MII (1L << 2)
+#define EMAC_MODE_PORT_MII_10M (3L << 2)
+#define EMAC_MODE_RESET (1L << 0)
+#define EMAC_REG_EMAC_LED 0xc
+#define EMAC_REG_EMAC_MAC_MATCH 0x10
+#define EMAC_REG_EMAC_MDIO_COMM 0xac
+#define EMAC_REG_EMAC_MDIO_MODE 0xb4
+#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
+#define EMAC_REG_EMAC_MODE 0x0
+#define EMAC_REG_EMAC_RX_MODE 0xc8
+#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
+#define EMAC_REG_EMAC_RX_STAT_AC 0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_TX_MODE 0xbc
+#define EMAC_REG_EMAC_TX_STAT_AC 0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_REG_RX_PFC_MODE 0x320
+#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L << 2)
+#define EMAC_REG_RX_PFC_MODE_RX_EN (1L << 1)
+#define EMAC_REG_RX_PFC_MODE_TX_EN (1L << 0)
+#define EMAC_REG_RX_PFC_PARAM 0x324
+#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
+#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff << 0)
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff << 0)
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff << 0)
+#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
+#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff << 0)
+#define EMAC_RX_MODE_FLOW_EN (1L << 2)
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L << 3)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L << 10)
+#define EMAC_RX_MODE_PROMISCUOUS (1L << 8)
+#define EMAC_RX_MODE_RESET (1L << 0)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L << 31)
+#define EMAC_TX_MODE_EXT_PAUSE_EN (1L << 3)
+#define EMAC_TX_MODE_FLOW_EN (1L << 4)
+#define EMAC_TX_MODE_RESET (1L << 0)
+#define MISC_REGISTERS_GPIO_0 0
+#define MISC_REGISTERS_GPIO_1 1
+#define MISC_REGISTERS_GPIO_2 2
+#define MISC_REGISTERS_GPIO_3 3
+#define MISC_REGISTERS_GPIO_CLR_POS 16
+#define MISC_REGISTERS_GPIO_FLOAT (0xffL << 24)
+#define MISC_REGISTERS_GPIO_FLOAT_POS 24
+#define MISC_REGISTERS_GPIO_HIGH 1
+#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
+#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
+#define MISC_REGISTERS_GPIO_INT_SET_POS 16
+#define MISC_REGISTERS_GPIO_LOW 0
+#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
+#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
+#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
+#define MISC_REGISTERS_GPIO_SET_POS 8
+#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
+#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1 << 0)
+#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1 << 19)
+#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1 << 29)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1 << 26)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1 << 27)
+#define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1 << 17)
+#define MISC_REGISTERS_RESET_REG_1_SET 0x584
+#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
+#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1 << 24)
+#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1 << 25)
+#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1 << 19)
+#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1 << 17)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1 << 0)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1 << 1)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1 << 2)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1 << 14)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1 << 3)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1 << 15)
+#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1 << 4)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1 << 6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1 << 8)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1 << 7)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1 << 5)
+#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1 << 11)
+#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1 << 13)
+#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR (0x1 << 16)
+#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1 << 9)
+#define MISC_REGISTERS_RESET_REG_2_SET 0x594
+#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1 << 20)
+#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1 << 21)
+#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1 << 22)
+#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1 << 23)
+#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1 << 1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1 << 2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1 << 3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1 << 0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1 << 5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1 << 6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1 << 7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1 << 4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1 << 8)
+#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
+#define MISC_SPIO_CLR_POS 16
+#define MISC_SPIO_FLOAT (0xffL << 24)
+#define MISC_SPIO_FLOAT_POS 24
+#define MISC_SPIO_INPUT_HI_Z 2
+#define MISC_SPIO_INT_OLD_SET_POS 16
+#define MISC_SPIO_OUTPUT_HIGH 1
+#define MISC_SPIO_OUTPUT_LOW 0
+#define MISC_SPIO_SET_POS 8
+#define MISC_SPIO_SPIO4 0x10
+#define MISC_SPIO_SPIO5 0x20
+#define HW_LOCK_MAX_RESOURCE_VALUE 31
+#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13
+#define HW_LOCK_RESOURCE_DRV_FLAGS 10
+#define HW_LOCK_RESOURCE_GPIO 1
+#define HW_LOCK_RESOURCE_MDIO 0
+#define HW_LOCK_RESOURCE_NVRAM 12
+#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
+#define HW_LOCK_RESOURCE_RECOVERY_REG 11
+#define HW_LOCK_RESOURCE_RESET 5
+#define HW_LOCK_RESOURCE_SPIO 2
+#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1 << 4)
+#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1 << 5)
+#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1 << 19)
+#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1 << 18)
+#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1 << 31)
+#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1 << 30)
+#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1 << 9)
+#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1 << 8)
+#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1 << 7)
+#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1 << 6)
+#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1 << 29)
+#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1 << 28)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1 << 1)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1 << 0)
+#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1 << 18)
+#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1 << 11)
+#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1 << 10)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1 << 13)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1 << 12)
+#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1 << 2)
+#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1 << 12)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1 << 28)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1 << 31)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1 << 29)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1 << 30)
+#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1 << 15)
+#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1 << 14)
+#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1 << 14)
+#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1 << 20)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1 << 31)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1 << 30)
+#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1 << 0)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1 << 2)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1 << 3)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1 << 5)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1 << 4)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1 << 3)
+#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1 << 2)
+#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1 << 3)
+#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1 << 2)
+#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1 << 22)
+#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1 << 15)
+#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1 << 27)
+#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1 << 26)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1 << 5)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1 << 4)
+#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1 << 25)
+#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1 << 24)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1 << 29)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1 << 28)
+#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1 << 23)
+#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1 << 22)
+#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1 << 27)
+#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1 << 26)
+#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1 << 21)
+#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1 << 20)
+#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1 << 25)
+#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1 << 24)
+#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1 << 16)
+#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1 << 9)
+#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1 << 8)
+#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1 << 7)
+#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1 << 6)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1 << 11)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1 << 10)
#define RESERVED_GENERAL_ATTENTION_BIT_0 0
#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
@@ -2155,7 +4467,8 @@
/* Used For Error Recovery: changing this will require more \
changes in code that assume
- * error recovery uses general attn bit20 ! */
+ * error recovery uses general attn bit20 !
+ */
#define ERROR_RECOVERY_ATTENTION_BIT \
RESERVED_GENERAL_ATTENTION_BIT_20
#define RESERVED_ATTENTION_BIT \
@@ -2175,8 +4488,6 @@
#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
#define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32))
-
-
/*
* This file defines GRC base address for every block.
* This file is included by chipsim, asm microcode and cpp microcode.
@@ -2706,7 +5017,7 @@
#define ME_REG_VF_VALID (1<<8)
#define ME_REG_VF_NUM_SHIFT 9
#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
-#define VF_ID(x) ((x & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT)
+#define VF_ID(x) 0 /* TODO: remove def */
#define ME_REG_VF_ERR (0x1<<3)
#define ME_REG_ABS_PF_NUM_SHIFT 16
#define ME_REG_ABS_PF_NUM \
@@ -2819,6 +5130,20 @@
#define PCI_MSIX_TABLE_ENABLE_MASK 0x8000
+#if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID))
+#define PCI_CAP_LIST_ID_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT))
+#define PCI_CAP_LIST_NEXT_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_STATUS))
+#define PCI_STATUS_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST))
+#define PCI_STATUS_CAP_LIST_DEF
+#endif
+
+
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
@@ -3263,6 +5588,9 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
+#define MDIO_AN_REG_848xx_ID_MSB 0xffe2
+#define BNX2X84858_PHY_ID 0x600d
+#define MDIO_AN_REG_848xx_ID_LSB 0xffe3
#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
@@ -3271,6 +5599,7 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
+#define MDIO_AN_REG_8481_INTERRUPT_MASK 0xfffb
#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
/* BNX2X84823 only */
@@ -3299,6 +5628,8 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
+/* BNX2X84858 only */
+#define MDIO_PMA_REG_84858_ALLOW_GPHY_ACT 0x8000
/* BNX2X84833 only */
#define MDIO_84833_TOP_CFG_FW_REV 0x400f
@@ -3306,32 +5637,32 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
#define MDIO_84833_SUPER_ISOLATE 0x8000
-/* These are mailbox register set used by 84833. */
-#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
-#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
-#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
-#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
-#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
-#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
-#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
-#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
-#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
-#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
-#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
-#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
-#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
-#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
-#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
-#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
-#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
-#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
-
-/* Mailbox command set used by 84833. */
-#define PHY84833_CMD_SET_PAIR_SWAP 0x8001
-#define PHY84833_CMD_GET_EEE_MODE 0x8008
-#define PHY84833_CMD_SET_EEE_MODE 0x8009
-#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
-/* Mailbox status set used by 84833. */
+/* These are mailbox register set used by 84833/84858. */
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
+#define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
+#define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
+#define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
+#define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
+#define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
+#define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
+#define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
+
+/* Mailbox command set used by 84833/84858 */
+#define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
+#define PHY848xx_CMD_GET_EEE_MODE 0x8008
+#define PHY848xx_CMD_SET_EEE_MODE 0x8009
+#define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031
+/* Mailbox status set used by 84833 only */
#define PHY84833_STATUS_CMD_RECEIVED 0x0001
#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
@@ -3341,6 +5672,17 @@ Theotherbitsarereservedandshouldbezero*/
#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
+/* Mailbox Process */
+#define PHY84833_MB_PROCESS1 1
+#define PHY84833_MB_PROCESS2 2
+#define PHY84833_MB_PROCESS3 3
+
+/* Mailbox status set used by 84858 only */
+#define PHY84858_STATUS_CMD_RECEIVED 0x0001
+#define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
+#define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
+#define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
+#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
/* Warpcore clause 45 addressing */
@@ -3367,6 +5709,8 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
@@ -3382,7 +5726,9 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
+#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
+#define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
#define MDIO_WC_REG_XGXS_STATUS3 0x8129
#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
@@ -3432,7 +5778,10 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
+#define AUTODET_EN (1 << 4)
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
+#define EN_PARALLEL_DET 1
+#define FILTER_FORCE_LINK (1 << 2)
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
@@ -3501,10 +5850,15 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_REG_GPHY_CL45_REG_READ 0xc000
#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
+#define MDIO_REG_GPHY_BASET_EXT_CTRL 0x10
+#define MDIO_REG_GPHY_TX_HIGH_LATENCY 0x1
#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
#define MDIO_REG_GPHY_EXP_ACCESS 0x17
#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
+#define MDIO_REG_GPHY_SHADOW_ACCESS 0x18
+#define MDIO_REG_GPHY_SHADOW_AUX_CTRL (0x0)
+#define MDIO_REG_GPHY_SHADOW_MISC_CTRL (0x7)
#define MDIO_REG_GPHY_AUX_STATUS 0x19
#define MDIO_REG_INTR_STATUS 0x1a
#define MDIO_REG_INTR_MASK 0x1b
@@ -3516,7 +5870,6 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
-
#define IGU_FUNC_BASE 0x0400
#define IGU_ADDR_MSIX 0x0000
@@ -3585,7 +5938,7 @@ Theotherbitsarereservedandshouldbezero*/
#define IGU_SEG_IDX_ATTN 2
#define IGU_SEG_IDX_DEFAULT 1
-/* Fields of IGU PF CONFIGRATION REGISTER */
+/* Fields of IGU PF CONFIGURATION REGISTER */
#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
@@ -3593,7 +5946,7 @@ Theotherbitsarereservedandshouldbezero*/
#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
-/* Fields of IGU VF CONFIGRATION REGISTER */
+/* Fields of IGU VF CONFIGURATION REGISTER */
#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v2 2/4] net/bnx2x: update HSI code
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (7 preceding siblings ...)
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 1/4] net/bnx2x: update and reorganize HW registers Rasesh Mody
@ 2019-09-19 21:11 ` Rasesh Mody
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 3/4] net/bnx2x: update to latest FW 7.13.11 Rasesh Mody
` (5 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-19 21:11 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, jerinj, ferruh.yigit, GR-Everest-DPDK-Dev
Update hardware software common base driver code in preparation to
update the firmware to version 7.13.11.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/bnx2x/bnx2x.c | 19 +-
drivers/net/bnx2x/bnx2x.h | 23 +-
drivers/net/bnx2x/bnx2x_osal.h | 27 +
drivers/net/bnx2x/bnx2x_rxtx.c | 10 +-
drivers/net/bnx2x/ecore_hsi.h | 3508 ++++++++++++++++++--------------
drivers/net/bnx2x/ecore_sp.c | 11 +-
6 files changed, 1991 insertions(+), 1607 deletions(-)
create mode 100644 drivers/net/bnx2x/bnx2x_osal.h
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index d552f50e2..7a76c308a 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -2182,8 +2182,10 @@ int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
- tx_start_bd->addr =
- rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
+ tx_start_bd->addr_lo =
+ rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
+ tx_start_bd->addr_hi =
+ rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
tx_start_bd->general_data =
@@ -5015,13 +5017,13 @@ static void
bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
- union ustorm_eth_rx_producers rx_prods;
+ struct ustorm_eth_rx_producers rx_prods = { 0 };
uint32_t i;
/* update producers */
- rx_prods.prod.bd_prod = rx_bd_prod;
- rx_prods.prod.cqe_prod = rx_cq_prod;
- rx_prods.prod.reserved = 0;
+ rx_prods.bd_prod = rx_bd_prod;
+ rx_prods.cqe_prod = rx_cq_prod;
+ rx_prods.reserved = 0;
/*
* Make sure that the BD and SGE data is updated before updating the
@@ -5034,9 +5036,8 @@ bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
wmb();
for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
- REG_WR(sc,
- (fp->ustorm_rx_prods_offset + (i * 4)),
- rx_prods.raw_data[i]);
+ REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
+ ((uint32_t *)&rx_prods)[i]);
}
wmb(); /* keep prod updates ordered */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 1ea8b55c9..054d95424 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -19,18 +19,7 @@
#include <rte_bus_pci.h>
#include <rte_io.h>
-#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
-#ifndef __LITTLE_ENDIAN
-#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
-#endif
-#undef __BIG_ENDIAN
-#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
-#ifndef __BIG_ENDIAN
-#define __BIG_ENDIAN RTE_BIG_ENDIAN
-#endif
-#undef __LITTLE_ENDIAN
-#endif
-
+#include "bnx2x_osal.h"
#include "bnx2x_ethdev.h"
#include "ecore_mfw_req.h"
#include "ecore_fw_defs.h"
@@ -1911,16 +1900,18 @@ bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
{
uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
COMMAND_REG_INT_ACK);
- union igu_ack_register igu_ack;
+ struct igu_ack_register igu_ack;
+ uint32_t *val = NULL;
- igu_ack.sb.status_block_index = index;
- igu_ack.sb.sb_id_and_flags =
+ igu_ack.status_block_index = index;
+ igu_ack.sb_id_and_flags =
((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
(storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
- REG_WR(sc, hc_addr, igu_ack.raw_data);
+ val = (uint32_t *)&igu_ack;
+ REG_WR(sc, hc_addr, *val);
/* Make sure that ACK is written */
mb();
diff --git a/drivers/net/bnx2x/bnx2x_osal.h b/drivers/net/bnx2x/bnx2x_osal.h
new file mode 100644
index 000000000..b701853e1
--- /dev/null
+++ b/drivers/net/bnx2x/bnx2x_osal.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2019 Cavium Inc.
+ *
+ * All rights reserved.
+ * www.cavium.com
+ */
+
+#ifndef BNX2X_OSAL_H
+#define BNX2X_OSAL_H
+
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
+#endif
+#undef __BIG_ENDIAN
+#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN RTE_BIG_ENDIAN
+#endif
+#undef __LITTLE_ENDIAN
+#endif
+
+#define __le16 uint16_t
+#define __le32 uint32_t
+#define __le64 uint64_t
+
+#endif /* BNX2X_OSAL_H */
diff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c
index e5a2b25b5..ae97dfee3 100644
--- a/drivers/net/bnx2x/bnx2x_rxtx.c
+++ b/drivers/net/bnx2x/bnx2x_rxtx.c
@@ -321,12 +321,14 @@ static inline void
bnx2x_upd_rx_prod_fast(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
- union ustorm_eth_rx_producers rx_prods;
+ struct ustorm_eth_rx_producers rx_prods = { 0 };
+ uint32_t *val = NULL;
- rx_prods.prod.bd_prod = rx_bd_prod;
- rx_prods.prod.cqe_prod = rx_cq_prod;
+ rx_prods.bd_prod = rx_bd_prod;
+ rx_prods.cqe_prod = rx_cq_prod;
- REG_WR(sc, fp->ustorm_rx_prods_offset, rx_prods.raw_data[0]);
+ val = (uint32_t *)&rx_prods;
+ REG_WR(sc, fp->ustorm_rx_prods_offset, val[0]);
}
static uint16_t
diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index 74189eed6..2728deb1d 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -13,29 +13,32 @@
#ifndef ECORE_HSI_H
#define ECORE_HSI_H
-#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
+#include "ecore_fw_defs.h"
+#include "ecore_mfw_req.h"
+#include "bnx2x_osal.h"
+
+#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
struct license_key {
- uint32_t reserved[6];
+ uint32_t reserved[6];
- uint32_t max_iscsi_conn;
-#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
-#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
-#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
-#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
+ uint32_t max_iscsi_conn;
+#define ECORE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
+#define ECORE_MAX_ISCSI_TRGT_CONN_SHIFT 0
+#define ECORE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
+#define ECORE_MAX_ISCSI_INIT_CONN_SHIFT 16
- uint32_t reserved_a;
+ uint32_t reserved_a;
- uint32_t max_fcoe_conn;
-#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
-#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
-#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
-#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
+ uint32_t max_fcoe_conn;
+#define ECORE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
+#define ECORE_MAX_FCOE_TRGT_CONN_SHIFT 0
+#define ECORE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
+#define ECORE_MAX_FCOE_INIT_CONN_SHIFT 16
- uint32_t reserved_b[4];
+ uint32_t reserved_b[4];
};
-typedef struct license_key license_key_t;
/****************************************************************************
@@ -270,6 +273,14 @@ struct shared_hw_cfg { /* NVRAM Offset */
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
+ /* This field extends the mf mode chosen in nvm cfg #73 (as we ran
+ * out of bits)
+ */
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
+
uint32_t ump_nc_si_config; /* 0x120 */
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
@@ -332,6 +343,7 @@ struct shared_hw_cfg { /* NVRAM Offset */
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
+ #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000
};
@@ -499,7 +511,6 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
*/
#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
-
/* Set non-default values for TXFIR in SFP mode. */
#define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
@@ -672,7 +683,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002
- #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
+ #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020
@@ -738,6 +749,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8722 0x00000f00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54616 0x00001000
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84834 0x00001100
+ #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84858 0x00001200
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
@@ -874,6 +886,9 @@ struct shared_feat_cfg { /* NVRAM Offset */
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
/* Act as if the FCoE license is invalid */
#define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000
@@ -958,6 +973,12 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00
+ #define PORT_FEAT_CFG_DCBX_SEL_MASK 0x00003000
+ #define PORT_FEAT_CFG_DCBX_SEL_SHIFT 12
+ #define PORT_FEAT_CFG_DCBX_SEL_CEE 0x00000000
+ #define PORT_FEAT_CFG_DCBX_SEL_IEEE 0x00001000
+ #define PORT_FEAT_CFG_DCBX_SEL_AUTO 0x00002000
+
#define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
#define PORT_FEATURE_EN_SIZE_SHIFT 24
#define PORT_FEATURE_WOL_ENABLED 0x01000000
@@ -1040,14 +1061,24 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000
#define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000
- uint32_t Reserved0; /* 0x460 */
+ /* Secondary MBA configuration,
+ * see mba_config for the fileds defination.
+ */
+ uint32_t mba_config2;
uint32_t mba_vlan_cfg;
#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF
#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
+ #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000
+ #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000
+ #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000
+
+ /* Secondary MBA configuration,
+ * see mba_vlan_cfg for the fileds defination.
+ */
+ uint32_t mba_vlan_cfg2;
- uint32_t Reserved1;
uint32_t smbus_config;
#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
@@ -1088,8 +1119,8 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000
#define PORT_FEATURE_LINK_SPEED_SHIFT 16
#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
- #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
- #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
+ #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000
+ #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000
#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
@@ -1130,7 +1161,7 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
- uint32_t Reserved2[16]; /* 0x488 */
+ uint32_t Reserved2[16]; /* 0x48C */
};
/****************************************************************************
@@ -1241,6 +1272,16 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0
+ /* Sensor interface - Disabled / BSC / In the future - SMBUS */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED \
+ 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000
+
+ /* On Board Sensor Address */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18
/* MFW flavor to be used */
uint32_t mfw_cfg; /* 0x4008 */
@@ -1255,6 +1296,32 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100
+ /* Prevent OCBB feature */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200
+
+ /* Enable DCi support */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400
+
+ /* Reserved bits: 75 */
+
+ /* PLDM support over MCTP */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_MASK 0x00001000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_SHIFT 12
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_ENABLED 0x00001000
+
+ /* Option to Disable embedded LLDP, 0 - Off, 1 - On */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_MASK 0x00002000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_SHIFT 13
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_OFF 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_ON 0x00002000
+
/* Hide DCBX feature in CCM/BACS menus */
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16
@@ -1291,6 +1358,26 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200
+ /* Override PCIE revision ID when enabled the,
+ * revision ID will set to B1=='0x11'
+ */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400
+
+ /* Bypass slicer offset tuning */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800
+ /* Control Revision ID */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000
/* Threshold in celcius for max continuous operation */
uint32_t temperature_report; /* 0x4014 */
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F
@@ -1341,6 +1428,14 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000
+ /* Override Rx signal detect threshold when enabled the threshold
+ * will be set staticaly
+ */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000
+
/* Debug signet rx threshold */
uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007
@@ -1434,6 +1529,31 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16
#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000
#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24
+
+ /* Manufacture kit version */
+ uint32_t manufacture_ver; /* 0x403C */
+
+ /* Manufacture timestamp */
+ uint32_t manufacture_data; /* 0x4040 */
+
+ /* Number of ISCSI/FCOE cfg images */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000
+
+ /* MCP crash dump trigger */
+ uint32_t mcp_crash_dump; /* 0x4044 */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001
+
+ /* MBI version */
+ uint32_t mbi_version; /* 0x4048 */
+
+ /* MBI date */
+ uint32_t mbi_date; /* 0x404C */
};
@@ -1449,6 +1569,7 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
+#define E1_FUNC_MAX 2
#define E1H_FUNC_MAX 8
#define E2_FUNC_MAX 4 /* per path */
@@ -1575,6 +1696,10 @@ struct drv_func_mb {
#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
+ #define DRV_MSG_CODE_OEM_OK 0x00010000
+ #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
/*
* The optic module verification command requires bootcode
@@ -1629,8 +1754,15 @@ struct drv_func_mb {
#define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000
#define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000
+ #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000
+
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
+ #define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000
+
+ #define DRV_MSG_CODE_UPDATE_DRIVER_STATE 0xC2000000
+ #define REQ_BC_VER_4_UPDATE_DRIVER_STATE 0x00070f35
+
uint32_t drv_mb_param;
#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
@@ -1642,6 +1774,22 @@ struct drv_func_mb {
#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
#define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001
+ #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002
+ #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003
+ #define DRV_MSG_CODE_VLAN_TABLE_IMAGE_REQ 0x00000004
+
+ #define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001
+ #define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002
+ #define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003
+ #define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004
+ #define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005
+ #define DRV_MSG_CODE_CONFIG_CHANGE_RST2DFT 0x00000006
+
+ #define DRV_MSG_CODE_DRIVER_STATE_UNKNOWN 0x00000001
+ #define DRV_MSG_CODE_DRIVER_STATE_NOT_LOADED 0x00000002
+ #define DRV_MSG_CODE_DRIVER_STATE_LOADING 0x00000003
+ #define DRV_MSG_CODE_DRIVER_STATE_DISABLED 0x00000004
+ #define DRV_MSG_CODE_DRIVER_STATE_ACTIVE 0x00000005
uint32_t fw_mb_header;
#define FW_MSG_CODE_MASK 0xffff0000
@@ -1708,6 +1856,13 @@ struct drv_func_mb {
#define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000
#define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000
+ #define FW_MSG_CODE_OEM_ACK 0x00010000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000
+
+ #define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000
+
+ #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0xC3000000
+
#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
uint32_t fw_mb_param;
@@ -1745,6 +1900,13 @@ struct drv_func_mb {
#define DRV_STATUS_SET_MF_BW 0x00000004
#define DRV_STATUS_LINK_EVENT 0x00000008
+ #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
+ #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
+ #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
+ #define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040
+
+ #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
+
#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
@@ -1958,7 +2120,7 @@ struct shmem_region { /* SharedMem Offset (size) */
struct shm_dev_info dev_info; /* 0x8 (0x438) */
- license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
+ struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52 * 2 = 0x68) */
/* FW information (for internal FW use) */
uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */
@@ -1976,7 +2138,7 @@ struct shmem_region { /* SharedMem Offset (size) */
struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
#endif /* BMAPI */
-}; /* 57711 = 0x7E4 | 57712 = 0x734 */
+}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
/****************************************************************************
* Shared Memory 2 Region *
@@ -1995,7 +2157,7 @@ struct shmem_region { /* SharedMem Offset (size) */
/****************************************************************************/
struct fw_flr_ack {
uint32_t pf_ack;
- uint32_t vf_ack[1];
+ uint32_t vf_ack;
uint32_t iov_dis_ack;
};
@@ -2134,17 +2296,30 @@ struct dcbx_app_priority_entry {
uint8_t pri_bitmap;
uint8_t appBitfield;
#define DCBX_APP_ENTRY_VALID 0x01
- #define DCBX_APP_ENTRY_SF_MASK 0x30
+ #define DCBX_APP_ENTRY_SF_MASK 0xF0
#define DCBX_APP_ENTRY_SF_SHIFT 4
#define DCBX_APP_SF_ETH_TYPE 0x10
- #define DCBX_APP_SF_PORT 0x20
+ #define DCBX_APP_SF_PORT 0x20 /* TCP */
+ #define DCBX_APP_SF_UDP 0x40 /* UDP */
+ #define DCBX_APP_SF_DEFAULT 0x80
+ #define DCBX_APP_PRI_0 0x01
+ #define DCBX_APP_PRI_1 0x02
+ #define DCBX_APP_PRI_2 0x04
+ #define DCBX_APP_PRI_3 0x08
+ #define DCBX_APP_PRI_4 0x10
+ #define DCBX_APP_PRI_5 0x20
+ #define DCBX_APP_PRI_6 0x40
+ #define DCBX_APP_PRI_7 0x80
#elif defined(__LITTLE_ENDIAN)
uint8_t appBitfield;
#define DCBX_APP_ENTRY_VALID 0x01
- #define DCBX_APP_ENTRY_SF_MASK 0x30
+ #define DCBX_APP_ENTRY_SF_MASK 0xF0
#define DCBX_APP_ENTRY_SF_SHIFT 4
+ #define DCBX_APP_ENTRY_VALID 0x01
#define DCBX_APP_SF_ETH_TYPE 0x10
- #define DCBX_APP_SF_PORT 0x20
+ #define DCBX_APP_SF_PORT 0x20 /* TCP */
+ #define DCBX_APP_SF_UDP 0x40 /* UDP */
+ #define DCBX_APP_SF_DEFAULT 0x80
uint8_t pri_bitmap;
uint16_t app_id;
#endif
@@ -2343,6 +2518,85 @@ struct shmem_lfa {
};
+/*
+ * Used to suppoert NSCI get OS driver version
+ * On driver load the version value will be set
+ * On driver unload driver value of 0x0 will be set
+ */
+struct os_drv_ver {
+ #define DRV_VER_NOT_LOADED 0
+ /*personalites orrder is importent */
+ #define DRV_PERS_ETHERNET 0
+ #define DRV_PERS_ISCSI 1
+ #define DRV_PERS_FCOE 2
+ /*shmem2 struct is constatnt can't add more personalites here*/
+ #define MAX_DRV_PERS 3
+ uint32_t versions[MAX_DRV_PERS];
+};
+
+#define OEM_I2C_UUID_STR_ADDR 0x9f
+#define OEM_I2C_CARD_SKU_STR_ADDR 0x3c
+#define OEM_I2C_CARD_FN_STR_ADDR 0x48
+#define OEM_I2C_CARD_NAME_STR_ADDR 0x10e
+
+#define OEM_I2C_UUID_STR_LEN 16
+#define OEM_I2C_CARD_SKU_STR_LEN 12
+#define OEM_I2C_CARD_FN_STR_LEN 12
+#define OEM_I2C_CARD_NAME_STR_LEN 128
+#define OEM_I2C_CARD_VERSION_STR_LEN 36
+
+struct oem_i2c_data_t {
+ uint32_t size;
+ uint8_t uuid[OEM_I2C_UUID_STR_LEN];
+ uint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN];
+ uint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN];
+ uint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN];
+ uint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN];
+};
+
+enum curr_cfg_method_e {
+ CURR_CFG_MET_NONE = 0, /* default config */
+ CURR_CFG_MET_OS = 1,
+ CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */
+ CURR_CFG_MET_HP_OTHER = 3,
+ CURR_CFG_MET_VC_CLP = 4, /* C-Class SM-CLP */
+ CURR_CFG_MET_HP_CNU = 5, /* Converged Network Utility */
+ CURR_CFG_MET_HP_DCI = 6, /* DCi (BD) changes */
+};
+
+#define FC_NPIV_WWPN_SIZE 8
+#define FC_NPIV_WWNN_SIZE 8
+struct bdn_npiv_settings {
+ uint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE];
+ uint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE];
+};
+
+struct bdn_fc_npiv_cfg {
+ /* hdr used internally by the MFW */
+ uint32_t hdr;
+ uint32_t num_of_npiv;
+};
+
+#define MAX_NUMBER_NPIV 64
+struct bdn_fc_npiv_tbl {
+ struct bdn_fc_npiv_cfg fc_npiv_cfg;
+ struct bdn_npiv_settings settings[MAX_NUMBER_NPIV];
+};
+
+struct mdump_driver_info {
+ uint32_t epoc;
+ uint32_t drv_ver;
+ uint32_t fw_ver;
+
+ uint32_t valid_dump;
+ #define FIRST_DUMP_VALID (1 << 0)
+ #define SECOND_DUMP_VALID (1 << 1)
+
+ uint32_t flags;
+ #define ENABLE_ALL_TRIGGERS (0x7fffffff)
+ #define TRIGGER_MDUMP_ONCE (1 << 31)
+};
+
struct shmem2_region {
uint32_t size; /* 0x0000 */
@@ -2426,18 +2680,18 @@ struct shmem2_region {
uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
- uint32_t swim_base_addr; /* 0x0108 */
- uint32_t swim_funcs;
- uint32_t swim_main_cb;
+ uint32_t swim_base_addr; /* 0x00a8 */
+ uint32_t swim_funcs; /* 0x00ac */
+ uint32_t swim_main_cb; /* 0x00b0 */
/*
* bitmap notifying which VIF profiles stored in nvram are enabled by
* switch
*/
- uint32_t afex_profiles_enabled[2];
+ uint32_t afex_profiles_enabled[2]; /* 0x00b4 */
/* generic flags controlled by the driver */
- uint32_t drv_flags;
+ uint32_t drv_flags; /* 0x00bc */
#define DRV_FLAGS_DCB_CONFIGURED 0x0
#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
#define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
@@ -2459,45 +2713,47 @@ struct shmem2_region {
(_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
/* pointer to extended dev_info shared data copied from nvm image */
- uint32_t extended_dev_info_shared_addr;
- uint32_t ncsi_oem_data_addr;
+ uint32_t extended_dev_info_shared_addr; /* 0x00c0 */
+ uint32_t ncsi_oem_data_addr; /* 0x00c4 */
- uint32_t sensor_data_addr;
- uint32_t buffer_block_addr;
- uint32_t sensor_data_req_update_interval;
- uint32_t temperature_in_half_celsius;
- uint32_t glob_struct_in_host;
+ uint32_t sensor_data_addr; /* 0x00c8 */
+ uint32_t buffer_block_addr; /* 0x00cc */
+ uint32_t sensor_data_req_update_interval; /* 0x00d0 */
+ uint32_t temperature_in_half_celsius; /* 0x00d4 */
+ uint32_t glob_struct_in_host; /* 0x00d8 */
- uint32_t dcbx_neg_res_ext_offset;
+ uint32_t dcbx_neg_res_ext_offset; /* 0x00dc */
#define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
- uint32_t drv_capabilities_flag[E2_FUNC_MAX];
+ uint32_t drv_capabilities_flag[E2_FUNC_MAX]; /* 0x00e0 */
#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
+ #define DRV_FLAGS_MTU_MASK 0xffff0000
+ #define DRV_FLAGS_MTU_SHIFT 16
- uint32_t extended_dev_info_shared_cfg_size;
+ uint32_t extended_dev_info_shared_cfg_size; /* 0x00f0 */
- uint32_t dcbx_en[PORT_MAX];
+ uint32_t dcbx_en[PORT_MAX]; /* 0x00f4 */
/* The offset points to the multi threaded meta structure */
- uint32_t multi_thread_data_offset;
+ uint32_t multi_thread_data_offset; /* 0x00fc */
/* address of DMAable host address holding values from the drivers */
- uint32_t drv_info_host_addr_lo;
- uint32_t drv_info_host_addr_hi;
+ uint32_t drv_info_host_addr_lo; /* 0x0100 */
+ uint32_t drv_info_host_addr_hi; /* 0x0104 */
/* general values written by the MFW (such as current version) */
- uint32_t drv_info_control;
+ uint32_t drv_info_control; /* 0x0108 */
#define DRV_INFO_CONTROL_VER_MASK 0x000000ff
#define DRV_INFO_CONTROL_VER_SHIFT 0
#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
- uint32_t ibft_host_addr; /* initialized by option ROM */
+ uint32_t ibft_host_addr; /* initialized by option ROM */ /* 0x010c */
- struct eee_remote_vals eee_remote_vals[PORT_MAX];
- uint32_t pf_allocation[E2_FUNC_MAX];
+ struct eee_remote_vals eee_remote_vals[PORT_MAX]; /* 0x0110 */
+ uint32_t pf_allocation[E2_FUNC_MAX]; /* 0x0120 */
#define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
#define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0
@@ -2515,13 +2771,13 @@ struct shmem2_region {
* bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
* value. When 1'b1 those bits contains a value times 16 microseconds.
*/
- uint32_t eee_status[PORT_MAX];
+ uint32_t eee_status[PORT_MAX]; /* 0x0130 */
#define SHMEM_EEE_TIMER_MASK 0x0000ffff
#define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
#define SHMEM_EEE_SUPPORTED_SHIFT 16
#define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
#define SHMEM_EEE_100M_ADV (1<<0)
- #define SHMEM_EEE_1G_ADV (1U<<1)
+ #define SHMEM_EEE_1G_ADV (1 << 1)
#define SHMEM_EEE_10G_ADV (1<<2)
#define SHMEM_EEE_ADV_STATUS_SHIFT 20
#define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
@@ -2531,26 +2787,143 @@ struct shmem2_region {
#define SHMEM_EEE_ACTIVE_BIT 0x40000000
#define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
- uint32_t sizeof_port_stats;
+ uint32_t sizeof_port_stats; /* 0x0138 */
/* Link Flap Avoidance */
- uint32_t lfa_host_addr[PORT_MAX];
+ uint32_t lfa_host_addr[PORT_MAX]; /* 0x013c */
/* External PHY temperature in deg C. */
- uint32_t extphy_temps_in_celsius;
+ uint32_t extphy_temps_in_celsius; /* 0x0144 */
#define EXTPHY1_TEMP_MASK 0x0000ffff
#define EXTPHY1_TEMP_SHIFT 0
+ #define ON_BOARD_TEMP_MASK 0xffff0000
+ #define ON_BOARD_TEMP_SHIFT 16
uint32_t ocdata_info_addr; /* Offset 0x148 */
uint32_t drv_func_info_addr; /* Offset 0x14C */
uint32_t drv_func_info_size; /* Offset 0x150 */
uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */
- #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
- #define LINK_ATTR_84858 0x00000002
- #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
- #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
+ #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
+ #define LINK_ATTR_84858 0x00000002
+ #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
+ #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
+ #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
+ #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
+ #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
+
+ uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */
+ uint32_t fcode_ver; /* Offset 0x15c */
+ uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
+ #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */
+ /* driver version for each personality*/
+ struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
+
+ /* Flag to the driver that PF's drv_info_host_addr buffer was read */
+ uint32_t mfw_drv_indication; /* Offset 0x19c */
+
+ /* We use inidcation for each PF (0..3) */
+ #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
+
+ union { /* For various OEMs */ /* Offset 0x1a0 */
+ uint8_t storage_boot_prog[E2_FUNC_MAX];
+ #define STORAGE_BOOT_PROG_MASK 0x000000FF
+ #define STORAGE_BOOT_PROG_NONE 0x00000000
+ #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
+ #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
+ #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
+ #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
+ #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
+ #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
+ #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
+ #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
+ #define STORAGE_BOOT_PROG_COMPLETED 0x00000080
+
+ uint32_t oem_i2c_data_addr;
+ };
+
+ /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
+ /* For PCP values 0-3 use the map lower */
+ /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
+ * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
+ */
+ uint32_t c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */
+
+ /* For PCP values 4-7 use the map upper */
+ /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
+ * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
+ */
+ uint32_t c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */
+
+ /* For PCP default value get the MSB byte of the map default */
+ uint32_t c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */
+
+ /* FC_NPIV table offset in NVRAM */
+ uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */
+
+ /* Shows last method that changed configuration of this device */
+ enum curr_cfg_method_e curr_cfg; /* 0x1dc */
+
+ /* Storm FW version, shold be kept in the format 0xMMmmbbdd:
+ * MM - Major, mm - Minor, bb - Build ,dd - Drop
+ */
+ uint32_t netproc_fw_ver; /* 0x1e0 */
+
+ /* Option ROM SMASH CLP version */
+ uint32_t clp_ver; /* 0x1e4 */
+
+ uint32_t pcie_bus_num; /* 0x1e8 */
- uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
+ uint32_t sriov_switch_mode; /* 0x1ec */
+ #define SRIOV_SWITCH_MODE_NONE 0x0
+ #define SRIOV_SWITCH_MODE_VEB 0x1
+ #define SRIOV_SWITCH_MODE_VEPA 0x2
+
+ uint8_t rsrv2[E2_FUNC_MAX]; /* 0x1f0 */
+
+ uint32_t img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */
+
+ uint32_t mtu_size[E2_FUNC_MAX]; /* 0x1f8 */
+
+ uint32_t os_driver_state[E2_FUNC_MAX]; /* 0x208 */
+ #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */
+ #define OS_DRIVER_STATE_LOADING 1 /* transition state */
+ #define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */
+ #define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */
+
+ /* mini dump driver info */
+ struct mdump_driver_info drv_info; /* 0x218 */
+
+ /* written by mfw, read by driver, eg. feature capability support */
+ uint32_t mfw_flags; /* 0x22c */
+ #define DISABLE_EMBEDDED_LLDP_SUPPORT 0x00000001
+};
+
+#define VLAN_BITMAP_SIZE 512
+#define VLAN_PF_NUM_MAX 8
+
+struct pf_vlan_table {
+ uint16_t pvid;
+ uint8_t pcp;
+ uint8_t rsvd;
+ uint8_t trunk_vlan_bitmap[VLAN_BITMAP_SIZE];
+ uint32_t rsvd1[4];
+};
+
+struct vlan_table_s {
+ uint32_t version;
+ #define VLAN_TABLE_IMAGE_VERSION_1 1
+ uint8_t vlan_mode[NVM_PATH_MAX][PORT_MAX];
+ #define VLAN_MODE_NORMAL 0
+ #define VLAN_MODE_FILTER 1
+ #define VLAN_MODE_QINQ 2
+ struct pf_vlan_table pf_vlans[VLAN_PF_NUM_MAX];
+ uint32_t rsvd2[8];
+};
+
+/* The VLAN table Image is stored in Big Endian format */
+struct nvm_vlan_table_image {
+ struct vlan_table_s vlan_table;
+ uint32_t crc;
};
@@ -3228,31 +3601,29 @@ struct port_info {
#define BNX2X_5710_FW_MAJOR_VERSION 7
-#define BNX2X_5710_FW_MINOR_VERSION 2
-#define BNX2X_5710_FW_REVISION_VERSION 51
+#define BNX2X_5710_FW_MINOR_VERSION 13
+#define BNX2X_5710_FW_REVISION_VERSION 11
#define BNX2X_5710_FW_ENGINEERING_VERSION 0
#define BNX2X_5710_FW_COMPILE_FLAGS 1
/*
- * attention bits $$KEEP_ENDIANNESS$$
+ * attention bits
*/
-struct atten_sp_status_block
-{
- uint32_t attn_bits /* 16 bit of attention signal lines */;
- uint32_t attn_bits_ack /* 16 bit of attention signal ack */;
- uint8_t status_block_id /* status block id */;
- uint8_t reserved0 /* resreved for padding */;
- uint16_t attn_bits_index /* attention bits running index */;
- uint32_t reserved1 /* resreved for padding */;
+struct atten_sp_status_block {
+ __le32 attn_bits;
+ __le32 attn_bits_ack;
+ uint8_t status_block_id;
+ uint8_t reserved0;
+ __le16 attn_bits_index;
+ __le32 reserved1;
};
/*
* The eth aggregative context of Cstorm
*/
-struct cstorm_eth_ag_context
-{
+struct cstorm_eth_ag_context {
uint32_t __reserved0[10];
};
@@ -3260,101 +3631,100 @@ struct cstorm_eth_ag_context
/*
* dmae command structure
*/
-struct dmae_command
-{
+struct dmae_command {
uint32_t opcode;
-#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */
+#define DMAE_COMMAND_SRC (0x1 << 0)
#define DMAE_COMMAND_SRC_SHIFT 0
-#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
+#define DMAE_COMMAND_DST (0x3 << 1)
#define DMAE_COMMAND_DST_SHIFT 1
-#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */
+#define DMAE_COMMAND_C_DST (0x1 << 3)
#define DMAE_COMMAND_C_DST_SHIFT 3
-#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */
+#define DMAE_COMMAND_C_TYPE_ENABLE (0x1 << 4)
#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
-#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1 << 5)
#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
-#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7 << 6)
#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
-#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */
+#define DMAE_COMMAND_ENDIANITY (0x3 << 9)
#define DMAE_COMMAND_ENDIANITY_SHIFT 9
-#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */
+#define DMAE_COMMAND_PORT (0x1 << 11)
#define DMAE_COMMAND_PORT_SHIFT 11
-#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */
+#define DMAE_COMMAND_CRC_RESET (0x1 << 12)
#define DMAE_COMMAND_CRC_RESET_SHIFT 12
-#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */
+#define DMAE_COMMAND_SRC_RESET (0x1 << 13)
#define DMAE_COMMAND_SRC_RESET_SHIFT 13
-#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */
+#define DMAE_COMMAND_DST_RESET (0x1 << 14)
#define DMAE_COMMAND_DST_RESET_SHIFT 14
-#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */
+#define DMAE_COMMAND_E1HVN (0x3 << 15)
#define DMAE_COMMAND_E1HVN_SHIFT 15
-#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */
+#define DMAE_COMMAND_DST_VN (0x3 << 17)
#define DMAE_COMMAND_DST_VN_SHIFT 17
-#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */
+#define DMAE_COMMAND_C_FUNC (0x1 << 19)
#define DMAE_COMMAND_C_FUNC_SHIFT 19
-#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */
+#define DMAE_COMMAND_ERR_POLICY (0x3 << 20)
#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
-#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */
+#define DMAE_COMMAND_RESERVED0 (0x3FF << 22)
#define DMAE_COMMAND_RESERVED0_SHIFT 22
- uint32_t src_addr_lo /* source address low/grc address */;
- uint32_t src_addr_hi /* source address hi */;
- uint32_t dst_addr_lo /* dest address low/grc address */;
- uint32_t dst_addr_hi /* dest address hi */;
+ uint32_t src_addr_lo;
+ uint32_t src_addr_hi;
+ uint32_t dst_addr_lo;
+ uint32_t dst_addr_hi;
#if defined(__BIG_ENDIAN)
uint16_t opcode_iov;
-#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
+#define DMAE_COMMAND_SRC_VFID (0x3F << 0)
#define DMAE_COMMAND_SRC_VFID_SHIFT 0
-#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
+#define DMAE_COMMAND_SRC_VFPF (0x1 << 6)
#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
-#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED1 (0x1 << 7)
#define DMAE_COMMAND_RESERVED1_SHIFT 7
-#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
+#define DMAE_COMMAND_DST_VFID (0x3F << 8)
#define DMAE_COMMAND_DST_VFID_SHIFT 8
-#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
+#define DMAE_COMMAND_DST_VFPF (0x1 << 14)
#define DMAE_COMMAND_DST_VFPF_SHIFT 14
-#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED2 (0x1 << 15)
#define DMAE_COMMAND_RESERVED2_SHIFT 15
- uint16_t len /* copy length */;
+ uint16_t len;
#elif defined(__LITTLE_ENDIAN)
- uint16_t len /* copy length */;
+ uint16_t len;
uint16_t opcode_iov;
-#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
+#define DMAE_COMMAND_SRC_VFID (0x3F << 0)
#define DMAE_COMMAND_SRC_VFID_SHIFT 0
-#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
+#define DMAE_COMMAND_SRC_VFPF (0x1 << 6)
#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
-#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED1 (0x1 << 7)
#define DMAE_COMMAND_RESERVED1_SHIFT 7
-#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
+#define DMAE_COMMAND_DST_VFID (0x3F << 8)
#define DMAE_COMMAND_DST_VFID_SHIFT 8
-#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
+#define DMAE_COMMAND_DST_VFPF (0x1 << 14)
#define DMAE_COMMAND_DST_VFPF_SHIFT 14
-#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED2 (0x1 << 15)
#define DMAE_COMMAND_RESERVED2_SHIFT 15
#endif
- uint32_t comp_addr_lo /* completion address low/grc address */;
- uint32_t comp_addr_hi /* completion address hi */;
- uint32_t comp_val /* value to write to completion address */;
- uint32_t crc32 /* crc32 result */;
- uint32_t crc32_c /* crc32_c result */;
+ uint32_t comp_addr_lo;
+ uint32_t comp_addr_hi;
+ uint32_t comp_val;
+ uint32_t crc32;
+ uint32_t crc32_c;
#if defined(__BIG_ENDIAN)
- uint16_t crc16_c /* crc16_c result */;
- uint16_t crc16 /* crc16 result */;
+ uint16_t crc16_c;
+ uint16_t crc16;
#elif defined(__LITTLE_ENDIAN)
- uint16_t crc16 /* crc16 result */;
- uint16_t crc16_c /* crc16_c result */;
+ uint16_t crc16;
+ uint16_t crc16_c;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3;
- uint16_t crc_t10 /* crc_t10 result */;
+ uint16_t crc_t10;
#elif defined(__LITTLE_ENDIAN)
- uint16_t crc_t10 /* crc_t10 result */;
+ uint16_t crc_t10;
uint16_t reserved3;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t xsum8 /* checksum8 result */;
- uint16_t xsum16 /* checksum16 result */;
+ uint16_t xsum8;
+ uint16_t xsum16;
#elif defined(__LITTLE_ENDIAN)
- uint16_t xsum16 /* checksum16 result */;
- uint16_t xsum8 /* checksum8 result */;
+ uint16_t xsum16;
+ uint16_t xsum8;
#endif
};
@@ -3362,162 +3732,149 @@ struct dmae_command
/*
* common data for all protocols
*/
-struct doorbell_hdr
-{
+struct doorbell_hdr {
uint8_t header;
-#define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */
+#define DOORBELL_HDR_RX (0x1 << 0)
#define DOORBELL_HDR_RX_SHIFT 0
-#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */
+#define DOORBELL_HDR_DB_TYPE (0x1 << 1)
#define DOORBELL_HDR_DB_TYPE_SHIFT 1
-#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */
+#define DOORBELL_HDR_DPM_SIZE (0x3 << 2)
#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
-#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */
+#define DOORBELL_HDR_CONN_TYPE (0xF << 4)
#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
};
/*
* Ethernet doorbell
*/
-struct eth_tx_doorbell
-{
+struct eth_tx_doorbell {
#if defined(__BIG_ENDIAN)
- uint16_t npackets /* number of data bytes that were added in the doorbell */;
+ uint16_t npackets;
uint8_t params;
-#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0)
#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
-#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6)
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
-#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
+#define ETH_TX_DOORBELL_SPARE (0x1 << 7)
#define ETH_TX_DOORBELL_SPARE_SHIFT 7
struct doorbell_hdr hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr hdr;
uint8_t params;
-#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0)
#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
-#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6)
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
-#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
+#define ETH_TX_DOORBELL_SPARE (0x1 << 7)
#define ETH_TX_DOORBELL_SPARE_SHIFT 7
- uint16_t npackets /* number of data bytes that were added in the doorbell */;
+ uint16_t npackets;
#endif
};
/*
- * 3 lines. status block $$KEEP_ENDIANNESS$$
+ * 3 lines. status block
*/
-struct hc_status_block_e1x
-{
- uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */;
- uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
- uint32_t rsrv[11];
+struct hc_status_block_e1x {
+ __le16 index_values[HC_SB_MAX_INDICES_E1X];
+ __le16 running_index[HC_SB_MAX_SM];
+ __le32 rsrv[11];
};
/*
* host status block
*/
-struct host_hc_status_block_e1x
-{
- struct hc_status_block_e1x sb /* fast path indices */;
+struct host_hc_status_block_e1x {
+ struct hc_status_block_e1x sb;
};
/*
- * 3 lines. status block $$KEEP_ENDIANNESS$$
+ * 3 lines. status block
*/
-struct hc_status_block_e2
-{
- uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */;
- uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
- uint32_t reserved[11];
+struct hc_status_block_e2 {
+ __le16 index_values[HC_SB_MAX_INDICES_E2];
+ __le16 running_index[HC_SB_MAX_SM];
+ __le32 reserved[11];
};
/*
* host status block
*/
-struct host_hc_status_block_e2
-{
- struct hc_status_block_e2 sb /* fast path indices */;
+struct host_hc_status_block_e2 {
+ struct hc_status_block_e2 sb;
};
/*
- * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$
+ * 5 lines. slow-path status block
*/
-struct hc_sp_status_block
-{
- uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */;
- uint16_t running_index /* Status Block running index */;
- uint16_t rsrv;
+struct hc_sp_status_block {
+ __le16 index_values[HC_SP_SB_MAX_INDICES];
+ __le16 running_index;
+ __le16 rsrv;
uint32_t rsrv1;
};
/*
* host status block
*/
-struct host_sp_status_block
-{
- struct atten_sp_status_block atten_status_block /* attention bits section */;
- struct hc_sp_status_block sp_sb /* slow path indices */;
+struct host_sp_status_block {
+ struct atten_sp_status_block atten_status_block;
+ struct hc_sp_status_block sp_sb;
};
/*
* IGU driver acknowledgment register
*/
-union igu_ack_register
-{
- struct {
+struct igu_ack_register {
#if defined(__BIG_ENDIAN)
- uint16_t sb_id_and_flags;
-#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
+ uint16_t sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0)
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
-#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_ACK_REGISTER_STORM_ID (0x7 << 5)
#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
-#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8)
#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
-#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9)
#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
-#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
+#define IGU_ACK_REGISTER_RESERVED (0x1F << 11)
#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
- uint16_t status_block_index /* status block index acknowledgement */;
+ uint16_t status_block_index;
#elif defined(__LITTLE_ENDIAN)
- uint16_t status_block_index /* status block index acknowledgement */;
- uint16_t sb_id_and_flags;
-#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
+ uint16_t status_block_index;
+ uint16_t sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0)
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
-#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_ACK_REGISTER_STORM_ID (0x7 << 5)
#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
-#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8)
#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
-#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9)
#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
-#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
+#define IGU_ACK_REGISTER_RESERVED (0x1F << 11)
#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
#endif
- } sb;
- uint32_t raw_data;
};
/*
* IGU driver acknowledgement register
*/
-struct igu_backward_compatible
-{
+struct igu_backward_compatible {
uint32_t sb_id_and_flags;
-#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF << 0)
#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
-#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F << 16)
#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
-#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7 << 21)
#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
-#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1 << 24)
#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
-#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3 << 25)
#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
-#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F << 27)
#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
uint32_t reserved_2;
};
@@ -3526,26 +3883,25 @@ struct igu_backward_compatible
/*
* IGU driver acknowledgement register
*/
-struct igu_regular
-{
+struct igu_regular {
uint32_t sb_id_and_flags;
-#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_SB_INDEX (0xFFFFF << 0)
#define IGU_REGULAR_SB_INDEX_SHIFT 0
-#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_RESERVED0 (0x1 << 20)
#define IGU_REGULAR_RESERVED0_SHIFT 20
-#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */
+#define IGU_REGULAR_SEGMENT_ACCESS (0x7 << 21)
#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
-#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_BUPDATE (0x1 << 24)
#define IGU_REGULAR_BUPDATE_SHIFT 24
-#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */
+#define IGU_REGULAR_ENABLE_INT (0x3 << 25)
#define IGU_REGULAR_ENABLE_INT_SHIFT 25
-#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_RESERVED_1 (0x1 << 27)
#define IGU_REGULAR_RESERVED_1_SHIFT 27
-#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_CLEANUP_TYPE (0x3 << 28)
#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
-#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_CLEANUP_SET (0x1 << 30)
#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
-#define IGU_REGULAR_BCLEANUP (0x1U<<31) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_BCLEANUP (0x1 << 31)
#define IGU_REGULAR_BCLEANUP_SHIFT 31
uint32_t reserved_2;
};
@@ -3553,8 +3909,7 @@ struct igu_regular
/*
* IGU driver acknowledgement register
*/
-union igu_consprod_reg
-{
+union igu_consprod_reg {
struct igu_regular regular;
struct igu_backward_compatible backward_compatible;
};
@@ -3563,8 +3918,7 @@ union igu_consprod_reg
/*
* Igu control commands
*/
-enum igu_ctrl_cmd
-{
+enum igu_ctrl_cmd {
IGU_CTRL_CMD_TYPE_RD,
IGU_CTRL_CMD_TYPE_WR,
MAX_IGU_CTRL_CMD};
@@ -3573,18 +3927,17 @@ enum igu_ctrl_cmd
/*
* Control register for the IGU command register
*/
-struct igu_ctrl_reg
-{
+struct igu_ctrl_reg {
uint32_t ctrl_data;
-#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */
+#define IGU_CTRL_REG_ADDRESS (0xFFF << 0)
#define IGU_CTRL_REG_ADDRESS_SHIFT 0
-#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */
+#define IGU_CTRL_REG_FID (0x7F << 12)
#define IGU_CTRL_REG_FID_SHIFT 12
-#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */
+#define IGU_CTRL_REG_RESERVED (0x1 << 19)
#define IGU_CTRL_REG_RESERVED_SHIFT 19
-#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */
+#define IGU_CTRL_REG_TYPE (0x1 << 20)
#define IGU_CTRL_REG_TYPE_SHIFT 20
-#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */
+#define IGU_CTRL_REG_UNUSED (0x7FF << 21)
#define IGU_CTRL_REG_UNUSED_SHIFT 21
};
@@ -3592,8 +3945,7 @@ struct igu_ctrl_reg
/*
* Igu interrupt command
*/
-enum igu_int_cmd
-{
+enum igu_int_cmd {
IGU_INT_ENABLE,
IGU_INT_DISABLE,
IGU_INT_NOP,
@@ -3604,8 +3956,7 @@ enum igu_int_cmd
/*
* Igu segments
*/
-enum igu_seg_access
-{
+enum igu_seg_access {
IGU_SEG_ACCESS_NORM,
IGU_SEG_ACCESS_DEF,
IGU_SEG_ACCESS_ATTN,
@@ -3615,34 +3966,33 @@ enum igu_seg_access
/*
* Parser parsing flags field
*/
-struct parsing_flags
-{
- uint16_t flags;
-#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */
+struct parsing_flags {
+ __le16 flags;
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1 << 0)
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
-#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */
+#define PARSING_FLAGS_VLAN (0x1 << 1)
#define PARSING_FLAGS_VLAN_SHIFT 1
-#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */
+#define PARSING_FLAGS_EXTRA_VLAN (0x1 << 2)
#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
-#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3 << 3)
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
-#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */
+#define PARSING_FLAGS_IP_OPTIONS (0x1 << 5)
#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
-#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */
+#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1 << 6)
#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
-#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */
+#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3 << 7)
#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
-#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */
+#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1 << 9)
#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
-#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1 << 10)
#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
-#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1 << 11)
#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
-#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */
+#define PARSING_FLAGS_CONNECTION_MATCH (0x1 << 12)
#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
-#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */
+#define PARSING_FLAGS_LLC_SNAP (0x1 << 13)
#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
-#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */
+#define PARSING_FLAGS_RESERVED0 (0x3 << 14)
#define PARSING_FLAGS_RESERVED0_SHIFT 14
};
@@ -3650,8 +4000,7 @@ struct parsing_flags
/*
* Parsing flags for TCP ACK type
*/
-enum prs_flags_ack_type
-{
+enum prs_flags_ack_type {
PRS_FLAG_PUREACK_PIGGY,
PRS_FLAG_PUREACK_PURE,
MAX_PRS_FLAGS_ACK_TYPE};
@@ -3660,8 +4009,7 @@ enum prs_flags_ack_type
/*
* Parsing flags for Ethernet address type
*/
-enum prs_flags_eth_addr_type
-{
+enum prs_flags_eth_addr_type {
PRS_FLAG_ETHTYPE_NON_UNICAST,
PRS_FLAG_ETHTYPE_UNICAST,
MAX_PRS_FLAGS_ETH_ADDR_TYPE};
@@ -3670,8 +4018,7 @@ enum prs_flags_eth_addr_type
/*
* Parsing flags for over-ethernet protocol
*/
-enum prs_flags_over_eth
-{
+enum prs_flags_over_eth {
PRS_FLAG_OVERETH_UNKNOWN,
PRS_FLAG_OVERETH_IPV4,
PRS_FLAG_OVERETH_IPV6,
@@ -3682,8 +4029,7 @@ enum prs_flags_over_eth
/*
* Parsing flags for over-IP protocol
*/
-enum prs_flags_over_ip
-{
+enum prs_flags_over_ip {
PRS_FLAG_OVERIP_UNKNOWN,
PRS_FLAG_OVERIP_TCP,
PRS_FLAG_OVERIP_UDP,
@@ -3693,18 +4039,17 @@ enum prs_flags_over_ip
/*
* SDM operation gen command (generate aggregative interrupt)
*/
-struct sdm_op_gen
-{
- uint32_t command;
-#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */
+struct sdm_op_gen {
+ __le32 command;
+#define SDM_OP_GEN_COMP_PARAM (0x1F << 0)
#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
-#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */
+#define SDM_OP_GEN_COMP_TYPE (0x7 << 5)
#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
-#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */
+#define SDM_OP_GEN_AGG_VECT_IDX (0xFF << 8)
#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
-#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */
+#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1 << 16)
#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
-#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */
+#define SDM_OP_GEN_RESERVED (0x7FFF << 17)
#define SDM_OP_GEN_RESERVED_SHIFT 17
};
@@ -3712,17 +4057,16 @@ struct sdm_op_gen
/*
* Timers connection context
*/
-struct timers_block_context
-{
- uint32_t __reserved_0 /* data of client 0 of the timers block*/;
- uint32_t __reserved_1 /* data of client 1 of the timers block*/;
- uint32_t __reserved_2 /* data of client 2 of the timers block*/;
+struct timers_block_context {
+ uint32_t __reserved_0;
+ uint32_t __reserved_1;
+ uint32_t __reserved_2;
uint32_t flags;
-#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */
+#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3 << 0)
#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
-#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */
+#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1 << 2)
#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
-#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */
+#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF << 3)
#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
};
@@ -3730,8 +4074,7 @@ struct timers_block_context
/*
* The eth aggregative context of Tstorm
*/
-struct tstorm_eth_ag_context
-{
+struct tstorm_eth_ag_context {
uint32_t __reserved0[14];
};
@@ -3739,17 +4082,16 @@ struct tstorm_eth_ag_context
/*
* The eth aggregative context of Ustorm
*/
-struct ustorm_eth_ag_context
-{
+struct ustorm_eth_ag_context {
uint32_t __reserved0;
#if defined(__BIG_ENDIAN)
- uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
+ uint8_t cdu_usage;
uint8_t __reserved2;
uint16_t __reserved1;
#elif defined(__LITTLE_ENDIAN)
uint16_t __reserved1;
uint8_t __reserved2;
- uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
+ uint8_t cdu_usage;
#endif
uint32_t __reserved3[6];
};
@@ -3758,17 +4100,16 @@ struct ustorm_eth_ag_context
/*
* The eth aggregative context of Xstorm
*/
-struct xstorm_eth_ag_context
-{
+struct xstorm_eth_ag_context {
uint32_t reserved0;
#if defined(__BIG_ENDIAN)
- uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
+ uint8_t cdu_reserved;
uint8_t reserved2;
uint16_t reserved1;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved1;
uint8_t reserved2;
- uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
+ uint8_t cdu_reserved;
#endif
uint32_t reserved3[30];
};
@@ -3777,16 +4118,15 @@ struct xstorm_eth_ag_context
/*
* doorbell message sent to the chip
*/
-struct doorbell
-{
+struct doorbell {
#if defined(__BIG_ENDIAN)
- uint16_t zero_fill2 /* driver must zero this field! */;
- uint8_t zero_fill1 /* driver must zero this field! */;
+ uint16_t zero_fill2;
+ uint8_t zero_fill1;
struct doorbell_hdr header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr header;
- uint8_t zero_fill1 /* driver must zero this field! */;
- uint16_t zero_fill2 /* driver must zero this field! */;
+ uint8_t zero_fill1;
+ uint16_t zero_fill2;
#endif
};
@@ -3794,527 +4134,563 @@ struct doorbell
/*
* doorbell message sent to the chip
*/
-struct doorbell_set_prod
-{
+struct doorbell_set_prod {
#if defined(__BIG_ENDIAN)
- uint16_t prod /* Producer index to be set */;
- uint8_t zero_fill1 /* driver must zero this field! */;
+ uint16_t prod;
+ uint8_t zero_fill1;
struct doorbell_hdr header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr header;
- uint8_t zero_fill1 /* driver must zero this field! */;
- uint16_t prod /* Producer index to be set */;
+ uint8_t zero_fill1;
+ uint16_t prod;
#endif
};
-struct regpair
-{
- uint32_t lo /* low word for reg-pair */;
- uint32_t hi /* high word for reg-pair */;
+struct regpair {
+ __le32 lo;
+ __le32 hi;
};
-struct regpair_native
-{
- uint32_t lo /* low word for reg-pair */;
- uint32_t hi /* high word for reg-pair */;
+struct regpair_native {
+ uint32_t lo;
+ uint32_t hi;
};
/*
* Classify rule opcodes in E2/E3
*/
-enum classify_rule
-{
- CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */,
- CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */,
- CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */,
+enum classify_rule {
+ CLASSIFY_RULE_OPCODE_MAC,
+ CLASSIFY_RULE_OPCODE_VLAN,
+ CLASSIFY_RULE_OPCODE_PAIR,
+ CLASSIFY_RULE_OPCODE_IMAC_VNI,
MAX_CLASSIFY_RULE};
/*
* Classify rule types in E2/E3
*/
-enum classify_rule_action_type
-{
+enum classify_rule_action_type {
CLASSIFY_RULE_REMOVE,
CLASSIFY_RULE_ADD,
MAX_CLASSIFY_RULE_ACTION_TYPE};
/*
- * client init ramrod data $$KEEP_ENDIANNESS$$
+ * client init ramrod data
*/
-struct client_init_general_data
-{
- uint8_t client_id /* client_id */;
- uint8_t statistics_counter_id /* statistics counter id */;
- uint8_t statistics_en_flg /* statistics en flg */;
- uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */;
- uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
- uint8_t sp_client_id /* the slow path rings client Id. */;
- uint16_t mtu /* Host MTU from client config */;
- uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */;
- uint8_t func_id /* PCI function ID (0-71) */;
- uint8_t cos /* The connection cos, if applicable */;
+struct client_init_general_data {
+ uint8_t client_id;
+ uint8_t statistics_counter_id;
+ uint8_t statistics_en_flg;
+ uint8_t is_fcoe_flg;
+ uint8_t activate_flg;
+ uint8_t sp_client_id;
+ __le16 mtu;
+ uint8_t statistics_zero_flg;
+ uint8_t func_id;
+ uint8_t cos;
uint8_t traffic_type;
- uint32_t reserved0;
+ uint8_t fp_hsi_ver;
+ uint8_t reserved0[3];
};
/*
- * client init rx data $$KEEP_ENDIANNESS$$
+ * client init rx data
*/
-struct client_init_rx_data
-{
+struct client_init_rx_data {
uint8_t tpa_en;
-#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1 << 0)
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
-#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1 << 1)
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
-#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */
+#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1 << 2)
#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
-#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */
-#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
- uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */;
- uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */;
- uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */;
- uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */;
- uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
- uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */;
- uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */;
- uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */;
- uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;
- uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */;
- uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */;
- uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */;
- uint8_t status_block_id /* rx status block id */;
- uint8_t rx_sb_index_number /* status block indices */;
- uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
- uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
- uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
- uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */;
- uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
- uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */;
- uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */;
- struct regpair bd_page_base /* BD page base address at the host */;
- struct regpair sge_page_base /* SGE page base address at the host */;
- struct regpair cqe_page_base /* Completion queue base address */;
+#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE (0x1 << 3)
+#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE_SHIFT 3
+#define CLIENT_INIT_RX_DATA_RESERVED5 (0xF << 4)
+#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 4
+ uint8_t vmqueue_mode_en_flg;
+ uint8_t extra_data_over_sgl_en_flg;
+ uint8_t cache_line_alignment_log_size;
+ uint8_t enable_dynamic_hc;
+ uint8_t max_sges_for_packet;
+ uint8_t client_qzone_id;
+ uint8_t drop_ip_cs_err_flg;
+ uint8_t drop_tcp_cs_err_flg;
+ uint8_t drop_ttl0_flg;
+ uint8_t drop_udp_cs_err_flg;
+ uint8_t inner_vlan_removal_enable_flg;
+ uint8_t outer_vlan_removal_enable_flg;
+ uint8_t status_block_id;
+ uint8_t rx_sb_index_number;
+ uint8_t dont_verify_rings_pause_thr_flg;
+ uint8_t max_tpa_queues;
+ uint8_t silent_vlan_removal_flg;
+ __le16 max_bytes_on_bd;
+ __le16 sge_buff_size;
+ uint8_t approx_mcast_engine_id;
+ uint8_t rss_engine_id;
+ struct regpair bd_page_base;
+ struct regpair sge_page_base;
+ struct regpair cqe_page_base;
uint8_t is_leading_rss;
uint8_t is_approx_mcast;
- uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
- uint16_t state;
-#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */
+ __le16 max_agg_size;
+ __le16 state;
+#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1 << 0)
#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
-#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1 << 1)
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
-#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1 << 2)
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
-#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */
+#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1 << 3)
#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
-#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1 << 4)
#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
-#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1 << 5)
#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
-#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */
+#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1 << 6)
#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
-#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */
+#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF << 7)
#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
- uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */;
- uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */;
- uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */;
- uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */;
- uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
- uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
- uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket with will be genratet when this ring is full. for regular flow control set this to 1 */;
- uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
- uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
- uint32_t reserved6[2];
-};
-
-/*
- * client init tx data $$KEEP_ENDIANNESS$$
- */
-struct client_init_tx_data
-{
- uint8_t enforce_security_flg /* if set, security checks will be made for this connection */;
- uint8_t tx_status_block_id /* the number of status block to update */;
- uint8_t tx_sb_index_number /* the index to use inside the status block */;
- uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */;
- uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */;
- uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */;
- uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
- struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */;
- uint16_t state;
-#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */
+ __le16 cqe_pause_thr_low;
+ __le16 cqe_pause_thr_high;
+ __le16 bd_pause_thr_low;
+ __le16 bd_pause_thr_high;
+ __le16 sge_pause_thr_low;
+ __le16 sge_pause_thr_high;
+ __le16 rx_cos_mask;
+ __le16 silent_vlan_value;
+ __le16 silent_vlan_mask;
+ uint8_t handle_ptp_pkts_flg;
+ uint8_t reserved6[3];
+ __le32 reserved7;
+};
+
+/*
+ * client init tx data
+ */
+struct client_init_tx_data {
+ uint8_t enforce_security_flg;
+ uint8_t tx_status_block_id;
+ uint8_t tx_sb_index_number;
+ uint8_t tss_leading_client_id;
+ uint8_t tx_switching_flg;
+ uint8_t anti_spoofing_flg;
+ __le16 default_vlan;
+ struct regpair tx_bd_page_base;
+ __le16 state;
+#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1 << 0)
#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
-#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1 << 1)
#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
-#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1 << 2)
#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
-#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */
+#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1 << 3)
#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
-#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */
+#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF << 4)
#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
- uint8_t default_vlan_flg /* is default vlan valid for this client. */;
- uint8_t force_default_pri_flg /* if set, force default priority */;
- uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */;
- uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */;
- uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */;
- uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */;
+ uint8_t default_vlan_flg;
+ uint8_t force_default_pri_flg;
+ uint8_t tunnel_lso_inc_ip_id;
+ uint8_t refuse_outband_vlan_flg;
+ uint8_t tunnel_non_lso_pcsum_location;
+ uint8_t tunnel_non_lso_outer_ip_csum_location;
};
/*
- * client init ramrod data $$KEEP_ENDIANNESS$$
+ * client init ramrod data
*/
-struct client_init_ramrod_data
-{
- struct client_init_general_data general /* client init general data */;
- struct client_init_rx_data rx /* client init rx data */;
- struct client_init_tx_data tx /* client init tx data */;
+struct client_init_ramrod_data {
+ struct client_init_general_data general;
+ struct client_init_rx_data rx;
+ struct client_init_tx_data tx;
};
/*
- * client update ramrod data $$KEEP_ENDIANNESS$$
+ * client update ramrod data
*/
-struct client_update_ramrod_data
-{
- uint8_t client_id /* the client to update */;
- uint8_t func_id /* PCI function ID this client belongs to (0-71) */;
- uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */;
- uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */;
- uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */;
- uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */;
- uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */;
- uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */;
- uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
- uint8_t activate_change_flg /* If set, activate_flg will be checked */;
- uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
+struct client_update_ramrod_data {
+ uint8_t client_id;
+ uint8_t func_id;
+ uint8_t inner_vlan_removal_enable_flg;
+ uint8_t inner_vlan_removal_change_flg;
+ uint8_t outer_vlan_removal_enable_flg;
+ uint8_t outer_vlan_removal_change_flg;
+ uint8_t anti_spoofing_enable_flg;
+ uint8_t anti_spoofing_change_flg;
+ uint8_t activate_flg;
+ uint8_t activate_change_flg;
+ __le16 default_vlan;
uint8_t default_vlan_enable_flg;
uint8_t default_vlan_change_flg;
- uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
- uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
- uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
+ __le16 silent_vlan_value;
+ __le16 silent_vlan_mask;
+ uint8_t silent_vlan_removal_flg;
uint8_t silent_vlan_change_flg;
- uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */;
- uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */;
- uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */;
- uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */;
- uint32_t reserved1;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+ uint8_t refuse_outband_vlan_flg;
+ uint8_t refuse_outband_vlan_change_flg;
+ uint8_t tx_switching_flg;
+ uint8_t tx_switching_change_flg;
+ uint8_t handle_ptp_pkts_flg;
+ uint8_t handle_ptp_pkts_change_flg;
+ __le16 reserved1;
+ __le32 echo;
};
/*
* The eth storm context of Cstorm
*/
-struct cstorm_eth_st_context
-{
+struct cstorm_eth_st_context {
uint32_t __reserved0[4];
};
-struct double_regpair
-{
- uint32_t regpair0_lo /* low word for reg-pair0 */;
- uint32_t regpair0_hi /* high word for reg-pair0 */;
- uint32_t regpair1_lo /* low word for reg-pair1 */;
- uint32_t regpair1_hi /* high word for reg-pair1 */;
+struct double_regpair {
+ uint32_t regpair0_lo;
+ uint32_t regpair0_hi;
+ uint32_t regpair1_lo;
+ uint32_t regpair1_hi;
};
/*
- * Ethernet address types used in ethernet tx BDs
+ * 2nd parse bd type used in ethernet tx BDs
+ */
+enum eth_2nd_parse_bd_type {
+ ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
+ MAX_ETH_2ND_PARSE_BD_TYPE};
+
+
+/*
+ * Ethernet address typesm used in ethernet tx BDs
*/
-enum eth_addr_type
-{
+enum eth_addr_type {
UNKNOWN_ADDRESS,
UNICAST_ADDRESS,
MULTICAST_ADDRESS,
BROADCAST_ADDRESS,
- MAX_ETH_ADDR_TYPE
-};
+ MAX_ETH_ADDR_TYPE};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct eth_classify_cmd_header
-{
+struct eth_classify_cmd_header {
uint8_t cmd_general_data;
-#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1 << 0)
#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
-#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1 << 1)
#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
-#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */
+#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3 << 2)
#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
-#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */
+#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1 << 4)
#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
-#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */
+#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7 << 5)
#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
- uint8_t func_id /* the function id */;
+ uint8_t func_id;
uint8_t client_id;
uint8_t reserved1;
};
/*
- * header for eth classification config ramrod $$KEEP_ENDIANNESS$$
+ * header for eth classification config ramrod
*/
-struct eth_classify_header
-{
- uint8_t rule_cnt /* number of rules in classification config ramrod */;
- uint8_t reserved0;
- uint16_t reserved1;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+struct eth_classify_header {
+ uint8_t rule_cnt;
+ uint8_t warning_on_error;
+ __le16 reserved1;
+ __le32 echo;
};
/*
- * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a Inner-MAC/VNI classification rule
*/
-struct eth_classify_mac_cmd
-{
+struct eth_classify_imac_vni_cmd {
struct eth_classify_cmd_header header;
- uint16_t reserved0;
- uint16_t inner_mac;
- uint16_t mac_lsb;
- uint16_t mac_mid;
- uint16_t mac_msb;
- uint16_t reserved1;
+ __le32 vni;
+ __le16 imac_lsb;
+ __le16 imac_mid;
+ __le16 imac_msb;
+ __le16 reserved1;
};
/*
- * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a MAC classification rule
*/
-struct eth_classify_pair_cmd
-{
+struct eth_classify_mac_cmd {
struct eth_classify_cmd_header header;
- uint16_t reserved0;
- uint16_t inner_mac;
- uint16_t mac_lsb;
- uint16_t mac_mid;
- uint16_t mac_msb;
- uint16_t vlan;
+ __le16 reserved0;
+ __le16 inner_mac;
+ __le16 mac_lsb;
+ __le16 mac_mid;
+ __le16 mac_msb;
+ __le16 reserved1;
};
/*
- * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a MAC-VLAN pair classification rule
*/
-struct eth_classify_vlan_cmd
-{
+struct eth_classify_pair_cmd {
struct eth_classify_cmd_header header;
- uint32_t reserved0;
- uint32_t reserved1;
- uint16_t reserved2;
- uint16_t vlan;
+ __le16 reserved0;
+ __le16 inner_mac;
+ __le16 mac_lsb;
+ __le16 mac_mid;
+ __le16 mac_msb;
+ __le16 vlan;
+};
+
+
+/*
+ * Command for adding/removing a VLAN classification rule
+ */
+struct eth_classify_vlan_cmd {
+ struct eth_classify_cmd_header header;
+ __le32 reserved0;
+ __le32 reserved1;
+ __le16 reserved2;
+ __le16 vlan;
};
/*
- * union for eth classification rule $$KEEP_ENDIANNESS$$
+ * union for eth classification rule
*/
-union eth_classify_rule_cmd
-{
+union eth_classify_rule_cmd {
struct eth_classify_mac_cmd mac;
struct eth_classify_vlan_cmd vlan;
struct eth_classify_pair_cmd pair;
+ struct eth_classify_imac_vni_cmd imac_vni;
};
/*
- * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
+ * parameters for eth classification configuration ramrod
*/
-struct eth_classify_rules_ramrod_data
-{
+struct eth_classify_rules_ramrod_data {
struct eth_classify_header header;
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
};
/*
- * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$
+ * The data contain client ID need to the ramrod
*/
-struct eth_common_ramrod_data
-{
- uint32_t client_id /* id of this client. (5 bits are used) */;
- uint32_t reserved1;
+struct eth_common_ramrod_data {
+ __le32 client_id;
+ __le32 reserved1;
};
/*
* The eth storm context of Ustorm
*/
-struct ustorm_eth_st_context
-{
+struct ustorm_eth_st_context {
uint32_t reserved0[52];
};
/*
* The eth storm context of Tstorm
*/
-struct tstorm_eth_st_context
-{
+struct tstorm_eth_st_context {
uint32_t __reserved0[28];
};
/*
* The eth storm context of Xstorm
*/
-struct xstorm_eth_st_context
-{
+struct xstorm_eth_st_context {
uint32_t reserved0[60];
};
/*
* Ethernet connection context
*/
-struct eth_context
-{
- struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */;
- struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */;
- struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */;
- struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */;
- struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */;
- struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */;
- struct timers_block_context timers_context /* Timers block context */;
- struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */;
- struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */;
+struct eth_context {
+ struct ustorm_eth_st_context ustorm_st_context;
+ struct tstorm_eth_st_context tstorm_st_context;
+ struct xstorm_eth_ag_context xstorm_ag_context;
+ struct tstorm_eth_ag_context tstorm_ag_context;
+ struct cstorm_eth_ag_context cstorm_ag_context;
+ struct ustorm_eth_ag_context ustorm_ag_context;
+ struct timers_block_context timers_context;
+ struct xstorm_eth_st_context xstorm_st_context;
+ struct cstorm_eth_st_context cstorm_st_context;
};
/*
* union for sgl and raw data.
*/
-union eth_sgl_or_raw_data
-{
- uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */;
- uint32_t raw_data[4] /* raw data from Tstorm to the driver. */;
+union eth_sgl_or_raw_data {
+ __le16 sgl[8];
+ uint32_t raw_data[4];
};
/*
- * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$
+ * eth FP end aggregation CQE parameters struct
*/
-struct eth_end_agg_rx_cqe
-{
+struct eth_end_agg_rx_cqe {
uint8_t type_error_flags;
-#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
+#define ETH_END_AGG_RX_CQE_TYPE (0x3 << 0)
#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
-#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
+#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1 << 2)
#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
-#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */
+#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F << 3)
#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
uint8_t reserved1;
- uint8_t queue_index /* The aggregation queue index of this packet */;
+ uint8_t queue_index;
uint8_t reserved2;
- uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */;
- uint16_t num_of_coalesced_segs /* Num of coalesced segments. */;
- uint16_t pkt_len /* Packet length */;
- uint8_t pure_ack_count /* Number of pure acks coalesced. */;
+ __le32 timestamp_delta;
+ __le16 num_of_coalesced_segs;
+ __le16 pkt_len;
+ uint8_t pure_ack_count;
uint8_t reserved3;
- uint16_t reserved4;
- union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
- uint32_t reserved5[8];
+ __le16 reserved4;
+ union eth_sgl_or_raw_data sgl_or_raw_data;
+ __le32 padding[8];
};
+/*
+ * Ethernet error code
+ */
+enum eth_error_code {
+ ETH_OK = 0x00,
+ ETH_RAMROD_DATA_READ_ERROR = 0x01,
+ ETH_FILTERS_FUNC_NOT_ENABLED,
+ ETH_FILTERS_MAC_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_MAC_DEL_FAIL_NOF,
+ ETH_FILTERS_PAIR_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_PAIR_DEL_FAIL_NOF,
+ ETH_FILTERS_VLAN_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_VLAN_ADD_FAIL_DUP_TT,
+ ETH_FILTERS_VLAN_DEL_FAIL_NOF,
+ ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT,
+ ETH_FILTERS_VLAN_DEL_FAIL_NO_VLAN,
+ ETH_FILTERS_IMAC_VNI_ADD_UNALLOWED_IN_TX,
+ ETH_FILTERS_IMAC_VNI_DEL_UNALLOWED_IN_TX,
+ ETH_FILTERS_IMAC_VNI_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_IMAC_VNI_DEL_FAIL_NOF,
+ MAX_ETH_ERROR_CODE};
/*
- * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$
+ * regular eth FP CQE parameters struct
*/
-struct eth_fast_path_rx_cqe
-{
+struct eth_fast_path_rx_cqe {
uint8_t type_error_flags;
-#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
+#define ETH_FAST_PATH_RX_CQE_TYPE (0x3 << 0)
#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
+#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1 << 2)
#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
-#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1 << 3)
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
-#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1 << 4)
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
-#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1 << 5)
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
-#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */
-#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1 << 6)
+#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1 << 7)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
uint8_t status_flags;
-#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7 << 0)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1 << 3)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
-#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1 << 4)
#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
-#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1 << 5)
#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
-#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1 << 6)
#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
-#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1 << 7)
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
- uint8_t queue_index /* The aggregation queue index of this packet */;
- uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */;
- uint32_t rss_hash_result /* RSS toeplitz hash result */;
- uint16_t vlan_tag /* Ethernet VLAN tag field */;
- uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;
- uint16_t len_on_bd /* Number of bytes placed on the BD */;
+ uint8_t queue_index;
+ uint8_t placement_offset;
+ __le32 rss_hash_result;
+ __le16 vlan_tag;
+ __le16 pkt_len_or_gro_seg_len;
+ __le16 len_on_bd;
struct parsing_flags pars_flags;
- union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
- uint32_t reserved1[8];
+ union eth_sgl_or_raw_data sgl_or_raw_data;
+ uint8_t tunn_type;
+ uint8_t tunn_inner_hdrs_offset;
+ __le16 reserved1;
+ __le32 tunn_tenant_id;
+ __le32 padding[5];
+ __le32 marker;
};
/*
- * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$
+ * Command for setting classification flags for a client
*/
-struct eth_filter_rules_cmd
-{
+struct eth_filter_rules_cmd {
uint8_t cmd_general_data;
-#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_FILTER_RULES_CMD_RX_CMD (0x1 << 0)
#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
-#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_FILTER_RULES_CMD_TX_CMD (0x1 << 1)
#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
-#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */
+#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F << 2)
#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
- uint8_t func_id /* the function id */;
- uint8_t client_id /* the client id */;
+ uint8_t func_id;
+ uint8_t client_id;
uint8_t reserved1;
- uint16_t state;
-#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */
+ __le16 state;
+#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1 << 0)
#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
-#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1 << 1)
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
-#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1 << 2)
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
-#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */
+#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1 << 3)
#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
-#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1 << 4)
#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
-#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1 << 5)
#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
-#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */
+#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1 << 6)
#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
-#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */
+#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF << 7)
#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
- uint16_t reserved3;
+ __le16 reserved3;
struct regpair reserved4;
};
/*
- * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$
+ * parameters for eth classification filters ramrod
*/
-struct eth_filter_rules_ramrod_data
-{
+struct eth_filter_rules_ramrod_data {
struct eth_classify_header header;
struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
};
/*
- * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
+ * Hsi version
+ */
+enum eth_fp_hsi_ver {
+ ETH_FP_HSI_VER_0,
+ ETH_FP_HSI_VER_1,
+ ETH_FP_HSI_VER_2,
+ MAX_ETH_FP_HSI_VER};
+
+
+/*
+ * parameters for eth classification configuration ramrod
*/
-struct eth_general_rules_ramrod_data
-{
+struct eth_general_rules_ramrod_data {
struct eth_classify_header header;
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
};
@@ -4323,38 +4699,36 @@ struct eth_general_rules_ramrod_data
/*
* The data for Halt ramrod
*/
-struct eth_halt_ramrod_data
-{
- uint32_t client_id /* id of this client. (5 bits are used) */;
- uint32_t reserved0;
+struct eth_halt_ramrod_data {
+ __le32 client_id;
+ __le32 reserved0;
};
/*
* destination and source mac address.
*/
-struct eth_mac_addresses
-{
+struct eth_mac_addresses {
#if defined(__BIG_ENDIAN)
- uint16_t dst_mid /* destination mac address 16 middle bits */;
- uint16_t dst_lo /* destination mac address 16 low bits */;
+ __le16 dst_mid;
+ __le16 dst_lo;
#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_lo /* destination mac address 16 low bits */;
- uint16_t dst_mid /* destination mac address 16 middle bits */;
+ __le16 dst_lo;
+ __le16 dst_mid;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t src_lo /* source mac address 16 low bits */;
- uint16_t dst_hi /* destination mac address 16 high bits */;
+ __le16 src_lo;
+ __le16 dst_hi;
#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_hi /* destination mac address 16 high bits */;
- uint16_t src_lo /* source mac address 16 low bits */;
+ __le16 dst_hi;
+ __le16 src_lo;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t src_hi /* source mac address 16 high bits */;
- uint16_t src_mid /* source mac address 16 middle bits */;
+ __le16 src_hi;
+ __le16 src_mid;
#elif defined(__LITTLE_ENDIAN)
- uint16_t src_mid /* source mac address 16 middle bits */;
- uint16_t src_hi /* source mac address 16 high bits */;
+ __le16 src_mid;
+ __le16 src_hi;
#endif
};
@@ -4362,78 +4736,54 @@ struct eth_mac_addresses
/*
* tunneling related data.
*/
-struct eth_tunnel_data
-{
-#if defined(__BIG_ENDIAN)
- uint16_t dst_mid /* destination mac address 16 middle bits */;
- uint16_t dst_lo /* destination mac address 16 low bits */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_lo /* destination mac address 16 low bits */;
- uint16_t dst_mid /* destination mac address 16 middle bits */;
-#endif
-#if defined(__BIG_ENDIAN)
- uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
- uint16_t dst_hi /* destination mac address 16 high bits */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_hi /* destination mac address 16 high bits */;
- uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
-#endif
-#if defined(__BIG_ENDIAN)
+struct eth_tunnel_data {
+ __le16 dst_lo;
+ __le16 dst_mid;
+ __le16 dst_hi;
+ __le16 fw_ip_hdr_csum;
+ __le16 pseudo_csum;
+ uint8_t ip_hdr_start_inner_w;
uint8_t flags;
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
-#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
+#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1 << 0)
+#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
+#define ETH_TUNNEL_DATA_RESERVED (0x7F << 1)
#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
- uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
- uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
- uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
- uint8_t flags;
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
-#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
-#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
-#endif
};
/*
* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1).
*/
-union eth_mac_addr_or_tunnel_data
-{
- struct eth_mac_addresses mac_addr /* destination and source mac addresses. */;
- struct eth_tunnel_data tunnel_data /* tunneling related data. */;
+union eth_mac_addr_or_tunnel_data {
+ struct eth_mac_addresses mac_addr;
+ struct eth_tunnel_data tunnel_data;
};
/*
- * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$
+ * Command for setting multicast classification for a client
*/
-struct eth_multicast_rules_cmd
-{
+struct eth_multicast_rules_cmd {
uint8_t cmd_general_data;
-#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1 << 0)
#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
-#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1 << 1)
#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
-#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */
+#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1 << 2)
#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
-#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */
+#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F << 3)
#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
- uint8_t func_id /* the function id */;
- uint8_t bin_id /* the bin to add this function to (0-255) */;
- uint8_t engine_id /* the approximate multicast engine id */;
- uint32_t reserved2;
+ uint8_t func_id;
+ uint8_t bin_id;
+ uint8_t engine_id;
+ __le32 reserved2;
struct regpair reserved3;
};
/*
- * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$
+ * parameters for multicast classification ramrod
*/
-struct eth_multicast_rules_ramrod_data
-{
+struct eth_multicast_rules_ramrod_data {
struct eth_classify_header header;
struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
};
@@ -4442,17 +4792,15 @@ struct eth_multicast_rules_ramrod_data
/*
* Place holder for ramrods protocol specific data
*/
-struct ramrod_data
-{
- uint32_t data_lo;
- uint32_t data_hi;
+struct ramrod_data {
+ __le32 data_lo;
+ __le32 data_hi;
};
/*
* union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
*/
-union eth_ramrod_data
-{
+union eth_ramrod_data {
struct ramrod_data general;
};
@@ -4460,8 +4808,7 @@ union eth_ramrod_data
/*
* RSS toeplitz hash type, as reported in CQE
*/
-enum eth_rss_hash_type
-{
+enum eth_rss_hash_type {
DEFAULT_HASH_TYPE,
IPV4_HASH_TYPE,
TCP_IPV4_HASH_TYPE,
@@ -4476,100 +4823,100 @@ enum eth_rss_hash_type
/*
* Ethernet RSS mode
*/
-enum eth_rss_mode
-{
+enum eth_rss_mode {
ETH_RSS_MODE_DISABLED,
- ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */,
- ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
- ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */,
- ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */,
- ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */,
+ ETH_RSS_MODE_REGULAR,
+ ETH_RSS_MODE_ESX51,
+ ETH_RSS_MODE_VLAN_PRI,
+ ETH_RSS_MODE_E1HOV_PRI,
+ ETH_RSS_MODE_IP_DSCP,
MAX_ETH_RSS_MODE};
/*
- * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$
+ * parameters for RSS update ramrod (E2)
*/
-struct eth_rss_update_ramrod_data
-{
+struct eth_rss_update_ramrod_data {
uint8_t rss_engine_id;
- uint8_t capabilities;
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */
+ uint8_t rss_mode;
+ __le16 capabilities;
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1 << 0)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1 << 1)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1 << 2)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */
-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
- uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
- uint8_t rss_mode /* The RSS mode for this function */;
- uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
- uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
- uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */;
- uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */;
- uint32_t echo;
- uint32_t reserved3;
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1 << 3)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1 << 4)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1 << 5)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1 << 6)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1 << 7)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
+#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1 << 8)
+#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1 << 9)
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F << 10)
+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
+ uint8_t rss_result_mask;
+ uint8_t reserved3;
+ __le16 reserved4;
+ uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
+ __le32 rss_key[T_ETH_RSS_KEY];
+ __le32 echo;
+ __le32 reserved5;
};
/*
* The eth Rx Buffer Descriptor
*/
-struct eth_rx_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
+struct eth_rx_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
};
/*
- * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$
+ * Eth Rx Cqe structure- general structure for ramrods
*/
-struct common_ramrod_eth_rx_cqe
-{
+struct common_ramrod_eth_rx_cqe {
uint8_t ramrod_type;
-#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3 << 0)
#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
-#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */
+#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1 << 2)
#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
-#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F << 3)
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
- uint8_t conn_type /* only 3 bits are used */;
- uint16_t reserved1 /* protocol specific data */;
- uint32_t conn_and_cmd_data;
-#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
+ uint8_t conn_type;
+ __le16 reserved1;
+ __le32 conn_and_cmd_data;
+#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF << 0)
#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
-#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF << 24)
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
- struct ramrod_data protocol_data /* protocol specific data */;
- uint32_t echo;
- uint32_t reserved2[11];
+ struct ramrod_data protocol_data;
+ __le32 echo;
+ __le32 reserved2[11];
};
/*
* Rx Last CQE in page (in ETH)
*/
-struct eth_rx_cqe_next_page
-{
- uint32_t addr_lo /* Next page low pointer */;
- uint32_t addr_hi /* Next page high pointer */;
- uint32_t reserved[14];
+struct eth_rx_cqe_next_page {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le32 reserved[14];
};
/*
* union for all eth rx cqe types (fix their sizes)
*/
-union eth_rx_cqe
-{
+union eth_rx_cqe {
struct eth_fast_path_rx_cqe fast_path_cqe;
struct common_ramrod_eth_rx_cqe ramrod_cqe;
struct eth_rx_cqe_next_page next_page_cqe;
@@ -4580,324 +4927,328 @@ union eth_rx_cqe
/*
* Values for RX ETH CQE type field
*/
-enum eth_rx_cqe_type
-{
- RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */,
- RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */,
- RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */,
- RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */,
+enum eth_rx_cqe_type {
+ RX_ETH_CQE_TYPE_ETH_FASTPATH,
+ RX_ETH_CQE_TYPE_ETH_RAMROD,
+ RX_ETH_CQE_TYPE_ETH_START_AGG,
+ RX_ETH_CQE_TYPE_ETH_STOP_AGG,
MAX_ETH_RX_CQE_TYPE};
/*
* Type of SGL/Raw field in ETH RX fast path CQE
*/
-enum eth_rx_fp_sel
-{
- ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */,
- ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */,
+enum eth_rx_fp_sel {
+ ETH_FP_CQE_REGULAR,
+ ETH_FP_CQE_RAW,
MAX_ETH_RX_FP_SEL};
/*
* The eth Rx SGE Descriptor
*/
-struct eth_rx_sge
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
+struct eth_rx_sge {
+ __le32 addr_lo;
+ __le32 addr_hi;
};
/*
- * common data for all protocols $$KEEP_ENDIANNESS$$
+ * common data for all protocols
*/
-struct spe_hdr
-{
- uint32_t conn_and_cmd_data;
-#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
+struct spe_hdr {
+ __le32 conn_and_cmd_data;
+#define SPE_HDR_CID (0xFFFFFF << 0)
#define SPE_HDR_CID_SHIFT 0
-#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */
+#define SPE_HDR_CMD_ID (0xFF << 24)
#define SPE_HDR_CMD_ID_SHIFT 24
- uint16_t type;
-#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */
+ __le16 type;
+#define SPE_HDR_CONN_TYPE (0xFF << 0)
#define SPE_HDR_CONN_TYPE_SHIFT 0
-#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */
+#define SPE_HDR_FUNCTION_ID (0xFF << 8)
#define SPE_HDR_FUNCTION_ID_SHIFT 8
- uint16_t reserved1;
+ __le16 reserved1;
};
/*
* specific data for ethernet slow path element
*/
-union eth_specific_data
-{
- uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
- struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */;
- struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */;
- struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */;
- struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */;
- struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */;
- struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */;
- struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */;
- struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */;
+union eth_specific_data {
+ uint8_t protocol_data[8];
+ struct regpair client_update_ramrod_data;
+ struct regpair client_init_ramrod_init_data;
+ struct eth_halt_ramrod_data halt_ramrod_data;
+ struct regpair update_data_addr;
+ struct eth_common_ramrod_data common_ramrod_data;
+ struct regpair classify_cfg_addr;
+ struct regpair filter_cfg_addr;
+ struct regpair mcast_cfg_addr;
};
/*
* Ethernet slow path element
*/
-struct eth_spe
-{
- struct spe_hdr hdr /* common data for all protocols */;
- union eth_specific_data data /* data specific to ethernet protocol */;
+struct eth_spe {
+ struct spe_hdr hdr;
+ union eth_specific_data data;
};
/*
* Ethernet command ID for slow path elements
*/
-enum eth_spqe_cmd_id
-{
+enum eth_spqe_cmd_id {
RAMROD_CMD_ID_ETH_UNUSED,
- RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */,
- RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */,
- RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */,
- RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */,
- RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */,
- RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */,
- RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */,
- RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */,
- RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */,
- RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */,
+ RAMROD_CMD_ID_ETH_CLIENT_SETUP,
+ RAMROD_CMD_ID_ETH_HALT,
+ RAMROD_CMD_ID_ETH_FORWARD_SETUP,
+ RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
+ RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
+ RAMROD_CMD_ID_ETH_EMPTY,
+ RAMROD_CMD_ID_ETH_TERMINATE,
+ RAMROD_CMD_ID_ETH_TPA_UPDATE,
+ RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
+ RAMROD_CMD_ID_ETH_FILTER_RULES,
+ RAMROD_CMD_ID_ETH_MULTICAST_RULES,
+ RAMROD_CMD_ID_ETH_RSS_UPDATE,
+ RAMROD_CMD_ID_ETH_SET_MAC,
MAX_ETH_SPQE_CMD_ID};
/*
* eth tpa update command
*/
-enum eth_tpa_update_command
-{
- TPA_UPDATE_NONE_COMMAND /* nop command */,
- TPA_UPDATE_ENABLE_COMMAND /* enable command */,
- TPA_UPDATE_DISABLE_COMMAND /* disable command */,
+enum eth_tpa_update_command {
+ TPA_UPDATE_NONE_COMMAND,
+ TPA_UPDATE_ENABLE_COMMAND,
+ TPA_UPDATE_DISABLE_COMMAND,
MAX_ETH_TPA_UPDATE_COMMAND};
/*
* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header
*/
-enum eth_tunnel_lso_inc_ip_id
-{
- EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */,
- INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */,
+enum eth_tunnel_lso_inc_ip_id {
+ EXT_HEADER,
+ INT_HEADER,
MAX_ETH_TUNNEL_LSO_INC_IP_ID};
/*
* In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD.
*/
-enum eth_tunnel_non_lso_csum_location
-{
- CSUM_ON_PKT /* checksum is on the packet. */,
- CSUM_ON_BD /* checksum is on the BD. */,
+enum eth_tunnel_non_lso_csum_location {
+ CSUM_ON_PKT,
+ CSUM_ON_BD,
MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};
/*
- * Tx regular BD structure $$KEEP_ENDIANNESS$$
+ * Packet Tunneling Type
+ */
+enum eth_tunn_type {
+ TUNN_TYPE_NONE,
+ TUNN_TYPE_VXLAN,
+ TUNN_TYPE_L2_GRE,
+ TUNN_TYPE_IPV4_GRE,
+ TUNN_TYPE_IPV6_GRE,
+ TUNN_TYPE_L2_GENEVE,
+ TUNN_TYPE_IPV4_GENEVE,
+ TUNN_TYPE_IPV6_GENEVE,
+ MAX_ETH_TUNN_TYPE};
+
+
+/*
+ * Tx regular BD structure
*/
-struct eth_tx_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
- uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */;
- uint16_t nbytes /* Size of the data represented by the BD */;
- uint8_t reserved[4] /* keeps same size as other eth tx bd types */;
+struct eth_tx_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le16 total_pkt_bytes;
+ __le16 nbytes;
+ uint8_t reserved[4];
};
/*
* structure for easy accessibility to assembler
*/
-struct eth_tx_bd_flags
-{
+struct eth_tx_bd_flags {
uint8_t as_bitfield;
-#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */
+#define ETH_TX_BD_FLAGS_IP_CSUM (0x1 << 0)
#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
-#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */
+#define ETH_TX_BD_FLAGS_L4_CSUM (0x1 << 1)
#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
-#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */
+#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3 << 2)
#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
-#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */
+#define ETH_TX_BD_FLAGS_START_BD (0x1 << 4)
#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
-#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */
+#define ETH_TX_BD_FLAGS_IS_UDP (0x1 << 5)
#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
-#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */
+#define ETH_TX_BD_FLAGS_SW_LSO (0x1 << 6)
#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
-#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */
+#define ETH_TX_BD_FLAGS_IPV6 (0x1 << 7)
#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
};
/*
- * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$
+ * The eth Tx Buffer Descriptor
*/
-struct eth_tx_start_bd
-{
- uint64_t addr;
- uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */;
- uint16_t nbytes /* Size of the data represented by the BD */;
- uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */;
+struct eth_tx_start_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le16 nbd;
+ __le16 nbytes;
+ __le16 vlan_or_ethertype;
struct eth_tx_bd_flags bd_flags;
uint8_t general_data;
-#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */
+#define ETH_TX_START_BD_HDR_NBDS (0x7 << 0)
#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
-#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */
+#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1 << 3)
+#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
+#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1 << 4)
#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
-#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */
+#define ETH_TX_START_BD_PARSE_NBDS (0x3 << 5)
#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
-#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */
+#define ETH_TX_START_BD_TUNNEL_EXIST (0x1 << 7)
#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
};
/*
- * Tx parsing BD structure for ETH E1h $$KEEP_ENDIANNESS$$
+ * Tx parsing BD structure for ETH E1/E1h
*/
-struct eth_tx_parse_bd_e1x
-{
- uint16_t global_data;
-#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */
+struct eth_tx_parse_bd_e1x {
+ __le16 global_data;
+#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF << 0)
#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */
+#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3 << 4)
#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
-#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */
+#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1 << 6)
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
-#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */
+#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1 << 7)
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
-#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
+#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1 << 8)
#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
-#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */
+#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F << 9)
#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
uint8_t tcp_flags;
-#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
+#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1 << 0)
#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
-#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
+#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1 << 1)
#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
-#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
+#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1 << 2)
#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
-#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
+#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1 << 3)
#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
-#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
+#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1 << 4)
#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
-#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
+#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1 << 5)
#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
-#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
+#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1 << 6)
#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
-#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
+#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1 << 7)
#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
- uint8_t ip_hlen_w /* IP header length in WORDs */;
- uint16_t total_hlen_w /* IP+TCP+ETH */;
- uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */;
- uint16_t lso_mss /* for LSO mode */;
- uint16_t ip_id /* for LSO mode */;
- uint32_t tcp_send_seq /* for LSO mode */;
+ uint8_t ip_hlen_w;
+ __le16 total_hlen_w;
+ __le16 tcp_pseudo_csum;
+ __le16 lso_mss;
+ __le16 ip_id;
+ __le32 tcp_send_seq;
};
/*
- * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$
+ * Tx parsing BD structure for ETH E2
*/
-struct eth_tx_parse_bd_e2
-{
- union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */;
- uint32_t parsing_data;
-#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */
+struct eth_tx_parse_bd_e2 {
+ union eth_mac_addr_or_tunnel_data data;
+ __le32 parsing_data;
+#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF << 0)
#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */
+#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF << 11)
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
-#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */
+#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1 << 15)
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
-#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */
+#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF << 16)
#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
-#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */
+#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3 << 30)
#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
};
/*
- * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$
+ * Tx 2nd parsing BD structure for ETH packet
*/
-struct eth_tx_parse_2nd_bd
-{
- uint16_t global_data;
-#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */
+struct eth_tx_parse_2nd_bd {
+ __le16 global_data;
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF << 0)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
-#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */
+#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1 << 4)
#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
-#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */
+#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1 << 5)
#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
-#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
+#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1 << 6)
#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
-#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */
+#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1 << 7)
#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
-#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F << 8)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
-#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */
+#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7 << 13)
#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
- uint16_t reserved2;
+ uint8_t bd_type;
+#define ETH_TX_PARSE_2ND_BD_TYPE (0xF << 0)
+#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
+#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF << 4)
+#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
+ uint8_t reserved3;
uint8_t tcp_flags;
-#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
+#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1 << 0)
#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
-#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
+#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1 << 1)
#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
-#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
+#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1 << 2)
#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
-#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
+#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1 << 3)
#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
-#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
+#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1 << 4)
#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
-#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
+#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1 << 5)
#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
-#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
+#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1 << 6)
#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
-#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
+#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1 << 7)
#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
- uint8_t reserved3;
- uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */;
- uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */;
- uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */;
- uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */;
- uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */;
+ uint8_t reserved4;
+ uint8_t tunnel_udp_hdr_start_w;
+ uint8_t fw_ip_hdr_to_payload_w;
+ __le16 fw_ip_csum_wo_len_flags_frag;
+ __le16 hw_ip_id;
+ __le32 tcp_send_seq;
};
/*
* The last BD in the BD memory will hold a pointer to the next BD memory
*/
-struct eth_tx_next_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
- uint8_t reserved[8] /* keeps same size as other eth tx bd types */;
+struct eth_tx_next_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ uint8_t reserved[8];
};
/*
* union for 4 Bd types
*/
-union eth_tx_bd_types
-{
- struct eth_tx_start_bd start_bd /* the first bd in a packets */;
- struct eth_tx_bd reg_bd /* the common bd */;
- struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */;
- struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */;
- struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */;
- struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */;
+union eth_tx_bd_types {
+ struct eth_tx_start_bd start_bd;
+ struct eth_tx_bd reg_bd;
+ struct eth_tx_parse_bd_e1x parse_bd_e1x;
+ struct eth_tx_parse_bd_e2 parse_bd_e2;
+ struct eth_tx_parse_2nd_bd parse_2nd_bd;
+ struct eth_tx_next_bd next_bd;
};
/*
* array of 13 bds as appears in the eth xstorm context
*/
-struct eth_tx_bds_array
-{
+struct eth_tx_bds_array {
union eth_tx_bd_types bds[13];
};
@@ -4905,79 +5256,73 @@ struct eth_tx_bds_array
/*
* VLAN mode on TX BDs
*/
-enum eth_tx_vlan_type
-{
+enum eth_tx_vlan_type {
X_ETH_NO_VLAN,
X_ETH_OUTBAND_VLAN,
X_ETH_INBAND_VLAN,
- X_ETH_FW_ADDED_VLAN /* Driver should not use this! */,
+ X_ETH_FW_ADDED_VLAN,
MAX_ETH_TX_VLAN_TYPE};
/*
* Ethernet VLAN filtering mode in E1x
*/
-enum eth_vlan_filter_mode
-{
- ETH_VLAN_FILTER_ANY_VLAN /* Don't filter by vlan */,
- ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */,
- ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */,
+enum eth_vlan_filter_mode {
+ ETH_VLAN_FILTER_ANY_VLAN,
+ ETH_VLAN_FILTER_SPECIFIC_VLAN,
+ ETH_VLAN_FILTER_CLASSIFY,
MAX_ETH_VLAN_FILTER_MODE};
/*
- * MAC filtering configuration command header $$KEEP_ENDIANNESS$$
+ * MAC filtering configuration command header
*/
-struct mac_configuration_hdr
-{
- uint8_t length /* number of entries valid in this command (6 bits) */;
- uint8_t offset /* offset of the first entry in the list */;
- uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+struct mac_configuration_hdr {
+ uint8_t length;
+ uint8_t offset;
+ __le16 client_id;
+ __le32 echo;
};
/*
- * MAC address in list for ramrod $$KEEP_ENDIANNESS$$
+ * MAC address in list for ramrod
*/
-struct mac_configuration_entry
-{
- uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */;
- uint8_t pf_id /* The pf id, for multi function mode */;
+struct mac_configuration_entry {
+ __le16 lsb_mac_addr;
+ __le16 middle_mac_addr;
+ __le16 msb_mac_addr;
+ __le16 vlan_id;
+ uint8_t pf_id;
uint8_t flags;
-#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */
+#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1 << 0)
#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
-#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */
+#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1 << 1)
#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
-#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */
+#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3 << 2)
#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
-#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - can't remove vlan 1 - can remove vlan. relevant only to everest1 */
+#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1 << 4)
#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
-#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */
+#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1 << 5)
#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
-#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */
+#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3 << 6)
#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
- uint16_t reserved0;
- uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */;
+ __le16 reserved0;
+ __le32 clients_bit_vector;
};
/*
* MAC filtering configuration command
*/
-struct mac_configuration_cmd
-{
- struct mac_configuration_hdr hdr /* header */;
- struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */;
+struct mac_configuration_cmd {
+ struct mac_configuration_hdr hdr;
+ struct mac_configuration_entry config_table[64];
};
/*
* Set-MAC command type (in E1x)
*/
-enum set_mac_action_type
-{
+enum set_mac_action_type {
T_ETH_MAC_COMMAND_INVALIDATE,
T_ETH_MAC_COMMAND_SET,
MAX_SET_MAC_ACTION_TYPE};
@@ -4986,160 +5331,211 @@ enum set_mac_action_type
/*
* Ethernet TPA Modes
*/
-enum tpa_mode
-{
- TPA_LRO /* LRO mode TPA */,
- TPA_GRO /* GRO mode TPA */,
+enum tpa_mode {
+ TPA_LRO,
+ TPA_GRO,
MAX_TPA_MODE};
/*
- * tpa update ramrod data $$KEEP_ENDIANNESS$$
+ * tpa update ramrod data
*/
-struct tpa_update_ramrod_data
-{
- uint8_t update_ipv4 /* none, enable or disable */;
- uint8_t update_ipv6 /* none, enable or disable */;
- uint8_t client_id /* client init flow control data */;
- uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
- uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
- uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */;
- uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
- uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */;
- uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
- uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
- uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */;
- uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */;
- uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
- uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
+struct tpa_update_ramrod_data {
+ uint8_t update_ipv4;
+ uint8_t update_ipv6;
+ uint8_t client_id;
+ uint8_t max_tpa_queues;
+ uint8_t max_sges_for_packet;
+ uint8_t complete_on_both_clients;
+ uint8_t dont_verify_rings_pause_thr_flg;
+ uint8_t tpa_mode;
+ __le16 sge_buff_size;
+ __le16 max_agg_size;
+ __le32 sge_page_base_lo;
+ __le32 sge_page_base_hi;
+ __le16 sge_pause_thr_low;
+ __le16 sge_pause_thr_high;
+ uint8_t tpa_over_vlan_disable;
+ uint8_t reserved[7];
};
/*
* approximate-match multicast filtering for E1H per function in Tstorm
*/
-struct tstorm_eth_approximate_match_multicast_filtering
-{
- uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */;
+struct tstorm_eth_approximate_match_multicast_filtering {
+ uint32_t mcast_add_hash_bit_array[8];
};
/*
- * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$
+ * Common configuration parameters per function in Tstorm
*/
-struct tstorm_eth_function_common_config
-{
- uint16_t config_flags;
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
+struct tstorm_eth_function_common_config {
+ __le16 config_flags;
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1 << 0)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1 << 1)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1 << 2)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1 << 3)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7 << 4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Don't filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1 << 7)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF << 8)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
- uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
+ uint8_t rss_result_mask;
uint8_t reserved1;
- uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */;
+ __le16 vlan_id[2];
};
/*
- * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$
+ * MAC filtering configuration parameters per port in Tstorm
*/
-struct tstorm_eth_mac_filter_config
-{
- uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */;
- uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */;
- uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */;
- uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */;
- uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */;
- uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. The primary vlan is taken from the CAM target table. */;
- uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */;
+struct tstorm_eth_mac_filter_config {
+ uint32_t ucast_drop_all;
+ uint32_t ucast_accept_all;
+ uint32_t mcast_drop_all;
+ uint32_t mcast_accept_all;
+ uint32_t bcast_accept_all;
+ uint32_t vlan_filter[2];
+ uint32_t unmatched_unicast;
};
/*
- * tx only queue init ramrod data $$KEEP_ENDIANNESS$$
+ * tx only queue init ramrod data
*/
-struct tx_queue_init_ramrod_data
-{
- struct client_init_general_data general /* client init general data */;
- struct client_init_tx_data tx /* client init tx data */;
+struct tx_queue_init_ramrod_data {
+ struct client_init_general_data general;
+ struct client_init_tx_data tx;
};
/*
* Three RX producers for ETH
*/
-union ustorm_eth_rx_producers
-{
- struct {
+struct ustorm_eth_rx_producers {
#if defined(__BIG_ENDIAN)
- uint16_t bd_prod /* Producer of the RX BD ring */;
- uint16_t cqe_prod /* Producer of the RX CQE ring */;
+ uint16_t bd_prod;
+ uint16_t cqe_prod;
#elif defined(__LITTLE_ENDIAN)
- uint16_t cqe_prod /* Producer of the RX CQE ring */;
- uint16_t bd_prod /* Producer of the RX BD ring */;
+ uint16_t cqe_prod;
+ uint16_t bd_prod;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t reserved;
- uint16_t sge_prod /* Producer of the RX SGE ring */;
+ uint16_t reserved;
+ uint16_t sge_prod;
#elif defined(__LITTLE_ENDIAN)
- uint16_t sge_prod /* Producer of the RX SGE ring */;
- uint16_t reserved;
+ uint16_t sge_prod;
+ uint16_t reserved;
#endif
- } prod;
- uint32_t raw_data[2];
};
/*
- * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$
+ * FCoE RX statistics parameters section#0
+ */
+struct fcoe_rx_stat_params_section0 {
+ __le32 fcoe_rx_pkt_cnt;
+ __le32 fcoe_rx_byte_cnt;
+};
+
+
+/*
+ * FCoE RX statistics parameters section#1
+ */
+struct fcoe_rx_stat_params_section1 {
+ __le32 fcoe_ver_cnt;
+ __le32 fcoe_rx_drop_pkt_cnt;
+};
+
+
+/*
+ * FCoE RX statistics parameters section#2
+ */
+struct fcoe_rx_stat_params_section2 {
+ __le32 fc_crc_cnt;
+ __le32 eofa_del_cnt;
+ __le32 miss_frame_cnt;
+ __le32 seq_timeout_cnt;
+ __le32 drop_seq_cnt;
+ __le32 fcoe_rx_drop_pkt_cnt;
+ __le32 fcp_rx_pkt_cnt;
+ __le32 reserved0;
+};
+
+
+/*
+ * FCoE TX statistics parameters
+ */
+struct fcoe_tx_stat_params {
+ __le32 fcoe_tx_pkt_cnt;
+ __le32 fcoe_tx_byte_cnt;
+ __le32 fcp_tx_pkt_cnt;
+ __le32 reserved0;
+};
+
+/*
+ * FCoE statistics parameters
*/
-struct afex_vif_list_ramrod_data
-{
- uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */;
- uint8_t func_bit_map /* the function bit map to set */;
- uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */;
- uint8_t func_to_clear /* the func id to clear in case of clear func mode */;
+struct fcoe_statistics_params {
+ struct fcoe_tx_stat_params tx_stat;
+ struct fcoe_rx_stat_params_section0 rx_stat0;
+ struct fcoe_rx_stat_params_section1 rx_stat1;
+ struct fcoe_rx_stat_params_section2 rx_stat2;
+};
+
+
+/*
+ * The data afex vif list ramrod need
+ */
+struct afex_vif_list_ramrod_data {
+ uint8_t afex_vif_list_command;
+ uint8_t func_bit_map;
+ __le16 vif_list_index;
+ uint8_t func_to_clear;
uint8_t echo;
- uint16_t reserved1;
+ __le16 reserved1;
};
/*
- * cfc delete event data $$KEEP_ENDIANNESS$$
+ *
*/
-struct cfc_del_event_data
-{
- uint32_t cid /* cid of deleted connection */;
- uint32_t reserved0;
- uint32_t reserved1;
+struct c2s_pri_trans_table_entry {
+ uint8_t val[8];
+};
+
+
+/*
+ * cfc delete event data
+ */
+struct cfc_del_event_data {
+ __le32 cid;
+ __le32 reserved0;
+ __le32 reserved1;
};
/*
* per-port SAFC demo variables
*/
-struct cmng_flags_per_port
-{
+struct cmng_flags_per_port {
uint32_t cmng_enables;
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1 << 0)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
-#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1 << 1)
#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1 << 2)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1 << 3)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
-#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */
+#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF << 4)
#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
uint32_t __reserved1;
};
@@ -5148,46 +5544,42 @@ struct cmng_flags_per_port
/*
* per-port rate shaping variables
*/
-struct rate_shaping_vars_per_port
-{
- uint32_t rs_periodic_timeout /* timeout of periodic timer */;
- uint32_t rs_threshold /* threshold, below which we start to stop queues */;
+struct rate_shaping_vars_per_port {
+ uint32_t rs_periodic_timeout;
+ uint32_t rs_threshold;
};
/*
* per-port fairness variables
*/
-struct fairness_vars_per_port
-{
- uint32_t upper_bound /* Quota for a protocol/vnic */;
- uint32_t fair_threshold /* almost-empty threshold */;
- uint32_t fairness_timeout /* timeout of fairness timer */;
- uint32_t reserved0;
+struct fairness_vars_per_port {
+ uint32_t upper_bound;
+ uint32_t fair_threshold;
+ uint32_t fairness_timeout;
+ uint32_t size_thr;
};
/*
* per-port SAFC variables
*/
-struct safc_struct_per_port
-{
+struct safc_struct_per_port {
#if defined(__BIG_ENDIAN)
uint16_t __reserved1;
uint8_t __reserved0;
- uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
+ uint8_t safc_timeout_usec;
#elif defined(__LITTLE_ENDIAN)
- uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
+ uint8_t safc_timeout_usec;
uint8_t __reserved0;
uint16_t __reserved1;
#endif
- uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */;
- uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */;
+ uint8_t cos_to_traffic_types[MAX_COS_NUMBER];
+ uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS];
};
/*
* Per-port congestion management variables
*/
-struct cmng_struct_per_port
-{
+struct cmng_struct_per_port {
struct rate_shaping_vars_per_port rs_vars;
struct fairness_vars_per_port fair_vars;
struct safc_struct_per_port safc_vars;
@@ -5197,14 +5589,13 @@ struct cmng_struct_per_port
/*
* a single rate shaping counter. can be used as protocol or vnic counter
*/
-struct rate_shaping_counter
-{
- uint32_t quota /* Quota for a protocol/vnic */;
+struct rate_shaping_counter {
+ uint32_t quota;
#if defined(__BIG_ENDIAN)
uint16_t __reserved0;
- uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
+ uint16_t rate;
#elif defined(__LITTLE_ENDIAN)
- uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
+ uint16_t rate;
uint16_t __reserved0;
#endif
};
@@ -5212,26 +5603,23 @@ struct rate_shaping_counter
/*
* per-vnic rate shaping variables
*/
-struct rate_shaping_vars_per_vn
-{
- struct rate_shaping_counter vn_counter /* per-vnic counter */;
+struct rate_shaping_vars_per_vn {
+ struct rate_shaping_counter vn_counter;
};
/*
* per-vnic fairness variables
*/
-struct fairness_vars_per_vn
-{
- uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */;
- uint32_t vn_credit_delta /* used for incrementing the credit */;
+struct fairness_vars_per_vn {
+ uint32_t cos_credit_delta[MAX_COS_NUMBER];
+ uint32_t vn_credit_delta;
uint32_t __reserved0;
};
/*
* cmng port init state
*/
-struct cmng_vnic
-{
+struct cmng_vnic {
struct rate_shaping_vars_per_vn vnic_max_rate[4];
struct fairness_vars_per_vn vnic_min_rate[4];
};
@@ -5239,8 +5627,7 @@ struct cmng_vnic
/*
* cmng port init state
*/
-struct cmng_init
-{
+struct cmng_init {
struct cmng_struct_per_port port;
struct cmng_vnic vnic;
};
@@ -5249,12 +5636,13 @@ struct cmng_init
/*
* driver parameters for congestion management init, all rates are in Mbps
*/
-struct cmng_init_input
-{
+struct cmng_init_input {
uint32_t port_rate;
- uint16_t vnic_min_rate[4] /* rates are in Mbps */;
- uint16_t vnic_max_rate[4] /* rates are in Mbps */;
- uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */;
+ uint32_t size_thr;
+ uint32_t fairness_thr;
+ uint16_t vnic_min_rate[4];
+ uint16_t vnic_max_rate[4];
+ uint16_t cos_min_rate[MAX_COS_NUMBER];
uint16_t cos_to_pause_mask[MAX_COS_NUMBER];
struct cmng_flags_per_port flags;
};
@@ -5263,64 +5651,59 @@ struct cmng_init_input
/*
* Protocol-common command ID for slow path elements
*/
-enum common_spqe_cmd_id
-{
+enum common_spqe_cmd_id {
RAMROD_CMD_ID_COMMON_UNUSED,
- RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */,
- RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */,
- RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */,
- RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */,
- RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
- RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */,
- RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
- RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
- RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */,
- RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
+ RAMROD_CMD_ID_COMMON_FUNCTION_START,
+ RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
+ RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
+ RAMROD_CMD_ID_COMMON_CFC_DEL,
+ RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
+ RAMROD_CMD_ID_COMMON_STAT_QUERY,
+ RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
+ RAMROD_CMD_ID_COMMON_START_TRAFFIC,
+ RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
+ RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
MAX_COMMON_SPQE_CMD_ID};
/*
* Per-protocol connection types
*/
-enum connection_type
-{
- ETH_CONNECTION_TYPE /* Ethernet */,
- TOE_CONNECTION_TYPE /* TOE */,
- RDMA_CONNECTION_TYPE /* RDMA */,
- ISCSI_CONNECTION_TYPE /* iSCSI */,
- FCOE_CONNECTION_TYPE /* FCoE */,
+enum connection_type {
+ ETH_CONNECTION_TYPE,
+ TOE_CONNECTION_TYPE,
+ RDMA_CONNECTION_TYPE,
+ ISCSI_CONNECTION_TYPE,
+ FCOE_CONNECTION_TYPE,
RESERVED_CONNECTION_TYPE_0,
RESERVED_CONNECTION_TYPE_1,
RESERVED_CONNECTION_TYPE_2,
- NONE_CONNECTION_TYPE /* General- used for common slow path */,
+ NONE_CONNECTION_TYPE,
MAX_CONNECTION_TYPE};
/*
* Cos modes
*/
-enum cos_mode
-{
- OVERRIDE_COS /* Firmware deduce cos according to DCB */,
- STATIC_COS /* Firmware has constant queues per CoS */,
- FW_WRR /* Firmware keep fairness between different CoSes */,
+enum cos_mode {
+ OVERRIDE_COS,
+ STATIC_COS,
+ FW_WRR,
MAX_COS_MODE};
/*
* Dynamic HC counters set by the driver
*/
-struct hc_dynamic_drv_counter
-{
- uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */;
+struct hc_dynamic_drv_counter {
+ uint32_t val[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* zone A per-queue data
*/
-struct cstorm_queue_zone_data
-{
- struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */;
+struct cstorm_queue_zone_data {
+ struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
struct regpair reserved[2];
};
@@ -5328,120 +5711,106 @@ struct cstorm_queue_zone_data
/*
* Vf-PF channel data in cstorm ram (non-triggered zone)
*/
-struct vf_pf_channel_zone_data
-{
- uint32_t msg_addr_lo /* the message address on VF memory */;
- uint32_t msg_addr_hi /* the message address on VF memory */;
+struct vf_pf_channel_zone_data {
+ uint32_t msg_addr_lo;
+ uint32_t msg_addr_hi;
};
/*
* zone for VF non-triggered data
*/
-struct non_trigger_vf_zone
-{
- struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */;
+struct non_trigger_vf_zone {
+ struct vf_pf_channel_zone_data vf_pf_channel;
};
/*
* Vf-PF channel trigger zone in cstorm ram
*/
-struct vf_pf_channel_zone_trigger
-{
- uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */;
+struct vf_pf_channel_zone_trigger {
+ uint8_t addr_valid;
};
/*
* zone that triggers the in-bound interrupt
*/
-struct trigger_vf_zone
-{
-#if defined(__BIG_ENDIAN)
- uint16_t reserved1;
- uint8_t reserved0;
- struct vf_pf_channel_zone_trigger vf_pf_channel;
-#elif defined(__LITTLE_ENDIAN)
+struct trigger_vf_zone {
struct vf_pf_channel_zone_trigger vf_pf_channel;
uint8_t reserved0;
uint16_t reserved1;
-#endif
uint32_t reserved2;
};
/*
* zone B per-VF data
*/
-struct cstorm_vf_zone_data
-{
- struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */;
- struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */;
+struct cstorm_vf_zone_data {
+ struct non_trigger_vf_zone non_trigger;
+ struct trigger_vf_zone trigger;
};
/*
* Dynamic host coalescing init parameters, per state machine
*/
-struct dynamic_hc_sm_config
-{
- uint32_t threshold[3] /* thresholds of number of outstanding bytes */;
- uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */;
- uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */;
- uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */;
- uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */;
- uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */;
+struct dynamic_hc_sm_config {
+ uint32_t threshold[3];
+ uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* Dynamic host coalescing init parameters
*/
-struct dynamic_hc_config
-{
- struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */;
+struct dynamic_hc_config {
+ struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
};
-struct e2_integ_data
-{
+struct e2_integ_data {
#if defined(__BIG_ENDIAN)
uint8_t flags;
-#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
+#define E2_INTEG_DATA_TESTING_EN (0x1 << 0)
#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
-#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
+#define E2_INTEG_DATA_LB_TX (0x1 << 1)
#define E2_INTEG_DATA_LB_TX_SHIFT 1
-#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
+#define E2_INTEG_DATA_COS_TX (0x1 << 2)
#define E2_INTEG_DATA_COS_TX_SHIFT 2
-#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1 << 3)
#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
-#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1 << 4)
#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
-#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
+#define E2_INTEG_DATA_RESERVED (0x7 << 5)
#define E2_INTEG_DATA_RESERVED_SHIFT 5
- uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
- uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
+ uint8_t cos;
+ uint8_t voq;
+ uint8_t pbf_queue;
#elif defined(__LITTLE_ENDIAN)
- uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
+ uint8_t pbf_queue;
+ uint8_t voq;
+ uint8_t cos;
uint8_t flags;
-#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
+#define E2_INTEG_DATA_TESTING_EN (0x1 << 0)
#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
-#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
+#define E2_INTEG_DATA_LB_TX (0x1 << 1)
#define E2_INTEG_DATA_LB_TX_SHIFT 1
-#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
+#define E2_INTEG_DATA_COS_TX (0x1 << 2)
#define E2_INTEG_DATA_COS_TX_SHIFT 2
-#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1 << 3)
#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
-#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1 << 4)
#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
-#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
+#define E2_INTEG_DATA_RESERVED (0x7 << 5)
#define E2_INTEG_DATA_RESERVED_SHIFT 5
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3;
uint8_t reserved2;
- uint8_t ramEn /* context area reserved for reading enable bit from ram */;
+ uint8_t ramEn;
#elif defined(__LITTLE_ENDIAN)
- uint8_t ramEn /* context area reserved for reading enable bit from ram */;
+ uint8_t ramEn;
uint8_t reserved2;
uint16_t reserved3;
#endif
@@ -5449,333 +5818,320 @@ struct e2_integ_data
/*
- * set mac event data $$KEEP_ENDIANNESS$$
+ * set mac event data
*/
-struct eth_event_data
-{
- uint32_t echo /* set mac echo data to return to driver */;
- uint32_t reserved0;
- uint32_t reserved1;
+struct eth_event_data {
+ __le32 echo;
+ __le32 reserved0;
+ __le32 reserved1;
};
/*
- * pf-vf event data $$KEEP_ENDIANNESS$$
+ * pf-vf event data
*/
-struct vf_pf_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
+struct vf_pf_event_data {
+ uint8_t vf_id;
uint8_t reserved0;
- uint16_t reserved1;
- uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */;
- uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */;
+ __le16 reserved1;
+ __le32 msg_addr_lo;
+ __le32 msg_addr_hi;
};
/*
- * VF FLR event data $$KEEP_ENDIANNESS$$
+ * VF FLR event data
*/
-struct vf_flr_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
+struct vf_flr_event_data {
+ uint8_t vf_id;
uint8_t reserved0;
- uint16_t reserved1;
- uint32_t reserved2;
- uint32_t reserved3;
+ __le16 reserved1;
+ __le32 reserved2;
+ __le32 reserved3;
};
/*
- * malicious VF event data $$KEEP_ENDIANNESS$$
+ * malicious VF event data
*/
-struct malicious_vf_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
- uint8_t err_id /* reason for malicious notification */;
- uint16_t reserved1;
- uint32_t reserved2;
- uint32_t reserved3;
+struct malicious_vf_event_data {
+ uint8_t vf_id;
+ uint8_t err_id;
+ __le16 reserved1;
+ __le32 reserved2;
+ __le32 reserved3;
};
/*
- * vif list event data $$KEEP_ENDIANNESS$$
+ * vif list event data
*/
-struct vif_list_event_data
-{
- uint8_t func_bit_map /* bit map of pf indice */;
+struct vif_list_event_data {
+ uint8_t func_bit_map;
uint8_t echo;
- uint16_t reserved0;
- uint32_t reserved1;
- uint32_t reserved2;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le32 reserved2;
};
/*
- * function update event data $$KEEP_ENDIANNESS$$
+ * function update event data
*/
-struct function_update_event_data
-{
+struct function_update_event_data {
uint8_t echo;
uint8_t reserved;
- uint16_t reserved0;
- uint32_t reserved1;
- uint32_t reserved2;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le32 reserved2;
};
/*
* union for all event ring message types
*/
-union event_data
-{
- struct vf_pf_event_data vf_pf_event /* vf-pf event data */;
- struct eth_event_data eth_event /* set mac event data */;
- struct cfc_del_event_data cfc_del_event /* cfc delete event data */;
- struct vf_flr_event_data vf_flr_event /* vf flr event data */;
- struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */;
- struct vif_list_event_data vif_list_event /* vif list event data */;
- struct function_update_event_data function_update_event /* function update event data */;
+union event_data {
+ struct vf_pf_event_data vf_pf_event;
+ struct eth_event_data eth_event;
+ struct cfc_del_event_data cfc_del_event;
+ struct vf_flr_event_data vf_flr_event;
+ struct malicious_vf_event_data malicious_vf_event;
+ struct vif_list_event_data vif_list_event;
+ struct function_update_event_data function_update_event;
};
/*
* per PF event ring data
*/
-struct event_ring_data
-{
- struct regpair_native base_addr /* ring base address */;
+struct event_ring_data {
+ struct regpair_native base_addr;
#if defined(__BIG_ENDIAN)
- uint8_t index_id /* index ID within the status block */;
- uint8_t sb_id /* status block ID */;
- uint16_t producer /* event ring producer */;
+ uint8_t index_id;
+ uint8_t sb_id;
+ uint16_t producer;
#elif defined(__LITTLE_ENDIAN)
- uint16_t producer /* event ring producer */;
- uint8_t sb_id /* status block ID */;
- uint8_t index_id /* index ID within the status block */;
+ uint16_t producer;
+ uint8_t sb_id;
+ uint8_t index_id;
#endif
uint32_t reserved0;
};
/*
- * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$
+ * event ring message element (each element is 128 bits)
*/
-struct event_ring_msg
-{
+struct event_ring_msg {
uint8_t opcode;
- uint8_t error /* error on the mesasage */;
+ uint8_t error;
uint16_t reserved1;
- union event_data data /* message data (96 bits data) */;
+ union event_data data;
};
/*
* event ring next page element (128 bits)
*/
-struct event_ring_next
-{
- struct regpair addr /* Address of the next page of the ring */;
+struct event_ring_next {
+ struct regpair addr;
uint32_t reserved[2];
};
/*
* union for event ring element types (each element is 128 bits)
*/
-union event_ring_elem
-{
- struct event_ring_msg message /* event ring message */;
- struct event_ring_next next_page /* event ring next page */;
+union event_ring_elem {
+ struct event_ring_msg message;
+ struct event_ring_next next_page;
};
/*
* Common event ring opcodes
*/
-enum event_ring_opcode
-{
+enum event_ring_opcode {
EVENT_RING_OPCODE_VF_PF_CHANNEL,
- EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */,
- EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */,
- EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */,
- EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
- EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */,
- EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
- EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
- EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */,
- EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */,
- EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */,
- EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */,
- EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */,
- EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */,
- EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */,
- EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */,
- EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
- EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
+ EVENT_RING_OPCODE_FUNCTION_START,
+ EVENT_RING_OPCODE_FUNCTION_STOP,
+ EVENT_RING_OPCODE_CFC_DEL,
+ EVENT_RING_OPCODE_CFC_DEL_WB,
+ EVENT_RING_OPCODE_STAT_QUERY,
+ EVENT_RING_OPCODE_STOP_TRAFFIC,
+ EVENT_RING_OPCODE_START_TRAFFIC,
+ EVENT_RING_OPCODE_VF_FLR,
+ EVENT_RING_OPCODE_MALICIOUS_VF,
+ EVENT_RING_OPCODE_FORWARD_SETUP,
+ EVENT_RING_OPCODE_RSS_UPDATE_RULES,
+ EVENT_RING_OPCODE_FUNCTION_UPDATE,
+ EVENT_RING_OPCODE_AFEX_VIF_LISTS,
+ EVENT_RING_OPCODE_SET_MAC,
+ EVENT_RING_OPCODE_CLASSIFICATION_RULES,
+ EVENT_RING_OPCODE_FILTERS_RULES,
+ EVENT_RING_OPCODE_MULTICAST_RULES,
+ EVENT_RING_OPCODE_SET_TIMESYNC,
MAX_EVENT_RING_OPCODE};
/*
* Modes for fairness algorithm
*/
-enum fairness_mode
-{
- FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */,
- FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */,
+enum fairness_mode {
+ FAIRNESS_COS_WRR_MODE,
+ FAIRNESS_COS_ETS_MODE,
MAX_FAIRNESS_MODE};
/*
- * Priority and cos $$KEEP_ENDIANNESS$$
+ * Priority and cos
*/
-struct priority_cos
-{
- uint8_t priority /* Priority */;
- uint8_t cos /* Cos */;
- uint16_t reserved1;
+struct priority_cos {
+ uint8_t priority;
+ uint8_t cos;
+ __le16 reserved1;
};
/*
- * The data for flow control configuration $$KEEP_ENDIANNESS$$
+ * The data for flow control configuration
*/
-struct flow_control_configuration
-{
- struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */;
- uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */;
- uint8_t dcb_version /* DCB version Increase by one on each DCB update */;
- uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */;
+struct flow_control_configuration {
+ struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
+ uint8_t dcb_enabled;
+ uint8_t dcb_version;
+ uint8_t dont_add_pri_0_en;
uint8_t reserved1;
- uint32_t reserved2;
+ __le32 reserved2;
+ uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct function_start_data
-{
- uint8_t function_mode /* the function mode */;
- uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode. (E2/E3 Only) */;
- uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */;
- uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
+struct function_start_data {
+ uint8_t function_mode;
+ uint8_t allow_npar_tx_switching;
+ __le16 sd_vlan_tag;
+ __le16 vif_id;
uint8_t path_id;
- uint8_t network_cos_mode /* The cos mode for network traffic. */;
- uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */;
- uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
- uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
- uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
- uint16_t reserved1[2];
-};
-
-
-/*
- * $$KEEP_ENDIANNESS$$
- */
-struct function_update_data
-{
- uint8_t vif_id_change_flg /* If set, vif_id will be checked */;
- uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */;
- uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */;
- uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */;
- uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
- uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */;
- uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */;
- uint8_t network_cos_mode /* The cos mode for network traffic. */;
- uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */;
- uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */;
- uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */;
- uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */;
+ uint8_t network_cos_mode;
+ uint8_t dmae_cmd_id;
+ uint8_t no_added_tags;
+ __le16 reserved0;
+ __le32 reserved1;
+ uint8_t inner_clss_vxlan;
+ uint8_t inner_clss_l2gre;
+ uint8_t inner_clss_l2geneve;
+ uint8_t inner_rss;
+ __le16 vxlan_dst_port;
+ __le16 geneve_dst_port;
+ uint8_t sd_accept_mf_clss_fail;
+ uint8_t sd_accept_mf_clss_fail_match_ethtype;
+ __le16 sd_accept_mf_clss_fail_ethtype;
+ __le16 sd_vlan_eth_type;
+ uint8_t sd_vlan_force_pri_flg;
+ uint8_t sd_vlan_force_pri_val;
+ uint8_t c2s_pri_tt_valid;
+ uint8_t c2s_pri_default;
+ uint8_t tx_vlan_filtering_enable;
+ uint8_t tx_vlan_filtering_use_pvid;
+ uint8_t reserved2[4];
+ struct c2s_pri_trans_table_entry c2s_pri_trans_table;
+};
+
+
+/*
+ *
+ */
+struct function_update_data {
+ uint8_t vif_id_change_flg;
+ uint8_t afex_default_vlan_change_flg;
+ uint8_t allowed_priorities_change_flg;
+ uint8_t network_cos_mode_change_flg;
+ __le16 vif_id;
+ __le16 afex_default_vlan;
+ uint8_t allowed_priorities;
+ uint8_t network_cos_mode;
+ uint8_t lb_mode_en_change_flg;
+ uint8_t lb_mode_en;
+ uint8_t tx_switch_suspend_change_flg;
+ uint8_t tx_switch_suspend;
uint8_t echo;
+ uint8_t update_tunn_cfg_flg;
+ uint8_t inner_clss_vxlan;
+ uint8_t inner_clss_l2gre;
+ uint8_t inner_clss_l2geneve;
+ uint8_t inner_rss;
+ __le16 vxlan_dst_port;
+ __le16 geneve_dst_port;
+ uint8_t sd_vlan_force_pri_change_flg;
+ uint8_t sd_vlan_force_pri_flg;
+ uint8_t sd_vlan_force_pri_val;
+ uint8_t sd_vlan_tag_change_flg;
+ uint8_t sd_vlan_eth_type_change_flg;
uint8_t reserved1;
- uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */;
- uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
- uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
- uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
- uint32_t reserved3;
+ __le16 sd_vlan_tag;
+ __le16 sd_vlan_eth_type;
+ uint8_t tx_vlan_filtering_pvid_change_flg;
+ uint8_t reserved0;
+ __le32 reserved2;
};
/*
* FW version stored in the Xstorm RAM
*/
-struct fw_version
-{
+struct fw_version {
#if defined(__BIG_ENDIAN)
- uint8_t engineering /* firmware current engineering version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t major /* firmware current major version */;
+ uint8_t engineering;
+ uint8_t revision;
+ uint8_t minor;
+ uint8_t major;
#elif defined(__LITTLE_ENDIAN)
- uint8_t major /* firmware current major version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t engineering /* firmware current engineering version */;
+ uint8_t major;
+ uint8_t minor;
+ uint8_t revision;
+ uint8_t engineering;
#endif
uint32_t flags;
-#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
+#define FW_VERSION_OPTIMIZED (0x1 << 0)
#define FW_VERSION_OPTIMIZED_SHIFT 0
-#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */
+#define FW_VERSION_BIG_ENDIEN (0x1 << 1)
#define FW_VERSION_BIG_ENDIEN_SHIFT 1
-#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 1 - E1H */
+#define FW_VERSION_CHIP_VERSION (0x3 << 2)
#define FW_VERSION_CHIP_VERSION_SHIFT 2
-#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */
+#define __FW_VERSION_RESERVED (0xFFFFFFF << 4)
#define __FW_VERSION_RESERVED_SHIFT 4
};
-/*
- * GRE RSS Mode
- */
-enum gre_rss_mode
-{
- GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */,
- GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */,
- NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */,
- MAX_GRE_RSS_MODE};
-
-
-/*
- * GRE Tunnel Mode
- */
-enum gre_tunnel_type
-{
- NO_GRE_TUNNEL,
- NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */,
- L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */,
- IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */,
- MAX_GRE_TUNNEL_TYPE};
-
-
/*
* Dynamic Host-Coalescing - Driver(host) counters
*/
-struct hc_dynamic_sb_drv_counters
-{
- uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */;
+struct hc_dynamic_sb_drv_counters {
+ uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* 2 bytes. configuration/state parameters for a single protocol index
*/
-struct hc_index_data
-{
+struct hc_index_data {
#if defined(__BIG_ENDIAN)
uint8_t flags;
-#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
+#define HC_INDEX_DATA_SM_ID (0x1 << 0)
#define HC_INDEX_DATA_SM_ID_SHIFT 0
-#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
+#define HC_INDEX_DATA_HC_ENABLED (0x1 << 1)
#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
-#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1 << 2)
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
-#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
+#define HC_INDEX_DATA_RESERVE (0x1F << 3)
#define HC_INDEX_DATA_RESERVE_SHIFT 3
- uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
+ uint8_t timeout;
#elif defined(__LITTLE_ENDIAN)
- uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
+ uint8_t timeout;
uint8_t flags;
-#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
+#define HC_INDEX_DATA_SM_ID (0x1 << 0)
#define HC_INDEX_DATA_SM_ID_SHIFT 0
-#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
+#define HC_INDEX_DATA_HC_ENABLED (0x1 << 1)
#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
-#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1 << 2)
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
-#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
+#define HC_INDEX_DATA_RESERVE (0x1F << 3)
#define HC_INDEX_DATA_RESERVE_SHIFT 3
#endif
};
@@ -5784,56 +6140,53 @@ struct hc_index_data
/*
* HC state-machine
*/
-struct hc_status_block_sm
-{
+struct hc_status_block_sm {
#if defined(__BIG_ENDIAN)
uint8_t igu_seg_id;
- uint8_t igu_sb_id /* sb_id within the IGU */;
- uint8_t timer_value /* Determines the time_to_expire */;
+ uint8_t igu_sb_id;
+ uint8_t timer_value;
uint8_t __flags;
#elif defined(__LITTLE_ENDIAN)
uint8_t __flags;
- uint8_t timer_value /* Determines the time_to_expire */;
- uint8_t igu_sb_id /* sb_id within the IGU */;
+ uint8_t timer_value;
+ uint8_t igu_sb_id;
uint8_t igu_seg_id;
#endif
- uint32_t time_to_expire /* The time in which it expects to wake up */;
+ uint32_t time_to_expire;
};
/*
* hold PCI identification variables- used in various places in firmware
*/
-struct pci_entity
-{
+struct pci_entity {
#if defined(__BIG_ENDIAN)
- uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
- uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
- uint8_t vnic_id /* Virtual NIC ID (0-3) */;
- uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
+ uint8_t vf_valid;
+ uint8_t vf_id;
+ uint8_t vnic_id;
+ uint8_t pf_id;
#elif defined(__LITTLE_ENDIAN)
- uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
- uint8_t vnic_id /* Virtual NIC ID (0-3) */;
- uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
- uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
+ uint8_t pf_id;
+ uint8_t vnic_id;
+ uint8_t vf_id;
+ uint8_t vf_valid;
#endif
};
/*
* The fast-path status block meta-data, common to all chips
*/
-struct hc_sb_data
-{
- struct regpair_native host_sb_addr /* Host status block address */;
- struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */;
- struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
+struct hc_sb_data {
+ struct regpair_native host_sb_addr;
+ struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
+ struct pci_entity p_func;
#if defined(__BIG_ENDIAN)
uint8_t rsrv0;
uint8_t state;
- uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
- uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
+ uint8_t dhc_qzone_id;
+ uint8_t same_igu_sb_1b;
#elif defined(__LITTLE_ENDIAN)
- uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
- uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
+ uint8_t same_igu_sb_1b;
+ uint8_t dhc_qzone_id;
uint8_t state;
uint8_t rsrv0;
#endif
@@ -5844,8 +6197,7 @@ struct hc_sb_data
/*
* Segment types for host coaslescing
*/
-enum hc_segment
-{
+enum hc_segment {
HC_REGULAR_SEGMENT,
HC_DEFAULT_SEGMENT,
MAX_HC_SEGMENT};
@@ -5854,59 +6206,64 @@ enum hc_segment
/*
* The fast-path status block meta-data
*/
-struct hc_sp_status_block_data
-{
- struct regpair_native host_sb_addr /* Host status block address */;
+struct hc_sp_status_block_data {
+ struct regpair_native host_sb_addr;
#if defined(__BIG_ENDIAN)
uint8_t rsrv1;
uint8_t state;
- uint8_t igu_seg_id /* segment id of the IGU */;
- uint8_t igu_sb_id /* sb_id within the IGU */;
+ uint8_t igu_seg_id;
+ uint8_t igu_sb_id;
#elif defined(__LITTLE_ENDIAN)
- uint8_t igu_sb_id /* sb_id within the IGU */;
- uint8_t igu_seg_id /* segment id of the IGU */;
+ uint8_t igu_sb_id;
+ uint8_t igu_seg_id;
uint8_t state;
uint8_t rsrv1;
#endif
- struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
+ struct pci_entity p_func;
};
/*
* The fast-path status block meta-data
*/
-struct hc_status_block_data_e1x
-{
- struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */;
- struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
+struct hc_status_block_data_e1x {
+ struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
+ struct hc_sb_data common;
};
/*
* The fast-path status block meta-data
*/
-struct hc_status_block_data_e2
-{
- struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */;
- struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
+struct hc_status_block_data_e2 {
+ struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
+ struct hc_sb_data common;
};
/*
* IGU block operartion modes (in Everest2)
*/
-enum igu_mode
-{
- HC_IGU_BC_MODE /* Backward compatible mode */,
- HC_IGU_NBC_MODE /* Non-backward compatible mode */,
+enum igu_mode {
+ HC_IGU_BC_MODE,
+ HC_IGU_NBC_MODE,
MAX_IGU_MODE};
+/*
+ * Inner Headers Classification Type
+ */
+enum inner_clss_type {
+ INNER_CLSS_DISABLED,
+ INNER_CLSS_USE_VLAN,
+ INNER_CLSS_USE_VNI,
+ MAX_INNER_CLSS_TYPE};
+
+
/*
* IP versions
*/
-enum ip_ver
-{
+enum ip_ver {
IP_V4,
IP_V6,
MAX_IP_VER};
@@ -5915,131 +6272,122 @@ enum ip_ver
/*
* Malicious VF error ID
*/
-enum malicious_vf_error_id
-{
- VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */,
- ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */,
- ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */,
- ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */,
- ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,
- ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */,
- ETH_TOO_MANY_BDS /* Tx packet has too many BDs */,
- ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */,
- ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */,
- ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */,
- ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */,
- ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */,
- ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */,
- ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */,
+enum malicious_vf_error_id {
+ MALICIOUS_VF_NO_ERROR,
+ VF_PF_CHANNEL_NOT_READY,
+ ETH_ILLEGAL_BD_LENGTHS,
+ ETH_PACKET_TOO_SHORT,
+ ETH_PAYLOAD_TOO_BIG,
+ ETH_ILLEGAL_ETH_TYPE,
+ ETH_ILLEGAL_LSO_HDR_LEN,
+ ETH_TOO_MANY_BDS,
+ ETH_ZERO_HDR_NBDS,
+ ETH_START_BD_NOT_SET,
+ ETH_ILLEGAL_PARSE_NBDS,
+ ETH_IPV6_AND_CHECKSUM,
+ ETH_VLAN_FLG_INCORRECT,
+ ETH_ILLEGAL_LSO_MSS,
+ ETH_TUNNEL_NOT_SUPPORTED,
MAX_MALICIOUS_VF_ERROR_ID};
/*
* Multi-function modes
*/
-enum mf_mode
-{
+enum mf_mode {
SINGLE_FUNCTION,
- MULTI_FUNCTION_SD /* Switch dependent (vlan based) */,
- MULTI_FUNCTION_SI /* Switch independent (mac based) */,
- MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */,
+ MULTI_FUNCTION_SD,
+ MULTI_FUNCTION_SI,
+ MULTI_FUNCTION_AFEX,
MAX_MF_MODE};
/*
- * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per pf)
*/
-struct tstorm_per_pf_stats
-{
- struct regpair rcv_error_bytes /* number of bytes received with errors */;
+struct tstorm_per_pf_stats {
+ struct regpair rcv_error_bytes;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_pf_stats
-{
+struct per_pf_stats {
struct tstorm_per_pf_stats tstorm_pf_statistics;
};
/*
- * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per port)
*/
-struct tstorm_per_port_stats
-{
- uint32_t mac_discard /* number of packets with mac errors */;
- uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */;
- uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */;
- uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */;
- uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */;
- uint32_t reserved;
+struct tstorm_per_port_stats {
+ __le32 mac_discard;
+ __le32 mac_filter_discard;
+ __le32 brb_truncate_discard;
+ __le32 mf_tag_discard;
+ __le32 packet_drop;
+ __le32 reserved;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_port_stats
-{
+struct per_port_stats {
struct tstorm_per_port_stats tstorm_port_statistics;
};
/*
- * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per client)
*/
-struct tstorm_per_queue_stats
-{
- struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */;
- uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */;
- uint32_t checksum_discard /* number of total packets received with checksum error */;
- struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */;
- uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */;
- uint32_t pkts_too_big_discard /* number of too long packets received */;
- struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */;
- uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */;
- uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;
- uint16_t no_buff_discard;
- uint16_t reserved0;
- uint32_t reserved1;
+struct tstorm_per_queue_stats {
+ struct regpair rcv_ucast_bytes;
+ __le32 rcv_ucast_pkts;
+ __le32 checksum_discard;
+ struct regpair rcv_bcast_bytes;
+ __le32 rcv_bcast_pkts;
+ __le32 pkts_too_big_discard;
+ struct regpair rcv_mcast_bytes;
+ __le32 rcv_mcast_pkts;
+ __le32 ttl0_discard;
+ __le16 no_buff_discard;
+ __le16 reserved0;
+ __le32 reserved1;
};
/*
- * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Ustorm (per client)
*/
-struct ustorm_per_queue_stats
-{
- struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */;
- struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */;
- struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */;
- uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */;
- struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */;
- uint32_t coalesced_events /* the number of aggregations */;
- uint32_t coalesced_aborts /* the number of exception which avoid aggregation */;
+struct ustorm_per_queue_stats {
+ struct regpair ucast_no_buff_bytes;
+ struct regpair mcast_no_buff_bytes;
+ struct regpair bcast_no_buff_bytes;
+ __le32 ucast_no_buff_pkts;
+ __le32 mcast_no_buff_pkts;
+ __le32 bcast_no_buff_pkts;
+ __le32 coalesced_pkts;
+ struct regpair coalesced_bytes;
+ __le32 coalesced_events;
+ __le32 coalesced_aborts;
};
/*
- * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Xstorm (per client)
*/
-struct xstorm_per_queue_stats
-{
- struct regpair ucast_bytes_sent /* number of total bytes sent without errors */;
- struct regpair mcast_bytes_sent /* number of total bytes sent without errors */;
- struct regpair bcast_bytes_sent /* number of total bytes sent without errors */;
- uint32_t ucast_pkts_sent /* number of total packets sent without errors */;
- uint32_t mcast_pkts_sent /* number of total packets sent without errors */;
- uint32_t bcast_pkts_sent /* number of total packets sent without errors */;
- uint32_t error_drop_pkts /* number of total packets drooped due to errors */;
+struct xstorm_per_queue_stats {
+ struct regpair ucast_bytes_sent;
+ struct regpair mcast_bytes_sent;
+ struct regpair bcast_bytes_sent;
+ __le32 ucast_pkts_sent;
+ __le32 mcast_pkts_sent;
+ __le32 bcast_pkts_sent;
+ __le32 error_drop_pkts;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_queue_stats
-{
+struct per_queue_stats {
struct tstorm_per_queue_stats tstorm_queue_statistics;
struct ustorm_per_queue_stats ustorm_queue_statistics;
struct xstorm_per_queue_stats xstorm_queue_statistics;
@@ -6047,24 +6395,23 @@ struct per_queue_stats
/*
- * FW version stored in first line of pram $$KEEP_ENDIANNESS$$
+ * FW version stored in first line of pram
*/
-struct pram_fw_version
-{
- uint8_t major /* firmware current major version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t engineering /* firmware current engineering version */;
+struct pram_fw_version {
+ uint8_t major;
+ uint8_t minor;
+ uint8_t revision;
+ uint8_t engineering;
uint8_t flags;
-#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
+#define PRAM_FW_VERSION_OPTIMIZED (0x1 << 0)
#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
-#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */
+#define PRAM_FW_VERSION_STORM_ID (0x3 << 1)
#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
-#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */
+#define PRAM_FW_VERSION_BIG_ENDIEN (0x1 << 3)
#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
-#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 1 - E1H */
+#define PRAM_FW_VERSION_CHIP_VERSION (0x3 << 4)
#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
-#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */
+#define __PRAM_FW_VERSION_RESERVED0 (0x3 << 6)
#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
};
@@ -6072,107 +6419,98 @@ struct pram_fw_version
/*
* Ethernet slow path element
*/
-union protocol_common_specific_data
-{
- uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
- struct regpair phy_address /* SPE physical address */;
- struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */;
- struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */;
+union protocol_common_specific_data {
+ uint8_t protocol_data[8];
+ struct regpair phy_address;
+ struct regpair mac_config_addr;
+ struct afex_vif_list_ramrod_data afex_vif_list_data;
};
/*
* The send queue element
*/
-struct protocol_common_spe
-{
- struct spe_hdr hdr /* SPE header */;
- union protocol_common_specific_data data /* data specific to common protocol */;
+struct protocol_common_spe {
+ struct spe_hdr hdr;
+ union protocol_common_specific_data data;
};
/*
- * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$
+ * The data for the Set Timesync Ramrod
*/
-struct set_timesync_ramrod_data
-{
- uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */;
- uint8_t offset_cmd /* Timesync Offset Command */;
- uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */;
- uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */;
- uint32_t drift_adjust_period /* Drift Adjust Period (in us) */;
- struct regpair offset_delta /* Timesync Offset Delta (in ns) */;
+struct set_timesync_ramrod_data {
+ uint8_t drift_adjust_cmd;
+ uint8_t offset_cmd;
+ uint8_t add_sub_drift_adjust_value;
+ uint8_t drift_adjust_value;
+ uint32_t drift_adjust_period;
+ struct regpair offset_delta;
};
/*
* The send queue element
*/
-struct slow_path_element
-{
- struct spe_hdr hdr /* common data for all protocols */;
- struct regpair protocol_data /* additional data specific to the protocol */;
+struct slow_path_element {
+ struct spe_hdr hdr;
+ struct regpair protocol_data;
};
/*
- * Protocol-common statistics counter $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics counter
*/
-struct stats_counter
-{
- uint16_t xstats_counter /* xstorm statistics counter */;
- uint16_t reserved0;
- uint32_t reserved1;
- uint16_t tstats_counter /* tstorm statistics counter */;
- uint16_t reserved2;
- uint32_t reserved3;
- uint16_t ustats_counter /* ustorm statistics counter */;
- uint16_t reserved4;
- uint32_t reserved5;
- uint16_t cstats_counter /* ustorm statistics counter */;
- uint16_t reserved6;
- uint32_t reserved7;
+struct stats_counter {
+ __le16 xstats_counter;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le16 tstats_counter;
+ __le16 reserved2;
+ __le32 reserved3;
+ __le16 ustats_counter;
+ __le16 reserved4;
+ __le32 reserved5;
+ __le16 cstats_counter;
+ __le16 reserved6;
+ __le32 reserved7;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct stats_query_entry
-{
+struct stats_query_entry {
uint8_t kind;
- uint8_t index /* queue index */;
- uint16_t funcID /* the func the statistic will send to */;
- uint32_t reserved;
- struct regpair address /* pxp address */;
+ uint8_t index;
+ __le16 funcID;
+ __le32 reserved;
+ struct regpair address;
};
/*
- * statistic command $$KEEP_ENDIANNESS$$
+ * statistic command
*/
-struct stats_query_cmd_group
-{
+struct stats_query_cmd_group {
struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
};
/*
- * statistic command header $$KEEP_ENDIANNESS$$
+ * statistic command header
*/
-struct stats_query_header
-{
- uint8_t cmd_num /* command number */;
+struct stats_query_header {
+ uint8_t cmd_num;
uint8_t reserved0;
- uint16_t drv_stats_counter;
- uint32_t reserved1;
- struct regpair stats_counters_addrs /* stats counter */;
+ __le16 drv_stats_counter;
+ __le32 reserved1;
+ struct regpair stats_counters_addrs;
};
/*
* Types of statistcis query entry
*/
-enum stats_query_type
-{
+enum stats_query_type {
STATS_TYPE_QUEUE,
STATS_TYPE_PORT,
STATS_TYPE_PF,
@@ -6184,8 +6522,7 @@ enum stats_query_type
/*
* Indicate of the function status block state
*/
-enum status_block_state
-{
+enum status_block_state {
SB_DISABLED,
SB_ENABLED,
SB_CLEANED,
@@ -6195,8 +6532,7 @@ enum status_block_state
/*
* Storm IDs (including attentions for IGU related enums)
*/
-enum storm_id
-{
+enum storm_id {
USTORM_ID,
CSTORM_ID,
XSTORM_ID,
@@ -6208,19 +6544,17 @@ enum storm_id
/*
* Taffic types used in ETS and flow control algorithms
*/
-enum traffic_type
-{
- LLFC_TRAFFIC_TYPE_NW /* Networking */,
- LLFC_TRAFFIC_TYPE_FCOE /* FCoE */,
- LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */,
+enum traffic_type {
+ LLFC_TRAFFIC_TYPE_NW,
+ LLFC_TRAFFIC_TYPE_FCOE,
+ LLFC_TRAFFIC_TYPE_ISCSI,
MAX_TRAFFIC_TYPE};
/*
* zone A per-queue data
*/
-struct tstorm_queue_zone_data
-{
+struct tstorm_queue_zone_data {
struct regpair reserved[4];
};
@@ -6228,8 +6562,7 @@ struct tstorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct tstorm_vf_zone_data
-{
+struct tstorm_vf_zone_data {
struct regpair reserved;
};
@@ -6237,41 +6570,87 @@ struct tstorm_vf_zone_data
/*
* Add or Subtract Value for Set Timesync Ramrod
*/
-enum ts_add_sub_value
-{
- TS_SUB_VALUE /* Subtract Value */,
- TS_ADD_VALUE /* Add Value */,
+enum ts_add_sub_value {
+ TS_SUB_VALUE,
+ TS_ADD_VALUE,
MAX_TS_ADD_SUB_VALUE};
/*
* Drift-Adjust Commands for Set Timesync Ramrod
*/
-enum ts_drift_adjust_cmd
-{
- TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */,
- TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */,
- TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */,
+enum ts_drift_adjust_cmd {
+ TS_DRIFT_ADJUST_KEEP,
+ TS_DRIFT_ADJUST_SET,
+ TS_DRIFT_ADJUST_RESET,
MAX_TS_DRIFT_ADJUST_CMD};
/*
* Offset Commands for Set Timesync Ramrod
*/
-enum ts_offset_cmd
-{
- TS_OFFSET_KEEP /* Keep Offset at current values */,
- TS_OFFSET_INC /* Increase Offset by Offset Delta */,
- TS_OFFSET_DEC /* Decrease Offset by Offset Delta */,
+enum ts_offset_cmd {
+ TS_OFFSET_KEEP,
+ TS_OFFSET_INC,
+ TS_OFFSET_DEC,
MAX_TS_OFFSET_CMD};
+/*
+ * Input for measuring Pci Latency
+ */
+struct t_measure_pci_latency_ctrl {
+ struct regpair read_addr;
+#if defined(__BIG_ENDIAN)
+ uint8_t sleep;
+ uint8_t enable;
+ uint8_t func_id;
+ uint8_t read_size;
+#elif defined(__LITTLE_ENDIAN)
+ uint8_t read_size;
+ uint8_t func_id;
+ uint8_t enable;
+ uint8_t sleep;
+#endif
+#if defined(__BIG_ENDIAN)
+ uint16_t num_meas;
+ uint8_t reserved;
+ uint8_t period_10us;
+#elif defined(__LITTLE_ENDIAN)
+ uint8_t period_10us;
+ uint8_t reserved;
+ uint16_t num_meas;
+#endif
+};
+
+
+/*
+ * Input for measuring Pci Latency
+ */
+struct t_measure_pci_latency_data {
+#if defined(__BIG_ENDIAN)
+ uint16_t max_time_ns;
+ uint16_t min_time_ns;
+#elif defined(__LITTLE_ENDIAN)
+ uint16_t min_time_ns;
+ uint16_t max_time_ns;
+#endif
+#if defined(__BIG_ENDIAN)
+ uint16_t reserved;
+ uint16_t num_reads;
+#elif defined(__LITTLE_ENDIAN)
+ uint16_t num_reads;
+ uint16_t reserved;
+#endif
+ struct regpair sum_time_ns;
+};
+
+
/*
* zone A per-queue data
*/
-struct ustorm_queue_zone_data
-{
- union ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */;
+struct ustorm_queue_zone_data {
+ struct ustorm_eth_rx_producers eth_rx_producers;
struct regpair reserved[3];
};
@@ -6279,8 +6658,7 @@ struct ustorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct ustorm_vf_zone_data
-{
+struct ustorm_vf_zone_data {
struct regpair reserved;
};
@@ -6288,15 +6666,14 @@ struct ustorm_vf_zone_data
/*
* data per VF-PF channel
*/
-struct vf_pf_channel_data
-{
+struct vf_pf_channel_data {
#if defined(__BIG_ENDIAN)
uint16_t reserved0;
- uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
- uint8_t state /* channel state (ready / waiting for ack) */;
+ uint8_t valid;
+ uint8_t state;
#elif defined(__LITTLE_ENDIAN)
- uint8_t state /* channel state (ready / waiting for ack) */;
- uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
+ uint8_t state;
+ uint8_t valid;
uint16_t reserved0;
#endif
uint32_t reserved1;
@@ -6306,18 +6683,16 @@ struct vf_pf_channel_data
/*
* State of VF-PF channel
*/
-enum vf_pf_channel_state
-{
- VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */,
- VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */,
+enum vf_pf_channel_state {
+ VF_PF_CHANNEL_STATE_READY,
+ VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
MAX_VF_PF_CHANNEL_STATE};
/*
* vif_list_rule_kind
*/
-enum vif_list_rule_kind
-{
+enum vif_list_rule_kind {
VIF_LIST_RULE_SET,
VIF_LIST_RULE_GET,
VIF_LIST_RULE_CLEAR_ALL,
@@ -6328,8 +6703,7 @@ enum vif_list_rule_kind
/*
* zone A per-queue data
*/
-struct xstorm_queue_zone_data
-{
+struct xstorm_queue_zone_data {
struct regpair reserved[4];
};
@@ -6337,10 +6711,8 @@ struct xstorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct xstorm_vf_zone_data
-{
+struct xstorm_vf_zone_data {
struct regpair reserved;
};
-
#endif /* ECORE_HSI_H */
diff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c
index 5ac22e725..ceac82815 100644
--- a/drivers/net/bnx2x/ecore_sp.c
+++ b/drivers/net/bnx2x/ecore_sp.c
@@ -3524,13 +3524,6 @@ static int ecore_setup_rss(struct bnx2x_softc *sc,
data->capabilities |=
ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
- if (ECORE_TEST_BIT(ECORE_RSS_TUNNELING, &p->rss_flags)) {
- data->udp_4tuple_dst_port_mask =
- ECORE_CPU_TO_LE16(p->tunnel_mask);
- data->udp_4tuple_dst_port_value =
- ECORE_CPU_TO_LE16(p->tunnel_value);
- }
-
/* Hashing mask */
data->rss_result_mask = p->rss_result_mask;
@@ -5088,8 +5081,6 @@ static int ecore_func_send_start(struct bnx2x_softc *sc,
rdata->sd_vlan_tag = ECORE_CPU_TO_LE16(start_params->sd_vlan_tag);
rdata->path_id = ECORE_PATH_ID(sc);
rdata->network_cos_mode = start_params->network_cos_mode;
- rdata->gre_tunnel_mode = start_params->gre_tunnel_mode;
- rdata->gre_tunnel_rss = start_params->gre_tunnel_rss;
/*
* No need for an explicit memory barrier here as long we would
@@ -5229,7 +5220,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st
rdata->dcb_enabled = tx_start_params->dcb_enabled;
rdata->dcb_version = tx_start_params->dcb_version;
- rdata->dont_add_pri_0 = tx_start_params->dont_add_pri_0;
+ rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;
for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
rdata->traffic_type_to_priority_cos[i] =
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v2 3/4] net/bnx2x: update to latest FW 7.13.11
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (8 preceding siblings ...)
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 2/4] net/bnx2x: update HSI code Rasesh Mody
@ 2019-09-19 21:11 ` Rasesh Mody
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 4/4] doc: cleanup SPDX license id usage in bnx2x guide Rasesh Mody
` (4 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-19 21:11 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, jerinj, ferruh.yigit, GR-Everest-DPDK-Dev
Use latest firmware 7.13.11.
Some of the fixes included with this FW are as following:
- Packets from a VF with pvid configured which were sent with a
different vlan were transmitted instead of being discarded.
- In some multi-function configurations, inter-PF and inter-VF
Tx switching is incorrectly enabled.
- Wrong assert code in FLR final cleanup in case it is sent not
after FLR.
- Chip may stall in very rare cases under heavy traffic with FW GRO
enabled.
- VF malicious notification error fixes.
- Default gre tunnel to IPGRE which allows proper RSS for IPGRE
packets, L2GRE traffic will reach single queue.
- Removes unnecessary internal mem config, latest FW performs this
autonomously.
Update the PMD version to 1.1.0.1.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
doc/guides/nics/bnx2x.rst | 4 +-
drivers/net/bnx2x/bnx2x.c | 40 +---
drivers/net/bnx2x/bnx2x.h | 5 +-
drivers/net/bnx2x/ecore_fw_defs.h | 252 ++++++++++++-----------
drivers/net/bnx2x/ecore_hsi.h | 2 +-
drivers/net/bnx2x/ecore_init.h | 214 ++++++++++----------
drivers/net/bnx2x/ecore_init_ops.h | 192 ++++++++----------
drivers/net/bnx2x/ecore_mfw_req.h | 11 +-
drivers/net/bnx2x/ecore_sp.c | 39 ++--
drivers/net/bnx2x/ecore_sp.h | 308 ++++++++++++++++++++++++-----
10 files changed, 640 insertions(+), 427 deletions(-)
diff --git a/doc/guides/nics/bnx2x.rst b/doc/guides/nics/bnx2x.rst
index 00e131484..d3650267f 100644
--- a/doc/guides/nics/bnx2x.rst
+++ b/doc/guides/nics/bnx2x.rst
@@ -93,9 +93,9 @@ Supported QLogic NICs
Prerequisites
-------------
-- Requires firmware version **7.2.51.0**. It is included in most of the
+- Requires firmware version **7.13.11.0**. It is included in most of the
standard Linux distros. If it is not available visit
- `linux-firmware git repository <https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/plain/bnx2x/bnx2x-e2-7.2.51.0.fw>`_
+ `linux-firmware git repository <https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/plain/bnx2x/bnx2x-e2-7.13.11.0.fw>`_
to get the required firmware.
Pre-Installation Configuration
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 7a76c308a..c1663b16a 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -29,8 +29,8 @@
#define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
#define BNX2X_PMD_VERSION_MAJOR 1
-#define BNX2X_PMD_VERSION_MINOR 0
-#define BNX2X_PMD_VERSION_REVISION 7
+#define BNX2X_PMD_VERSION_MINOR 1
+#define BNX2X_PMD_VERSION_REVISION 0
#define BNX2X_PMD_VERSION_PATCH 1
static inline const char *
@@ -5230,20 +5230,6 @@ static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
{
int i;
- if (IS_MF_SI(sc)) {
-/*
- * In switch independent mode, the TSTORM needs to accept
- * packets that failed classification, since approximate match
- * mac addresses aren't written to NIG LLH.
- */
- REG_WR8(sc,
- (BAR_TSTRORM_INTMEM +
- TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
- } else
- REG_WR8(sc,
- (BAR_TSTRORM_INTMEM +
- TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
-
/*
* Zero this manually as its initialization is currently missing
* in the initTool.
@@ -5797,15 +5783,12 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc)
VNICS_PER_PATH(sc));
/* RSS configuration object */
- ecore_init_rss_config_obj(&sc->rss_conf_obj,
- sc->fp[0].cl_id,
- sc->fp[0].index,
- SC_FUNC(sc),
- SC_FUNC(sc),
+ ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
+ sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
BNX2X_SP(sc, rss_rdata),
(rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
- ECORE_FILTER_RSS_CONF_PENDING,
- &sc->sp_state, ECORE_OBJ_TYPE_RX);
+ ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
+ ECORE_OBJ_TYPE_RX);
}
/*
@@ -5834,9 +5817,6 @@ static int bnx2x_func_start(struct bnx2x_softc *sc)
start_params->network_cos_mode = FW_WRR;
}
- start_params->gre_tunnel_mode = 0;
- start_params->gre_tunnel_rss = 0;
-
return ecore_func_state_change(sc, &func_params);
}
@@ -9650,8 +9630,8 @@ static void bnx2x_init_rte(struct bnx2x_softc *sc)
}
#define FW_HEADER_LEN 104
-#define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
-#define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
+#define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
+#define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
void bnx2x_load_firmware(struct bnx2x_softc *sc)
{
@@ -10367,7 +10347,7 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
/* clean the DMAE memory */
sc->dmae_ready = 1;
- ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
+ ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
@@ -11579,7 +11559,7 @@ static void bnx2x_reset_func(struct bnx2x_softc *sc)
ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
ilt_cli.client_num = ILT_CLIENT_TM;
- ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
+ ecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
}
/* this assumes that reset_port() called before reset_func() */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 054d95424..43c60408a 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -83,9 +83,6 @@
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif
-#ifndef ARRSIZE
-#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-#endif
#ifndef DIV_ROUND_UP
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#endif
@@ -1020,6 +1017,8 @@ struct bnx2x_pci_cap {
uint16_t addr;
};
+struct ecore_ilt;
+
struct bnx2x_vfdb;
/* Top level device private data structure. */
diff --git a/drivers/net/bnx2x/ecore_fw_defs.h b/drivers/net/bnx2x/ecore_fw_defs.h
index 5984acd94..5397a701a 100644
--- a/drivers/net/bnx2x/ecore_fw_defs.h
+++ b/drivers/net/bnx2x/ecore_fw_defs.h
@@ -13,170 +13,170 @@
#ifndef ECORE_FW_DEFS_H
#define ECORE_FW_DEFS_H
-
-#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base)
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
- (IRO[147].base + ((assertListEntry) * IRO[147].m1))
+ (IRO[151].base + ((assertListEntry) * IRO[151].m1))
#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
- (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
- IRO[153].m2))
+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
+ IRO[157].m2))
#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
- (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
- IRO[154].m2))
-#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
- (IRO[155].base + ((vfId) * IRO[155].m1))
-#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
- (IRO[156].base + ((vfId) * IRO[156].m1))
-#define CSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[150].base + ((funcId) * IRO[150].m1))
+ (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
+ IRO[158].m2))
#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
- (IRO[159].base + ((funcId) * IRO[159].m1))
+ (IRO[163].base + ((funcId) * IRO[163].m1))
#define CSTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[149].base + ((funcId) * IRO[149].m1))
+ (IRO[153].base + ((funcId) * IRO[153].m1))
#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
- (IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))
+ (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
- (IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \
- * IRO[138].m2) + ((sbId) * IRO[138].m3))
-#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
+ (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
+ * IRO[142].m2) + ((sbId) * IRO[142].m3))
+#define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
- (IRO[317].base + ((pfId) * IRO[317].m1))
+ (IRO[323].base + ((pfId) * IRO[323].m1))
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
- (IRO[318].base + ((pfId) * IRO[318].m1))
+ (IRO[324].base + ((pfId) * IRO[324].m1))
#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
- (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))
+ (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
- (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))
+ (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
- (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))
+ (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
- (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))
+ (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
- (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
-#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
(IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
+ (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
- (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))
+ (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
- (IRO[316].base + ((pfId) * IRO[316].m1))
+ (IRO[322].base + ((pfId) * IRO[322].m1))
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[308].base + ((pfId) * IRO[308].m1))
+ (IRO[314].base + ((pfId) * IRO[314].m1))
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[307].base + ((pfId) * IRO[307].m1))
+ (IRO[313].base + ((pfId) * IRO[313].m1))
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[306].base + ((pfId) * IRO[306].m1))
+ (IRO[312].base + ((pfId) * IRO[312].m1))
#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[151].base + ((funcId) * IRO[151].m1))
+ (IRO[155].base + ((funcId) * IRO[155].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
- (IRO[142].base + ((pfId) * IRO[142].m1))
+ (IRO[146].base + ((pfId) * IRO[146].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
- (IRO[143].base + ((pfId) * IRO[143].m1))
+ (IRO[147].base + ((pfId) * IRO[147].m1))
#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
- (IRO[141].base + ((pfId) * IRO[141].m1))
-#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)
+ (IRO[145].base + ((pfId) * IRO[145].m1))
+#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
- (IRO[144].base + ((pfId) * IRO[144].m1))
-#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)
+ (IRO[148].base + ((pfId) * IRO[148].m1))
+#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
- (IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))
+ (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
- (IRO[133].base + ((sbId) * IRO[133].m1))
+ (IRO[137].base + ((sbId) * IRO[137].m1))
#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
- (IRO[134].base + ((sbId) * IRO[134].m1))
+ (IRO[138].base + ((sbId) * IRO[138].m1))
#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
- (IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))
+ (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
- (IRO[132].base + ((sbId) * IRO[132].m1))
-#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)
+ (IRO[136].base + ((sbId) * IRO[136].m1))
+#define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
- (IRO[137].base + ((sbId) * IRO[137].m1))
-#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)
+ (IRO[141].base + ((sbId) * IRO[141].m1))
+#define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
+#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
+ (IRO[159].base + ((vfId) * IRO[159].m1))
+#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
+ (IRO[160].base + ((vfId) * IRO[160].m1))
#define CSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[150].base + ((funcId) * IRO[150].m1))
-#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base)
+ (IRO[154].base + ((funcId) * IRO[154].m1))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
- (IRO[203].base + ((pfId) * IRO[203].m1))
+ (IRO[207].base + ((pfId) * IRO[207].m1))
#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[101].base + ((assertListEntry) * IRO[101].m1))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
- (IRO[201].base + ((pfId) * IRO[201].m1))
+ (IRO[205].base + ((pfId) * IRO[205].m1))
#define TSTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[103].base + ((funcId) * IRO[103].m1))
+ (IRO[107].base + ((funcId) * IRO[107].m1))
#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
- (IRO[272].base + ((pfId) * IRO[272].m1))
+ (IRO[278].base + ((pfId) * IRO[278].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
+ (IRO[279].base + ((pfId) * IRO[279].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
+ (IRO[280].base + ((pfId) * IRO[280].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
+ (IRO[281].base + ((pfId) * IRO[281].m1))
#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[271].base + ((pfId) * IRO[271].m1))
+ (IRO[277].base + ((pfId) * IRO[277].m1))
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[270].base + ((pfId) * IRO[270].m1))
+ (IRO[276].base + ((pfId) * IRO[276].m1))
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[269].base + ((pfId) * IRO[269].m1))
+ (IRO[275].base + ((pfId) * IRO[275].m1))
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
- (IRO[268].base + ((pfId) * IRO[268].m1))
+ (IRO[274].base + ((pfId) * IRO[274].m1))
#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
- (IRO[278].base + ((pfId) * IRO[278].m1))
+ (IRO[284].base + ((pfId) * IRO[284].m1))
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
- (IRO[264].base + ((pfId) * IRO[264].m1))
+ (IRO[270].base + ((pfId) * IRO[270].m1))
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[265].base + ((pfId) * IRO[265].m1))
+ (IRO[271].base + ((pfId) * IRO[271].m1))
#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[266].base + ((pfId) * IRO[266].m1))
+ (IRO[272].base + ((pfId) * IRO[272].m1))
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[267].base + ((pfId) * IRO[267].m1))
+ (IRO[273].base + ((pfId) * IRO[273].m1))
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
- (IRO[202].base + ((pfId) * IRO[202].m1))
+ (IRO[206].base + ((pfId) * IRO[206].m1))
#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[105].base + ((funcId) * IRO[105].m1))
+ (IRO[109].base + ((funcId) * IRO[109].m1))
#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
- (IRO[217].base + ((pfId) * IRO[217].m1))
+ (IRO[223].base + ((pfId) * IRO[223].m1))
#define TSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[104].base + ((funcId) * IRO[104].m1))
-#define USTORM_AGG_DATA_OFFSET (IRO[206].base)
-#define USTORM_AGG_DATA_SIZE (IRO[206].size)
-#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base)
+ (IRO[108].base + ((funcId) * IRO[108].m1))
+#define USTORM_AGG_DATA_OFFSET (IRO[212].base)
+#define USTORM_AGG_DATA_SIZE (IRO[212].size)
+#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
- (IRO[176].base + ((assertListEntry) * IRO[176].m1))
-#define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \
- (IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * IRO[205].m2))
+ (IRO[180].base + ((assertListEntry) * IRO[180].m1))
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
- (IRO[183].base + ((portId) * IRO[183].m1))
+ (IRO[187].base + ((portId) * IRO[187].m1))
#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
- (IRO[319].base + ((pfId) * IRO[319].m1))
+ (IRO[325].base + ((pfId) * IRO[325].m1))
#define USTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[178].base + ((funcId) * IRO[178].m1))
+ (IRO[182].base + ((funcId) * IRO[182].m1))
#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
- (IRO[283].base + ((pfId) * IRO[283].m1))
+ (IRO[289].base + ((pfId) * IRO[289].m1))
#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
- (IRO[284].base + ((pfId) * IRO[284].m1))
+ (IRO[290].base + ((pfId) * IRO[290].m1))
#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
- (IRO[288].base + ((pfId) * IRO[288].m1))
+ (IRO[294].base + ((pfId) * IRO[294].m1))
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
- (IRO[285].base + ((pfId) * IRO[285].m1))
+ (IRO[291].base + ((pfId) * IRO[291].m1))
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[281].base + ((pfId) * IRO[281].m1))
+ (IRO[287].base + ((pfId) * IRO[287].m1))
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[280].base + ((pfId) * IRO[280].m1))
+ (IRO[286].base + ((pfId) * IRO[286].m1))
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[279].base + ((pfId) * IRO[279].m1))
+ (IRO[285].base + ((pfId) * IRO[285].m1))
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
- (IRO[282].base + ((pfId) * IRO[282].m1))
+ (IRO[288].base + ((pfId) * IRO[288].m1))
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
- (IRO[286].base + ((pfId) * IRO[286].m1))
+ (IRO[292].base + ((pfId) * IRO[292].m1))
#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
- (IRO[287].base + ((pfId) * IRO[287].m1))
+ (IRO[293].base + ((pfId) * IRO[293].m1))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
- (IRO[182].base + ((pfId) * IRO[182].m1))
+ (IRO[186].base + ((pfId) * IRO[186].m1))
#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[180].base + ((funcId) * IRO[180].m1))
+ (IRO[184].base + ((funcId) * IRO[184].m1))
#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
- (IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \
- IRO[209].m2))
+ (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
+ IRO[215].m2))
#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
- (IRO[210].base + ((qzoneId) * IRO[210].m1))
-#define USTORM_TPA_BTR_OFFSET (IRO[207].base)
-#define USTORM_TPA_BTR_SIZE (IRO[207].size)
+ (IRO[216].base + ((qzoneId) * IRO[216].m1))
+#define USTORM_TPA_BTR_OFFSET (IRO[213].base)
+#define USTORM_TPA_BTR_SIZE (IRO[213].size)
#define USTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[179].base + ((funcId) * IRO[179].m1))
+ (IRO[183].base + ((funcId) * IRO[183].m1))
#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
@@ -189,39 +189,39 @@
#define XSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[47].base + ((funcId) * IRO[47].m1))
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
- (IRO[296].base + ((pfId) * IRO[296].m1))
+ (IRO[302].base + ((pfId) * IRO[302].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
- (IRO[299].base + ((pfId) * IRO[299].m1))
+ (IRO[305].base + ((pfId) * IRO[305].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
- (IRO[300].base + ((pfId) * IRO[300].m1))
+ (IRO[306].base + ((pfId) * IRO[306].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
- (IRO[301].base + ((pfId) * IRO[301].m1))
+ (IRO[307].base + ((pfId) * IRO[307].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
- (IRO[302].base + ((pfId) * IRO[302].m1))
+ (IRO[308].base + ((pfId) * IRO[308].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
- (IRO[303].base + ((pfId) * IRO[303].m1))
+ (IRO[309].base + ((pfId) * IRO[309].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
- (IRO[304].base + ((pfId) * IRO[304].m1))
+ (IRO[310].base + ((pfId) * IRO[310].m1))
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
- (IRO[305].base + ((pfId) * IRO[305].m1))
+ (IRO[311].base + ((pfId) * IRO[311].m1))
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[295].base + ((pfId) * IRO[295].m1))
+ (IRO[301].base + ((pfId) * IRO[301].m1))
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[294].base + ((pfId) * IRO[294].m1))
+ (IRO[300].base + ((pfId) * IRO[300].m1))
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[293].base + ((pfId) * IRO[293].m1))
+ (IRO[299].base + ((pfId) * IRO[299].m1))
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
- (IRO[298].base + ((pfId) * IRO[298].m1))
+ (IRO[304].base + ((pfId) * IRO[304].m1))
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
- (IRO[297].base + ((pfId) * IRO[297].m1))
+ (IRO[303].base + ((pfId) * IRO[303].m1))
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
- (IRO[292].base + ((pfId) * IRO[292].m1))
+ (IRO[298].base + ((pfId) * IRO[298].m1))
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
- (IRO[291].base + ((pfId) * IRO[291].m1))
+ (IRO[297].base + ((pfId) * IRO[297].m1))
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
- (IRO[290].base + ((pfId) * IRO[290].m1))
+ (IRO[296].base + ((pfId) * IRO[296].m1))
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
- (IRO[289].base + ((pfId) * IRO[289].m1))
+ (IRO[295].base + ((pfId) * IRO[295].m1))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
(IRO[44].base + ((pfId) * IRO[44].m1))
#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
@@ -234,15 +234,18 @@
#define XSTORM_SPQ_PROD_OFFSET(funcId) \
(IRO[31].base + ((funcId) * IRO[31].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
- (IRO[211].base + ((portId) * IRO[211].m1))
+ (IRO[217].base + ((portId) * IRO[217].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
- (IRO[212].base + ((portId) * IRO[212].m1))
+ (IRO[218].base + ((portId) * IRO[218].m1))
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
- (IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \
- IRO[214].m2))
+ (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
+ IRO[220].m2))
#define XSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[48].base + ((funcId) * IRO[48].m1))
-#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base)
+#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+
+/* eth hsi version */
+#define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)
/* Ethernet Ring parameters */
@@ -250,19 +253,27 @@
#define FIRST_BD_IN_PKT 0
#define PARSE_BD_INDEX 1
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
+#define U_ETH_NUM_OF_SGES_TO_FETCH 8
+#define U_ETH_MAX_SGES_FOR_PACKET 3
/* Rx ring params */
#define U_ETH_LOCAL_BD_RING_SIZE 8
+#define U_ETH_LOCAL_SGE_RING_SIZE 10
#define U_ETH_SGL_SIZE 8
/* The fw will padd the buffer with this value, so the IP header \
will be align to 4 Byte */
#define IP_HEADER_ALIGNMENT_PADDING 2
+#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
+
#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
#define U_ETH_UNDEFINED_Q 0xFF
@@ -281,20 +292,25 @@
#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
/* Maximal L2 clients supported */
+#define ETH_MAX_RX_CLIENTS_E1 18
#define ETH_MAX_RX_CLIENTS_E1H 28
#define ETH_MAX_RX_CLIENTS_E2 152
/* Maximal statistics client Ids */
+#define MAX_STAT_COUNTER_ID_E1 36
#define MAX_STAT_COUNTER_ID_E1H 56
#define MAX_STAT_COUNTER_ID_E2 140
+#define MAX_MAC_CREDIT_E1 192 /* Per Chip */
#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
#define MAX_MAC_CREDIT_E2 272 /* Per Path */
+#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */
#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
#define MAX_VLAN_CREDIT_E2 272 /* Per Path */
/* Maximal aggregation queues supported */
+#define ETH_MAX_AGGREGATION_QUEUES_E1 32
#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
@@ -302,6 +318,8 @@
#define ETH_NUM_OF_MCAST_ENGINES_E2 72
#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
+#define ETH_MIN_RX_CQES_WITH_TPA_E1 \
+ (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)
#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
(ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
@@ -357,6 +375,7 @@
/* used for Host Coallescing */
#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
+#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
@@ -370,7 +389,7 @@
#define MAX_COS_NUMBER 4
#define MAX_TRAFFIC_TYPES 8
#define MAX_PFC_PRIORITIES 8
-
+#define MAX_VLAN_PRIORITIES 8
/* used by array traffic_type_to_priority[] to mark traffic type \
that is not mapped to priority*/
#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
@@ -397,5 +416,4 @@
#define MAX_NUM_FCOE_TASKS_PER_ENGINE \
4096 /*Each port can have at max 1 function*/
-
#endif /* ECORE_FW_DEFS_H */
diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index 2728deb1d..aaf8b048e 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -5508,7 +5508,7 @@ struct afex_vif_list_ramrod_data {
*
*/
struct c2s_pri_trans_table_entry {
- uint8_t val[8];
+ uint8_t val[MAX_VLAN_PRIORITIES];
};
diff --git a/drivers/net/bnx2x/ecore_init.h b/drivers/net/bnx2x/ecore_init.h
index 97dfe69b5..4e348612a 100644
--- a/drivers/net/bnx2x/ecore_init.h
+++ b/drivers/net/bnx2x/ecore_init.h
@@ -26,10 +26,6 @@ enum {
OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */
OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
- OP_IF_PHASE,
- OP_RT,
- OP_DELAY,
- OP_VERIFY,
OP_MAX
};
@@ -86,17 +82,6 @@ struct op_if_mode {
uint32_t mode_bit_map;
};
-struct op_if_phase {
- uint32_t op:8;
- uint32_t cmd_offset:24;
- uint32_t phase_bit_map;
-};
-
-struct op_delay {
- uint32_t op:8;
- uint32_t reserved:24;
- uint32_t delay;
-};
union init_op {
struct op_read read;
@@ -105,8 +90,6 @@ union init_op {
struct op_zero zero;
struct raw_op raw;
struct op_if_mode if_mode;
- struct op_if_phase if_phase;
- struct op_delay delay;
};
@@ -187,12 +170,7 @@ enum {
NUM_OF_INIT_BLOCKS
};
-
-
-
-
-
-
+#include "bnx2x.h"
/* Vnics per mode */
#define ECORE_PORT2_MODE_NUM_VNICS 4
@@ -239,7 +217,7 @@ static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint3
/* update parameters for 4port mode */
if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
- if (PORT_ID(sc)) {
+ if (SC_PORT(sc)) {
curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
}
@@ -248,7 +226,7 @@ static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint3
/* change queue mapping for each VNIC */
for (vnic = 0; vnic < num_vnics; vnic++) {
uint32_t pf_q_num =
- ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
+ ECORE_PF_Q_NUM(q_num, SC_PORT(sc), vnic);
uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
/* overwrite queue->VOQ mapping */
@@ -427,7 +405,11 @@ static inline void ecore_init_min(const struct cmng_init_input *input_data,
tFair = T_FAIR_COEF / input_data->port_rate;
/* this is the threshold below which we won't arm the timer anymore */
- pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
+ pdata->fair_vars.fair_threshold = QM_ARB_BYTES +
+ input_data->fairness_thr;
+
+ /*New limitation - minimal packet size to cause timeout to be armed */
+ pdata->fair_vars.size_thr = input_data->size_thr;
/*
* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
@@ -469,6 +451,7 @@ static inline void ecore_init_min(const struct cmng_init_input *input_data,
}
static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
+ uint32_t r_param __rte_unused,
struct cmng_init *ram_data)
{
uint32_t vnic, cos;
@@ -507,7 +490,9 @@ static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
}
}
-static inline void ecore_init_safc(struct cmng_init *ram_data)
+static inline void
+ecore_init_safc(const struct cmng_init_input *input_data __rte_unused,
+ struct cmng_init *ram_data)
{
/* in microSeconds */
ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
@@ -518,7 +503,7 @@ static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
struct cmng_init *ram_data)
{
uint32_t r_param;
- ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
+ ECORE_MEMSET(ram_data, 0, sizeof(struct cmng_init));
ram_data->port.flags = input_data->flags;
@@ -529,8 +514,8 @@ static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
r_param = BITS_TO_BYTES(input_data->port_rate);
ecore_init_max(input_data, r_param, ram_data);
ecore_init_min(input_data, r_param, ram_data);
- ecore_init_fw_wrr(input_data, ram_data);
- ecore_init_safc(ram_data);
+ ecore_init_fw_wrr(input_data, r_param, ram_data);
+ ecore_init_safc(input_data, ram_data);
}
@@ -585,25 +570,25 @@ struct src_ent {
/****************************************************************************
* Parity configuration
****************************************************************************/
-#define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK, \
block##_REG_##block##_PRTY_STS_CLR, \
- en_mask, {m1h, m2, m3}, #block \
+ en_mask, {m1, m1h, m2, m3}, #block \
}
-#define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK_0, \
block##_REG_##block##_PRTY_STS_CLR_0, \
- en_mask, {m1h, m2, m3}, #block"_0" \
+ en_mask, {m1, m1h, m2, m3}, #block "_0" \
}
-#define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK_1, \
block##_REG_##block##_PRTY_STS_CLR_1, \
- en_mask, {m1h, m2, m3}, #block"_1" \
+ en_mask, {m1, m1h, m2, m3}, #block "_1" \
}
static const struct {
@@ -611,6 +596,7 @@ static const struct {
uint32_t sts_clr_addr;
uint32_t en_mask; /* Mask to enable parity attentions */
struct {
+ uint32_t e1; /* 57710 */
uint32_t e1h; /* 57711 */
uint32_t e2; /* 57712 */
uint32_t e3; /* 578xx */
@@ -620,63 +606,67 @@ static const struct {
*/
} ecore_blocks_parity_data[] = {
/* bit 19 masked */
- /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
+ /* REG_WR(sc, PXP_REG_PXP_PRTY_MASK, 0x80000); */
/* bit 5,18,20-31 */
- /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
+ /* REG_WR(sc, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
/* bit 5 */
- /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
- /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
- /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
+ /* REG_WR(sc, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
+ /* REG_WR(sc, HC_REG_HC_PRTY_MASK, 0x0); */
+ /* REG_WR(sc, MISC_REG_MISC_PRTY_MASK, 0x0); */
/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
* want to handle "system kill" flow at the moment.
*/
- BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,
+ BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
0x7ffffff),
- BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff,
+ BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff),
- BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),
- BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),
- BLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),
- BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0xff, 0xffff),
- BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
- BLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),
- BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),
- BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),
- BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
+ BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
+ BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
+ BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
+ BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
+ BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
+ BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
+ BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
+ BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
+ BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
- {0xf, 0xf, 0xf}, "UPB"},
+ {0xf, 0xf, 0xf, 0xf}, "UPB"},
{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
- {0xf, 0xf, 0xf}, "XPB"},
- BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
- BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),
- BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
- BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
- BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
- BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
- BLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),
- BLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),
- BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
- BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),
- BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),
+ {0xf, 0xf, 0xf, 0xf}, "XPB"},
+ BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
+ BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
+ BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
+ BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
+ BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
+ BLOCK_PRTY_INFO(PRS, (1 << 6), 0xff, 0xff, 0xff, 0xff),
+ BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
+ BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
+ BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
+ BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
+ BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
};
@@ -685,45 +675,59 @@ static const struct {
* [30] MCP Latched ump_tx_parity
* [31] MCP Latched scpad_parity
*/
-#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
+#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
+
+#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
+ (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
/* Below registers control the MCP parity attention output. When
* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
* enabled, when cleared - disabled.
*/
-static const uint32_t mcp_attn_ctl_regs[] = {
- MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
- MISC_REG_AEU_ENABLE4_NIG_0,
- MISC_REG_AEU_ENABLE4_PXP_0,
- MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
- MISC_REG_AEU_ENABLE4_NIG_1,
- MISC_REG_AEU_ENABLE4_PXP_1
+static const struct {
+ uint32_t addr;
+ uint32_t bits;
+} mcp_attn_ctl_regs[] = {
+ { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
+ MISC_AEU_ENABLE_MCP_PRTY_BITS },
+ { MISC_REG_AEU_ENABLE4_NIG_0,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_PXP_0,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
+ MISC_AEU_ENABLE_MCP_PRTY_BITS },
+ { MISC_REG_AEU_ENABLE4_NIG_1,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_PXP_1,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
};
static inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable)
{
- uint32_t i;
+ unsigned int i;
uint32_t reg_val;
- for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
- reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);
+ for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
+ reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);
if (enable)
- reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
+ reg_val |= mcp_attn_ctl_regs[i].bits;
else
- reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
+ reg_val &= ~mcp_attn_ctl_regs[i].bits;
- REG_WR(sc, mcp_attn_ctl_regs[i], reg_val);
+ REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val);
}
}
static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
{
- if (CHIP_IS_E1H(sc))
+ if (CHIP_IS_E1(sc))
+ return ecore_blocks_parity_data[idx].reg_mask.e1;
+ else if (CHIP_IS_E1H(sc))
return ecore_blocks_parity_data[idx].reg_mask.e1h;
else if (CHIP_IS_E2(sc))
return ecore_blocks_parity_data[idx].reg_mask.e2;
@@ -733,9 +737,9 @@ static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
if (dis_mask) {
@@ -748,7 +752,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
}
/* Disable MCP parity attentions */
- ecore_set_mcp_parity(sc, FALSE);
+ ecore_set_mcp_parity(sc, false);
}
/**
@@ -756,7 +760,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
*/
static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
uint32_t reg_val, mcp_aeu_bits =
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
@@ -769,7 +773,7 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
if (reg_mask) {
@@ -799,9 +803,9 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
if (reg_mask)
@@ -810,7 +814,7 @@ static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
}
/* Enable MCP parity attentions */
- ecore_set_mcp_parity(sc, TRUE);
+ ecore_set_mcp_parity(sc, true);
}
diff --git a/drivers/net/bnx2x/ecore_init_ops.h b/drivers/net/bnx2x/ecore_init_ops.h
index 733ad1aa8..0945e7999 100644
--- a/drivers/net/bnx2x/ecore_init_ops.h
+++ b/drivers/net/bnx2x/ecore_init_ops.h
@@ -28,16 +28,19 @@ static void ecore_init_str_wr(struct bnx2x_softc *sc, uint32_t addr,
REG_WR(sc, addr + i*4, data[i]);
}
-static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len)
+static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr,
+ uint32_t len, uint8_t wb __rte_unused)
{
if (DMAE_READY(sc))
ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
- else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
}
static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,
- uint32_t len)
+ uint32_t len, uint8_t wb)
{
uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
uint32_t buf_len32 = buf_len/4;
@@ -48,7 +51,7 @@ static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,
for (i = 0; i < len; i += buf_len32) {
uint32_t cur_len = min(buf_len32, len - i);
- ecore_write_big_buf(sc, addr + i*4, cur_len);
+ ecore_write_big_buf(sc, addr + i * 4, cur_len, wb);
}
}
@@ -57,7 +60,9 @@ static void ecore_write_big_buf_wb(struct bnx2x_softc *sc, uint32_t addr, uint32
if (DMAE_READY(sc))
ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
- else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
}
static void ecore_init_wr_64(struct bnx2x_softc *sc, uint32_t addr,
@@ -135,9 +140,12 @@ static void ecore_init_wr_wb(struct bnx2x_softc *sc, uint32_t addr,
if (DMAE_READY(sc))
VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
- else ecore_init_str_wr(sc, addr, data, len);
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, data, len);
}
+
static void ecore_wr_64(struct bnx2x_softc *sc, uint32_t reg, uint32_t val_lo,
uint32_t val_hi)
{
@@ -215,11 +223,14 @@ static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t st
ecore_init_wr_wb(sc, addr, data, len);
break;
case OP_ZR:
+ ecore_init_fill(sc, addr, 0, op->zero.len, 0);
+ break;
case OP_WB_ZR:
- ecore_init_fill(sc, addr, 0, op->zero.len);
+ ecore_init_fill(sc, addr, 0, op->zero.len, 1);
break;
case OP_ZP:
- ecore_init_wr_zp(sc, addr, len, op->arr_wr.data_off);
+ ecore_init_wr_zp(sc, addr, len,
+ op->arr_wr.data_off);
break;
case OP_WR_64:
ecore_init_wr_64(sc, addr, data, len);
@@ -241,11 +252,6 @@ static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t st
op->if_mode.mode_bit_map) == 0)
op_idx += op->if_mode.cmd_offset;
break;
- /* the following opcodes are unused at the moment. */
- case OP_IF_PHASE:
- case OP_RT:
- case OP_DELAY:
- case OP_VERIFY:
default:
/* Should never get here! */
@@ -490,7 +496,7 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
- if (CHIP_IS_E1H(sc) && (r_order == MAX_RD_ORD))
+ if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))
REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
if (CHIP_IS_E3(sc))
@@ -500,31 +506,33 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
else
REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
- /* MPS w_order optimal TH presently TH
- * 128 0 0 2
- * 256 1 1 3
- * >=512 2 2 3
- */
- /* DMAE is special */
- if (!CHIP_IS_E1H(sc)) {
- /* E2 can use optimal TH */
- val = w_order;
- REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
- } else {
- val = ((w_order == 0) ? 2 : 3);
- REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
- }
+ if (!CHIP_IS_E1(sc)) {
+ /* MPS w_order optimal TH presently TH
+ * 128 0 0 2
+ * 256 1 1 3
+ * >=512 2 2 3
+ */
+ /* DMAE is special */
+ if (!CHIP_IS_E1H(sc)) {
+ /* E2 can use optimal TH */
+ val = w_order;
+ REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
+ } else {
+ val = ((w_order == 0) ? 2 : 3);
+ REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
+ }
- REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
- REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
- REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
- REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
+ }
/* Validate number of tags suppoted by device */
#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
@@ -559,18 +567,15 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
#define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
#define ILT_RANGE(f, l) (((l) << 10) | f)
-static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,
- struct ilt_line *line, uint32_t size, uint8_t memop, int cli_num, int i)
+static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc __rte_unused,
+ struct ilt_line *line, uint32_t size,
+ uint8_t memop)
{
-#define ECORE_ILT_NAMESIZE 10
- char str[ECORE_ILT_NAMESIZE];
-
if (memop == ILT_MEMOP_FREE) {
ECORE_ILT_FREE(line->page, line->page_mapping, line->size);
return 0;
}
- snprintf(str, ECORE_ILT_NAMESIZE, "ILT_%d_%d", cli_num, i);
- ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size, str);
+ ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size);
if (!line->page)
return -1;
line->size = size;
@@ -581,7 +586,7 @@ static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,
static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,
uint8_t memop)
{
- int i, rc = 0;
+ int i, rc;
struct ecore_ilt *ilt = SC_ILT(sc);
struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
@@ -591,25 +596,13 @@ static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,
if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
return 0;
- for (i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
+ for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],
- ilt_cli->page_size, memop, cli_num, i);
+ ilt_cli->page_size, memop);
}
return rc;
}
-static inline int ecore_ilt_mem_op_cnic(struct bnx2x_softc *sc, uint8_t memop)
-{
- int rc = 0;
-
- if (CONFIGURE_NIC_MODE(sc))
- rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
- if (!rc)
- rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);
-
- return rc;
-}
-
static int ecore_ilt_mem_op(struct bnx2x_softc *sc, uint8_t memop)
{
int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);
@@ -626,7 +619,10 @@ static void ecore_ilt_line_wr(struct bnx2x_softc *sc, int abs_idx,
{
uint32_t reg;
- reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
+ if (CHIP_IS_E1(sc))
+ reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx * 8;
+ else
+ reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx * 8;
ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
}
@@ -637,6 +633,7 @@ static void ecore_ilt_line_init_op(struct bnx2x_softc *sc,
ecore_dma_addr_t null_mapping;
int abs_idx = ilt->start_line + idx;
+
switch (initop) {
case INITOP_INIT:
/* set in the init-value array */
@@ -650,9 +647,10 @@ static void ecore_ilt_line_init_op(struct bnx2x_softc *sc,
}
}
-static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
- struct ilt_client_info *ilt_cli,
- uint32_t ilt_start)
+static void ecore_ilt_boundary_init_op(struct bnx2x_softc *sc,
+ struct ilt_client_info *ilt_cli,
+ uint32_t ilt_start,
+ uint8_t initop __rte_unused)
{
uint32_t start_reg = 0;
uint32_t end_reg = 0;
@@ -661,7 +659,26 @@ static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
CLEAR => SET and for now SET ~~ INIT */
/* find the appropriate regs */
- switch (ilt_cli->client_num) {
+ if (CHIP_IS_E1(sc)) {
+ switch (ilt_cli->client_num) {
+ case ILT_CLIENT_CDU:
+ start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
+ break;
+ case ILT_CLIENT_QM:
+ start_reg = PXP2_REG_PSWRQ_QM0_L2P;
+ break;
+ case ILT_CLIENT_SRC:
+ start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
+ break;
+ case ILT_CLIENT_TM:
+ start_reg = PXP2_REG_PSWRQ_TM0_L2P;
+ break;
+ }
+ REG_WR(sc, start_reg + SC_FUNC(sc) * 4,
+ ILT_RANGE((ilt_start + ilt_cli->start),
+ (ilt_start + ilt_cli->end)));
+ } else {
+ switch (ilt_cli->client_num) {
case ILT_CLIENT_CDU:
start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
@@ -678,9 +695,10 @@ static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
end_reg = PXP2_REG_RQ_TM_LAST_ILT;
break;
+ }
+ REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
+ REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
}
- REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
- REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
}
static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,
@@ -697,7 +715,7 @@ static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,
ecore_ilt_line_init_op(sc, ilt, i, initop);
/* init/clear the ILT boundries */
- ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line);
+ ecore_ilt_boundary_init_op(sc, ilt_cli, ilt->start_line, initop);
}
static void ecore_ilt_client_init_op(struct bnx2x_softc *sc,
@@ -717,13 +735,6 @@ static void ecore_ilt_client_id_init_op(struct bnx2x_softc *sc,
ecore_ilt_client_init_op(sc, ilt_cli, initop);
}
-static inline void ecore_ilt_init_op_cnic(struct bnx2x_softc *sc, uint8_t initop)
-{
- if (CONFIGURE_NIC_MODE(sc))
- ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
- ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);
-}
-
static void ecore_ilt_init_op(struct bnx2x_softc *sc, uint8_t initop)
{
ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);
@@ -771,7 +782,7 @@ static void ecore_ilt_init_page_size(struct bnx2x_softc *sc, uint8_t initop)
/****************************************************************************
* QM initializations
****************************************************************************/
-#define QM_QUEUES_PER_FUNC 16
+#define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
#define QM_INIT_MIN_CID_COUNT 31
#define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
@@ -831,33 +842,4 @@ static void ecore_qm_init_ptr_table(struct bnx2x_softc *sc, int qm_cid_count,
}
}
-/****************************************************************************
-* SRC initializations
-****************************************************************************/
-#ifdef ECORE_L5
-/* called during init func stage */
-static void ecore_src_init_t2(struct bnx2x_softc *sc, struct src_ent *t2,
- ecore_dma_addr_t t2_mapping, int src_cid_count)
-{
- int i;
- int port = SC_PORT(sc);
-
- /* Initialize T2 */
- for (i = 0; i < src_cid_count-1; i++)
- t2[i].next = (uint64_t)(t2_mapping +
- (i+1)*sizeof(struct src_ent));
-
- /* tell the searcher where the T2 table is */
- REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
-
- ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,
- U64_LO(t2_mapping), U64_HI(t2_mapping));
-
- ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,
- U64_LO((uint64_t)t2_mapping +
- (src_cid_count-1) * sizeof(struct src_ent)),
- U64_HI((uint64_t)t2_mapping +
- (src_cid_count-1) * sizeof(struct src_ent)));
-}
-#endif
#endif /* ECORE_INIT_OPS_H */
diff --git a/drivers/net/bnx2x/ecore_mfw_req.h b/drivers/net/bnx2x/ecore_mfw_req.h
index fe9450481..4ffd9daf7 100644
--- a/drivers/net/bnx2x/ecore_mfw_req.h
+++ b/drivers/net/bnx2x/ecore_mfw_req.h
@@ -14,7 +14,6 @@
#define ECORE_MFW_REQ_H
-
#define PORT_0 0
#define PORT_1 1
#define PORT_MAX 2
@@ -143,6 +142,15 @@ struct iscsi_stats_info {
uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
/* QoS Priority (per 802.1p). 0-7255 */
uint32_t qos_priority;
+#define ISCSI_QOS_PRIORITY_OFFSET 0
+#define ISCSI_QOS_PRIORITY_MASK (0xffff)
+
+#define ISCSI_IP_ADDRESS_TYPE_OFFSET 30
+#define ISCSI_IP_ADDRESS_TYPE_MASK (3 << 30)
+/* Driver does not have the IP address and type populated */
+#define ISCSI_IP_ADDRESS_TYPE_NOT_SET (0 << 30)
+#define ISCSI_IP_ADDRESS_TYPE_IPV4 (1 << 30) /* IPV4 IP address set */
+#define ISCSI_IP_ADDRESS_TYPE_IPV6 (2 << 30) /* IPV6 IP address set */
uint8_t initiator_name[64]; /* iSCSI Boot Initiator Node name. */
@@ -181,5 +189,4 @@ union drv_info_to_mcp {
struct iscsi_stats_info iscsi_stat;
};
-
#endif /* ECORE_MFW_REQ_H */
diff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c
index ceac82815..b9bca9115 100644
--- a/drivers/net/bnx2x/ecore_sp.c
+++ b/drivers/net/bnx2x/ecore_sp.c
@@ -501,7 +501,7 @@ static int __ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc __rte_unused,
*
* @details May sleep. Claims and releases execution queue lock during its run.
*/
-static int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
+int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *o)
{
int rc;
@@ -712,7 +712,7 @@ static uint8_t ecore_vlan_mac_get_rx_tx_flag(struct ecore_vlan_mac_obj
return rx_tx_flag;
}
-static void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
+void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
int add, unsigned char *dev_addr, int index)
{
uint32_t wb_data[2];
@@ -2764,12 +2764,16 @@ static int ecore_mcast_validate_e2(__rte_unused struct bnx2x_softc *sc,
static void ecore_mcast_revert_e2(__rte_unused struct bnx2x_softc *sc,
struct ecore_mcast_ramrod_params *p,
- int old_num_bins)
+ int old_num_bins,
+ enum ecore_mcast_cmd cmd)
{
struct ecore_mcast_obj *o = p->mcast_obj;
o->set_registry_size(o, old_num_bins);
o->total_pending_num -= p->mcast_list_len;
+
+ if (cmd == ECORE_MCAST_CMD_SET)
+ o->total_pending_num -= o->max_cmd_len;
}
/**
@@ -2915,7 +2919,8 @@ static int ecore_mcast_validate_e1h(__rte_unused struct bnx2x_softc *sc,
static void ecore_mcast_revert_e1h(__rte_unused struct bnx2x_softc *sc,
__rte_unused struct ecore_mcast_ramrod_params
- *p, __rte_unused int old_num_bins)
+ *p, __rte_unused int old_num_bins,
+ __rte_unused enum ecore_mcast_cmd cmd)
{
/* Do nothing */
}
@@ -3093,7 +3098,7 @@ int ecore_config_mcast(struct bnx2x_softc *sc,
r->clear_pending(r);
error_exit1:
- o->revert(sc, p, old_reg_size);
+ o->revert(sc, p, old_reg_size, cmd);
return rc;
}
@@ -3350,7 +3355,7 @@ static int ecore_credit_pool_get_entry_always_TRUE(__rte_unused struct
* If credit is negative pool operations will always succeed (unlimited pool).
*
*/
-static void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
+void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
int base, int credit)
{
/* Zero the object first */
@@ -3588,11 +3593,13 @@ int ecore_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *p)
return rc;
}
-void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
+void ecore_init_rss_config_obj(struct bnx2x_softc *sc __rte_unused,
+ struct ecore_rss_config_obj *rss_obj,
uint8_t cl_id, uint32_t cid, uint8_t func_id,
- uint8_t engine_id, void *rdata,
- ecore_dma_addr_t rdata_mapping, int state,
- unsigned long *pstate, ecore_obj_type type)
+ uint8_t engine_id,
+ void *rdata, ecore_dma_addr_t rdata_mapping,
+ int state, unsigned long *pstate,
+ ecore_obj_type type)
{
ecore_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,
rdata_mapping, state, pstate, type);
@@ -5107,8 +5114,14 @@ static int ecore_func_send_switch_update(struct bnx2x_softc *sc, struct ecore_fu
ECORE_MEMSET(rdata, 0, sizeof(*rdata));
/* Fill the ramrod data with provided parameters */
- rdata->tx_switch_suspend_change_flg = 1;
- rdata->tx_switch_suspend = switch_update_params->suspend;
+ if (ECORE_TEST_BIT(ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+ &switch_update_params->changes)) {
+ rdata->tx_switch_suspend_change_flg = 1;
+ rdata->tx_switch_suspend =
+ ECORE_TEST_BIT(ECORE_F_UPDATE_TX_SWITCH_SUSPEND,
+ &switch_update_params->changes);
+ }
+
rdata->echo = SWITCH_UPDATE;
return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
@@ -5220,7 +5233,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st
rdata->dcb_enabled = tx_start_params->dcb_enabled;
rdata->dcb_version = tx_start_params->dcb_version;
- rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;
+ rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en;
for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
rdata->traffic_type_to_priority_cos[i] =
diff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h
index fce715b6d..cc1db377a 100644
--- a/drivers/net/bnx2x/ecore_sp.h
+++ b/drivers/net/bnx2x/ecore_sp.h
@@ -135,16 +135,16 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
#define SC_ILT(sc) ((sc)->ilt)
#define ILOG2(x) bnx2x_ilog2(x)
-#define ECORE_ILT_ZALLOC(x, y, size, str) \
+#define ECORE_ILT_ZALLOC(x, y, size) \
do { \
x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \
if (x) { \
if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
size, (struct bnx2x_dma *)x, \
- str, RTE_CACHE_LINE_SIZE) != 0) { \
+ "ILT", RTE_CACHE_LINE_SIZE) != 0) { \
rte_free(x); \
x = NULL; \
- *y = 0; \
+ *(y) = 0; \
} else { \
*y = ((struct bnx2x_dma *)x)->paddr; \
} \
@@ -161,7 +161,7 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
} \
} while (0)
-#define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE
+#define ECORE_IS_VALID_ETHER_ADDR(_mac) true
#define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE
#define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE
@@ -238,11 +238,11 @@ typedef struct ecore_list_t
(_list)->cnt = 0; \
} while (0)
-/* return TRUE if the element is the last on the list */
+/* return true if the element is the last on the list */
#define ECORE_LIST_IS_LAST(_elem, _list) \
(_elem == (_list)->tail)
-/* return TRUE if the list is empty */
+/* return true if the list is empty */
#define ECORE_LIST_IS_EMPTY(_list) \
((_list)->cnt == 0)
@@ -413,9 +413,6 @@ enum {
AFEX_UPDATE,
};
-
-
-
struct bnx2x_softc;
struct eth_context;
@@ -461,11 +458,18 @@ enum {
ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
ECORE_FILTER_FCOE_ETH_START_SCHED,
ECORE_FILTER_FCOE_ETH_STOP_SCHED,
+#ifdef ECORE_CHAR_DEV
+ ECORE_FILTER_BYPASS_RX_MODE_PENDING,
+ ECORE_FILTER_BYPASS_MAC_PENDING,
+ ECORE_FILTER_BYPASS_RSS_CONF_PENDING,
+#endif
ECORE_FILTER_MCAST_PENDING,
ECORE_FILTER_MCAST_SCHED,
ECORE_FILTER_RSS_CONF_PENDING,
ECORE_AFEX_FCOE_Q_UPDATE_PENDING,
- ECORE_AFEX_PENDING_VIFSET_MCP_ACK
+ ECORE_AFEX_PENDING_VIFSET_MCP_ACK,
+ ECORE_FILTER_VXLAN_PENDING,
+ ECORE_FILTER_PVLAN_PENDING
};
struct ecore_raw_obj {
@@ -488,7 +492,7 @@ struct ecore_raw_obj {
int (*wait_comp)(struct bnx2x_softc *sc,
struct ecore_raw_obj *o);
- int (*check_pending)(struct ecore_raw_obj *o);
+ bool (*check_pending)(struct ecore_raw_obj *o);
void (*clear_pending)(struct ecore_raw_obj *o);
void (*set_pending)(struct ecore_raw_obj *o);
};
@@ -509,10 +513,16 @@ struct ecore_vlan_mac_ramrod_data {
uint16_t vlan;
};
+struct ecore_vxlan_fltr_ramrod_data {
+ uint8_t innermac[ETH_ALEN];
+ uint32_t vni;
+};
+
union ecore_classification_ramrod_data {
struct ecore_mac_ramrod_data mac;
struct ecore_vlan_ramrod_data vlan;
struct ecore_vlan_mac_ramrod_data vlan_mac;
+ struct ecore_vxlan_fltr_ramrod_data vxlan_fltr;
};
/* VLAN_MAC commands */
@@ -541,6 +551,7 @@ union ecore_exe_queue_cmd_data {
struct ecore_vlan_mac_data vlan_mac;
struct {
+ /* TODO */
} mcast;
};
@@ -642,7 +653,7 @@ struct ecore_vlan_mac_registry_elem {
ecore_list_entry_t link;
/* Used to store the cam offset used for the mac/vlan/vlan-mac.
- * Relevant for 57711 only. VLANs and MACs share the
+ * Relevant for 57710 and 57711 only. VLANs and MACs share the
* same CAM for these chips.
*/
int cam_offset;
@@ -659,9 +670,18 @@ enum {
ECORE_ETH_MAC,
ECORE_ISCSI_ETH_MAC,
ECORE_NETQ_ETH_MAC,
+ ECORE_VLAN,
ECORE_DONT_CONSUME_CAM_CREDIT,
ECORE_DONT_CONSUME_CAM_CREDIT_DEST,
};
+/* When looking for matching filters, some flags are not interesting */
+#define ECORE_VLAN_MAC_CMP_MASK (1 << ECORE_UC_LIST_MAC | \
+ 1 << ECORE_ETH_MAC | \
+ 1 << ECORE_ISCSI_ETH_MAC | \
+ 1 << ECORE_NETQ_ETH_MAC | \
+ 1 << ECORE_VLAN)
+#define ECORE_VLAN_MAC_CMP_FLAGS(flags) \
+ ((flags) & ECORE_VLAN_MAC_CMP_MASK)
struct ecore_vlan_mac_ramrod_params {
/* Object to run the command from */
@@ -685,7 +705,7 @@ struct ecore_vlan_mac_obj {
* all these fields should only be accessed under the exe_queue lock
*/
uint8_t head_reader; /* Num. of readers accessing head list */
- int head_exe_request; /* Pending execution request. */
+ bool head_exe_request; /* Pending execution request. */
unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
/* Execution queue interface instance */
@@ -728,7 +748,7 @@ struct ecore_vlan_mac_obj {
/**
* Checks if DEL-ramrod with the given params may be performed.
*
- * @return TRUE if the element may be deleted
+ * @return true if the element may be deleted
*/
struct ecore_vlan_mac_registry_elem *
(*check_del)(struct bnx2x_softc *sc,
@@ -738,9 +758,9 @@ struct ecore_vlan_mac_obj {
/**
* Checks if DEL-ramrod with the given params may be performed.
*
- * @return TRUE if the element may be deleted
+ * @return true if the element may be deleted
*/
- int (*check_move)(struct bnx2x_softc *sc,
+ bool (*check_move)(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *src_o,
struct ecore_vlan_mac_obj *dst_o,
union ecore_classification_ramrod_data *data);
@@ -749,10 +769,10 @@ struct ecore_vlan_mac_obj {
* Update the relevant credit object(s) (consume/return
* correspondingly).
*/
- int (*get_credit)(struct ecore_vlan_mac_obj *o);
- int (*put_credit)(struct ecore_vlan_mac_obj *o);
- int (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
- int (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
+ bool (*get_credit)(struct ecore_vlan_mac_obj *o);
+ bool (*put_credit)(struct ecore_vlan_mac_obj *o);
+ bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
+ bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
/**
* Configures one rule in the ramrod data buffer.
@@ -838,6 +858,9 @@ enum {
ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
};
+void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
+ bool add, unsigned char *dev_addr, int index);
+
/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
/* RX_MODE ramrod special flags: set in rx_mode_flags field in
@@ -898,7 +921,7 @@ struct ecore_mcast_list_elem {
union ecore_mcast_config_data {
uint8_t *mac;
- uint8_t bin; /* used in a RESTORE flow */
+ uint8_t bin; /* used in a RESTORE/SET flows */
};
struct ecore_mcast_ramrod_params {
@@ -908,6 +931,14 @@ struct ecore_mcast_ramrod_params {
unsigned long ramrod_flags;
ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */
+ /** TODO:
+ * - rename it to macs_num.
+ * - Add a new command type for handling pending commands
+ * (remove "zero semantics").
+ *
+ * Length of mcast_list. If zero and ADD_CONT command - post
+ * pending commands.
+ */
int mcast_list_len;
};
@@ -916,6 +947,15 @@ enum ecore_mcast_cmd {
ECORE_MCAST_CMD_CONT,
ECORE_MCAST_CMD_DEL,
ECORE_MCAST_CMD_RESTORE,
+
+ /* Following this, multicast configuration should equal to approx
+ * the set of MACs provided [i.e., remove all else].
+ * The two sub-commands are used internally to decide whether a given
+ * bin is to be added or removed
+ */
+ ECORE_MCAST_CMD_SET,
+ ECORE_MCAST_CMD_SET_ADD,
+ ECORE_MCAST_CMD_SET_DEL,
};
struct ecore_mcast_obj {
@@ -989,14 +1029,14 @@ struct ecore_mcast_obj {
/** Checks if there are more mcast MACs to be set or a previous
* command is still pending.
*/
- int (*check_pending)(struct ecore_mcast_obj *o);
+ bool (*check_pending)(struct ecore_mcast_obj *o);
/**
* Set/Clear/Check SCHEDULED state of the object
*/
void (*set_sched)(struct ecore_mcast_obj *o);
void (*clear_sched)(struct ecore_mcast_obj *o);
- int (*check_sched)(struct ecore_mcast_obj *o);
+ bool (*check_sched)(struct ecore_mcast_obj *o);
/* Wait until all pending commands complete */
int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o);
@@ -1015,7 +1055,8 @@ struct ecore_mcast_obj {
*/
void (*revert)(struct bnx2x_softc *sc,
struct ecore_mcast_ramrod_params *p,
- int old_num_bins);
+ int old_num_bins,
+ enum ecore_mcast_cmd cmd);
int (*get_registry_size)(struct ecore_mcast_obj *o);
void (*set_registry_size)(struct ecore_mcast_obj *o, int n);
@@ -1045,33 +1086,33 @@ struct ecore_credit_pool_obj {
/**
* Get the next free pool entry.
*
- * @return TRUE if there was a free entry in the pool
+ * @return true if there was a free entry in the pool
*/
- int (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
+ bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
/**
* Return the entry back to the pool.
*
- * @return TRUE if entry is legal and has been successfully
+ * @return true if entry is legal and has been successfully
* returned to the pool.
*/
- int (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
+ bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
/**
* Get the requested amount of credit from the pool.
*
* @param cnt Amount of requested credit
- * @return TRUE if the operation is successful
+ * @return true if the operation is successful
*/
- int (*get)(struct ecore_credit_pool_obj *o, int cnt);
+ bool (*get)(struct ecore_credit_pool_obj *o, int cnt);
/**
* Returns the credit to the pool.
*
* @param cnt Amount of credit to return
- * @return TRUE if the operation is successful
+ * @return true if the operation is successful
*/
- int (*put)(struct ecore_credit_pool_obj *o, int cnt);
+ bool (*put)(struct ecore_credit_pool_obj *o, int cnt);
/**
* Reads the current amount of credit.
@@ -1094,7 +1135,9 @@ enum {
ECORE_RSS_IPV6_TCP,
ECORE_RSS_IPV6_UDP,
- ECORE_RSS_TUNNELING,
+ ECORE_RSS_IPV4_VXLAN,
+ ECORE_RSS_IPV6_VXLAN,
+ ECORE_RSS_TUNN_INNER_HDRS,
};
struct ecore_config_rss_params {
@@ -1117,10 +1160,6 @@ struct ecore_config_rss_params {
/* valid only if ECORE_RSS_UPDATE_TOE is set */
uint16_t toe_rss_bitmap;
-
- /* valid if ECORE_RSS_TUNNELING is set */
- uint16_t tunnel_value;
- uint16_t tunnel_mask;
};
struct ecore_rss_config_obj {
@@ -1158,6 +1197,8 @@ enum {
ECORE_Q_UPDATE_SILENT_VLAN_REM,
ECORE_Q_UPDATE_TX_SWITCHING_CHNG,
ECORE_Q_UPDATE_TX_SWITCHING,
+ ECORE_Q_UPDATE_PTP_PKTS_CHNG,
+ ECORE_Q_UPDATE_PTP_PKTS,
};
/* Allowed Queue states */
@@ -1222,12 +1263,16 @@ enum {
ECORE_Q_FLG_FORCE_DEFAULT_PRI,
ECORE_Q_FLG_REFUSE_OUTBAND_VLAN,
ECORE_Q_FLG_PCSUM_ON_PKT,
- ECORE_Q_FLG_TUN_INC_INNER_IP_ID
+ ECORE_Q_FLG_TUN_INC_INNER_IP_ID,
+ ECORE_Q_FLG_TPA_VLAN_DIS,
};
/* Queue type options: queue type may be a combination of below. */
enum ecore_q_type {
ECORE_Q_TYPE_FWD,
+ /** TODO: Consider moving both these flags into the init()
+ * ramrod params.
+ */
ECORE_Q_TYPE_HAS_RX,
ECORE_Q_TYPE_HAS_TX,
};
@@ -1238,6 +1283,10 @@ enum ecore_q_type {
#define ECORE_MULTI_TX_COS_E3B0 3
#define ECORE_MULTI_TX_COS 3 /* Maximum possible */
#define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)
+/* DMAE channel to be used by FW for timesync workaroun. A driver that sends
+ * timesync-related ramrods must not use this DMAE command ID.
+ */
+#define FW_DMAE_CMD_ID 6
struct ecore_queue_init_params {
struct {
@@ -1280,6 +1329,26 @@ struct ecore_queue_update_params {
uint8_t cid_index;
};
+struct ecore_queue_update_tpa_params {
+ ecore_dma_addr_t sge_map;
+ uint8_t update_ipv4;
+ uint8_t update_ipv6;
+ uint8_t max_tpa_queues;
+ uint8_t max_sges_pkt;
+ uint8_t complete_on_both_clients;
+ uint8_t dont_verify_thr;
+ uint8_t tpa_mode;
+ uint8_t _pad;
+
+ uint16_t sge_buff_sz;
+ uint16_t max_agg_sz;
+
+ uint16_t sge_pause_thr_low;
+ uint16_t sge_pause_thr_high;
+
+ uint8_t disable_tpa_over_vlan;
+};
+
struct rxq_pause_params {
uint16_t bd_th_lo;
uint16_t bd_th_hi;
@@ -1298,11 +1367,14 @@ struct ecore_general_setup_params {
uint8_t spcl_id;
uint16_t mtu;
uint8_t cos;
+
+ uint8_t fp_hsi;
};
struct ecore_rxq_setup_params {
/* dma */
ecore_dma_addr_t dscr_map;
+ ecore_dma_addr_t sge_map;
ecore_dma_addr_t rcq_map;
ecore_dma_addr_t rcq_np_map;
@@ -1313,6 +1385,8 @@ struct ecore_rxq_setup_params {
/* valid if ECORE_Q_FLG_TPA */
uint16_t tpa_agg_sz;
+ uint16_t sge_buf_sz;
+ uint8_t max_sges_pkt;
uint8_t max_tpa_queues;
uint8_t rss_engine_id;
@@ -1323,7 +1397,7 @@ struct ecore_rxq_setup_params {
uint8_t sb_cq_index;
- /* valid if BXN2X_Q_FLG_SILENT_VLAN_REM */
+ /* valid if ECORE_Q_FLG_SILENT_VLAN_REM */
uint16_t silent_removal_value;
uint16_t silent_removal_mask;
};
@@ -1371,6 +1445,7 @@ struct ecore_queue_state_params {
/* Params according to the current command */
union {
struct ecore_queue_update_params update;
+ struct ecore_queue_update_tpa_params update_tpa;
struct ecore_queue_setup_params setup;
struct ecore_queue_init_params init;
struct ecore_queue_setup_tx_only_params tx_only;
@@ -1450,6 +1525,24 @@ struct ecore_queue_sp_obj {
};
/********************** Function state update *********************************/
+
+/* UPDATE command options */
+enum {
+ ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+ ECORE_F_UPDATE_TX_SWITCH_SUSPEND,
+ ECORE_F_UPDATE_SD_VLAN_TAG_CHNG,
+ ECORE_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
+ ECORE_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
+ ECORE_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
+ ECORE_F_UPDATE_TUNNEL_CFG_CHNG,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
+ ECORE_F_UPDATE_TUNNEL_INNER_RSS,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN_INNER_VNI,
+ ECORE_F_UPDATE_VLAN_FILTERING_PVID_CHNG,
+};
+
/* Allowed Function states */
enum ecore_func_state {
ECORE_F_STATE_RESET,
@@ -1470,6 +1563,7 @@ enum ecore_func_cmd {
ECORE_F_CMD_TX_STOP,
ECORE_F_CMD_TX_START,
ECORE_F_CMD_SWITCH_UPDATE,
+ ECORE_F_CMD_SET_TIMESYNC,
ECORE_F_CMD_MAX,
};
@@ -1511,19 +1605,60 @@ struct ecore_func_start_params {
/* Function cos mode */
uint8_t network_cos_mode;
- /* NVGRE classification enablement */
- uint8_t nvgre_clss_en;
+ /* DMAE command id to be used for FW DMAE transactions */
+ uint8_t dmae_cmd_id;
+
+ /* UDP dest port for VXLAN */
+ uint16_t vxlan_dst_port;
+
+ /* UDP dest port for Geneve */
+ uint16_t geneve_dst_port;
+
+ /* Enable inner Rx classifications for L2GRE packets */
+ uint8_t inner_clss_l2gre;
+
+ /* Enable inner Rx classifications for L2-Geneve packets */
+ uint8_t inner_clss_l2geneve;
+
+ /* Enable inner Rx classification for vxlan packets */
+ uint8_t inner_clss_vxlan;
+
+ /* Enable RSS according to inner header */
+ uint8_t inner_rss;
+
+ /** Allows accepting of packets failing MF classification, possibly
+ * only matching a given ethertype
+ */
+ uint8_t class_fail;
+ uint16_t class_fail_ethtype;
+
+ /* Override priority of output packets */
+ uint8_t sd_vlan_force_pri;
+ uint8_t sd_vlan_force_pri_val;
+
+ /* Replace vlan's ethertype */
+ uint16_t sd_vlan_eth_type;
- /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
- uint8_t gre_tunnel_mode;
+ /* Prevent inner vlans from being added by FW */
+ uint8_t no_added_tags;
- /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
- uint8_t gre_tunnel_rss;
+ /* Inner-to-Outer vlan priority mapping */
+ uint8_t c2s_pri[MAX_VLAN_PRIORITIES];
+ uint8_t c2s_pri_default;
+ uint8_t c2s_pri_valid;
+ /* TX Vlan filtering configuration */
+ uint8_t tx_vlan_filtering_enable;
+ uint8_t tx_vlan_filtering_use_pvid;
};
struct ecore_func_switch_update_params {
- uint8_t suspend;
+ unsigned long changes; /* ECORE_F_UPDATE_XX bits */
+ uint16_t vlan;
+ uint16_t vlan_eth_type;
+ uint8_t vlan_force_prio;
+ uint16_t vxlan_dst_port;
+ uint16_t geneve_dst_port;
};
struct ecore_func_afex_update_params {
@@ -1538,11 +1673,28 @@ struct ecore_func_afex_viflists_params {
uint8_t afex_vif_list_command;
uint8_t func_to_clear;
};
+
struct ecore_func_tx_start_params {
struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
uint8_t dcb_enabled;
uint8_t dcb_version;
- uint8_t dont_add_pri_0;
+ uint8_t dont_add_pri_0_en;
+ uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];
+};
+
+struct ecore_func_set_timesync_params {
+ /* Reset, set or keep the current drift value */
+ uint8_t drift_adjust_cmd;
+ /* Dec, inc or keep the current offset */
+ uint8_t offset_cmd;
+ /* Drift value direction */
+ uint8_t add_sub_drift_adjust_value;
+ /* Drift, period and offset values to be used according to the commands
+ * above.
+ */
+ uint8_t drift_adjust_value;
+ uint32_t drift_adjust_period;
+ uint64_t offset_delta;
};
struct ecore_func_state_params {
@@ -1563,6 +1715,7 @@ struct ecore_func_state_params {
struct ecore_func_afex_update_params afex_update;
struct ecore_func_afex_viflists_params afex_viflists;
struct ecore_func_tx_start_params tx_start;
+ struct ecore_func_set_timesync_params set_timesync;
} params;
};
@@ -1583,6 +1736,10 @@ struct ecore_func_sp_drv_ops {
void (*reset_hw_port)(struct bnx2x_softc *sc);
void (*reset_hw_func)(struct bnx2x_softc *sc);
+ /* Init/Free GUNZIP resources */
+ int (*gunzip_init)(struct bnx2x_softc *sc);
+ void (*gunzip_end)(struct bnx2x_softc *sc);
+
/* Prepare/Release FW resources */
int (*init_fw)(struct bnx2x_softc *sc);
void (*release_fw)(struct bnx2x_softc *sc);
@@ -1669,6 +1826,9 @@ void ecore_init_queue_obj(struct bnx2x_softc *sc,
int ecore_queue_state_change(struct bnx2x_softc *sc,
struct ecore_queue_state_params *params);
+int ecore_get_q_logical_state(struct bnx2x_softc *sc,
+ struct ecore_queue_sp_obj *obj);
+
/********************* VLAN-MAC ****************/
void ecore_init_mac_obj(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *mac_obj,
@@ -1677,6 +1837,34 @@ void ecore_init_mac_obj(struct bnx2x_softc *sc,
unsigned long *pstate, ecore_obj_type type,
struct ecore_credit_pool_obj *macs_pool);
+void ecore_init_vlan_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id,
+ void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+void ecore_init_vlan_mac_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_mac_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id,
+ void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *macs_pool,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+void ecore_init_vxlan_fltr_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_mac_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id,
+ void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *macs_pool,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *o);
void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *o);
int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc,
@@ -1719,7 +1907,7 @@ void ecore_init_mcast_obj(struct bnx2x_softc *sc,
/**
* ecore_config_mcast - Configure multicast MACs list.
*
- * @cmd: command to execute: BNX2X_MCAST_CMD_X
+ * @cmd: command to execute: ECORE_MCAST_CMD_X
*
* May configure a new list
* provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up
@@ -1747,9 +1935,12 @@ void ecore_init_mac_credit_pool(struct bnx2x_softc *sc,
void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,
struct ecore_credit_pool_obj *p, uint8_t func_id,
uint8_t func_num);
+void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
+ int base, int credit);
/****************** RSS CONFIGURATION ****************/
-void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
+void ecore_init_rss_config_obj(struct bnx2x_softc *sc,
+ struct ecore_rss_config_obj *rss_obj,
uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,
void *rdata, ecore_dma_addr_t rdata_mapping,
int state, unsigned long *pstate,
@@ -1763,5 +1954,24 @@ void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
int ecore_config_rss(struct bnx2x_softc *sc,
struct ecore_config_rss_params *p);
+/**
+ * ecore_get_rss_ind_table - Return the current ind_table configuration.
+ *
+ * @ind_table: buffer to fill with the current indirection
+ * table content. Should be at least
+ * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
+ */
+void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj,
+ uint8_t *ind_table);
+
+#define PF_MAC_CREDIT_E2(sc, func_num) \
+ ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_MAC_CREDIT_CNT) / \
+ (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT)
+
+#define PF_VLAN_CREDIT_E2(sc, func_num) \
+ ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_VLAN_CREDIT_CNT) / \
+ (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_VLAN_CREDIT_CNT)
+
+#define ECORE_PF_VLAN_CREDIT_VLAN_FILTERING 256
#endif /* ECORE_SP_H */
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v2 4/4] doc: cleanup SPDX license id usage in bnx2x guide
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (9 preceding siblings ...)
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 3/4] net/bnx2x: update to latest FW 7.13.11 Rasesh Mody
@ 2019-09-19 21:11 ` Rasesh Mody
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 0/3] net/bnx2x: update to latest FW Rasesh Mody
` (3 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-09-19 21:11 UTC (permalink / raw)
To: dev; +Cc: Rasesh Mody, jerinj, ferruh.yigit, GR-Everest-DPDK-Dev
Removed redundant BSD boilerplate text from bnx2x guide.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
doc/guides/nics/bnx2x.rst | 26 --------------------------
1 file changed, 26 deletions(-)
diff --git a/doc/guides/nics/bnx2x.rst b/doc/guides/nics/bnx2x.rst
index d3650267f..67d765af8 100644
--- a/doc/guides/nics/bnx2x.rst
+++ b/doc/guides/nics/bnx2x.rst
@@ -1,32 +1,6 @@
.. SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2015 QLogic Corporation
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in
- the documentation and/or other materials provided with the
- distribution.
- * Neither the name of QLogic Corporation nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
BNX2X Poll Mode Driver
======================
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 0/3] net/bnx2x: update to latest FW
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (10 preceding siblings ...)
2019-09-19 21:11 ` [dpdk-dev] [PATCH v2 4/4] doc: cleanup SPDX license id usage in bnx2x guide Rasesh Mody
@ 2019-10-02 19:14 ` Rasesh Mody
2019-10-03 5:57 ` Jerin Jacob
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 1/3] net/bnx2x: update and reorganize HW registers Rasesh Mody
` (2 subsequent siblings)
14 siblings, 1 reply; 29+ messages in thread
From: Rasesh Mody @ 2019-10-02 19:14 UTC (permalink / raw)
To: dev, jerinj, ferruh.yigit; +Cc: Rasesh Mody, GR-Everest-DPDK-Dev
Hi,
Currently, BNX2X PMD uses a very old firmware 7.2.51.
This patch series updated the base driver to use to latest
firmware 7.13.11. The latest firmware comprises of enhancements
and fixes.
v3:
- Addressed gcc 9.2 build issues
v2:
- Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
- Addressed most of checkpatch issues
Thanks!
-Rasesh
Rasesh Mody (3):
net/bnx2x: update and reorganize HW registers
net/bnx2x: update HSI code
net/bnx2x: update to latest FW 7.13.11
doc/guides/nics/bnx2x.rst | 4 +-
drivers/net/bnx2x/bnx2x.c | 63 +-
drivers/net/bnx2x/bnx2x.h | 95 +-
drivers/net/bnx2x/bnx2x_osal.h | 29 +
drivers/net/bnx2x/bnx2x_rxtx.c | 10 +-
drivers/net/bnx2x/ecore_fw_defs.h | 252 +-
drivers/net/bnx2x/ecore_hsi.h | 3508 ++++++++-------
drivers/net/bnx2x/ecore_init.h | 214 +-
drivers/net/bnx2x/ecore_init_ops.h | 192 +-
drivers/net/bnx2x/ecore_mfw_req.h | 11 +-
drivers/net/bnx2x/ecore_reg.h | 6617 +++++++++++++++++++---------
drivers/net/bnx2x/ecore_sp.c | 48 +-
drivers/net/bnx2x/ecore_sp.h | 308 +-
13 files changed, 7185 insertions(+), 4166 deletions(-)
create mode 100644 drivers/net/bnx2x/bnx2x_osal.h
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH v3 0/3] net/bnx2x: update to latest FW
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 0/3] net/bnx2x: update to latest FW Rasesh Mody
@ 2019-10-03 5:57 ` Jerin Jacob
2019-10-03 6:48 ` Rasesh Mody
0 siblings, 1 reply; 29+ messages in thread
From: Jerin Jacob @ 2019-10-03 5:57 UTC (permalink / raw)
To: Rasesh Mody; +Cc: dpdk-dev, Jerin Jacob, Ferruh Yigit, GR-Everest-DPDK-Dev
On Thu, Oct 3, 2019 at 12:45 AM Rasesh Mody <rmody@marvell.com> wrote:
>
> Hi,
>
> Currently, BNX2X PMD uses a very old firmware 7.2.51.
> This patch series updated the base driver to use to latest
> firmware 7.13.11. The latest firmware comprises of enhancements
> and fixes.
>
> v3:
> - Addressed gcc 9.2 build issues
> v2:
> - Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
> - Addressed most of checkpatch issues
>
> Thanks!
> -Rasesh
>
> Rasesh Mody (3):
> net/bnx2x: update and reorganize HW registers
> net/bnx2x: update HSI code
> net/bnx2x: update to latest FW 7.13.11
I don't think this patch comes as _base_ code, Please fix the trivial
and genuine check path errors.
[master][dpdk-next-net-mrvl] $ ./devtools/checkpatches.sh
### net/bnx2x: update HSI code
WARNING:TYPO_SPELLING: 'entires' may be misspelled - perhaps 'entries'?
#863: FILE: drivers/net/bnx2x/ecore_hsi.h:2844:
+ /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
total: 0 errors, 1 warnings, 0 checks, 5425 lines checked
### net/bnx2x: update to latest FW 7.13.11
CHECK:CAMELCASE: Avoid CamelCase: <assertListEntry>
#174: FILE: drivers/net/bnx2x/ecore_fw_defs.h:18:
+ (IRO[151].base + ((assertListEntry) * IRO[151].m1))
CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
#178: FILE: drivers/net/bnx2x/ecore_fw_defs.h:20:
+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
^
CHECK:SPACING: spaces preferred around that '&' (ctx:VxV)
#178: FILE: drivers/net/bnx2x/ecore_fw_defs.h:20:
+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
^
CHECK:CAMELCASE: Avoid CamelCase: <pfId>
#178: FILE: drivers/net/bnx2x/ecore_fw_defs.h:20:
+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
#189: FILE: drivers/net/bnx2x/ecore_fw_defs.h:23:
+ (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
^
CHECK:SPACING: spaces preferred around that '&' (ctx:VxV)
#189: FILE: drivers/net/bnx2x/ecore_fw_defs.h:23:
+ (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
^
CHECK:CAMELCASE: Avoid CamelCase: <funcId>
#193: FILE: drivers/net/bnx2x/ecore_fw_defs.h:26:
+ (IRO[163].base + ((funcId) * IRO[163].m1))
CHECK:CAMELCASE: Avoid CamelCase: <hcIndex>
#199: FILE: drivers/net/bnx2x/ecore_fw_defs.h:30:
+ (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
CHECK:CAMELCASE: Avoid CamelCase: <sbId>
#199: FILE: drivers/net/bnx2x/ecore_fw_defs.h:30:
+ (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
#204: FILE: drivers/net/bnx2x/ecore_fw_defs.h:32:
+ (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
^
CHECK:SPACING: spaces preferred around that '&' (ctx:VxV)
#204: FILE: drivers/net/bnx2x/ecore_fw_defs.h:32:
+ (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
CHECK:CAMELCASE: Avoid CamelCase: <iscsiEqId>
[65/1889]
#215: FILE: drivers/net/bnx2x/ecore_fw_defs.h:40:
+ (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
CHECK:CAMELCASE: Avoid CamelCase: <vfId>
#287: FILE: drivers/net/bnx2x/ecore_fw_defs.h:87:
+#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
CHECK:CAMELCASE: Avoid CamelCase: <portId>
#368: FILE: drivers/net/bnx2x/ecore_fw_defs.h:142:
+ (IRO[187].base + ((portId) * IRO[187].m1))
CHECK:CAMELCASE: Avoid CamelCase: <clientId>
#414: FILE: drivers/net/bnx2x/ecore_fw_defs.h:172:
+ (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
CHECK:CAMELCASE: Avoid CamelCase: <qzoneId>
#420: FILE: drivers/net/bnx2x/ecore_fw_defs.h:175:
+ (IRO[216].base + ((qzoneId) * IRO[216].m1))
CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
#498: FILE: drivers/net/bnx2x/ecore_fw_defs.h:241:
+ (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
^
CHECK:SPACING: spaces preferred around that '&' (ctx:VxV)
#498: FILE: drivers/net/bnx2x/ecore_fw_defs.h:241:
+ (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
^
CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#526: FILE: drivers/net/bnx2x/ecore_fw_defs.h:268:
+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
^
CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#526: FILE: drivers/net/bnx2x/ecore_fw_defs.h:268:
+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
^
CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#526: FILE: drivers/net/bnx2x/ecore_fw_defs.h:268:
+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
^
CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#530: FILE: drivers/net/bnx2x/ecore_fw_defs.h:272:
+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
^
CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#530: FILE: drivers/net/bnx2x/ecore_fw_defs.h:272:
+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
^
CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#534: FILE: drivers/net/bnx2x/ecore_fw_defs.h:276:
+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
[16/1889]
CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#530: FILE: drivers/net/bnx2x/ecore_fw_defs.h:272:
+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
^
CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#534: FILE: drivers/net/bnx2x/ecore_fw_defs.h:276:
+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
^
CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#577: FILE: drivers/net/bnx2x/ecore_fw_defs.h:378:
+#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
^
CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'r_order
== MAX_RD_ORD'
#1119: FILE: drivers/net/bnx2x/ecore_init_ops.h:499:
+ if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#1537: FILE: drivers/net/bnx2x/ecore_sp.h:138:
+#define ECORE_ILT_ZALLOC(x, y, size) \
do { \
x = rte_malloc("", sizeof(struct bnx2x_dma),
RTE_CACHE_LINE_SIZE); \
if (x) { \
if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
size, (struct bnx2x_dma *)x, \
+ "ILT", RTE_CACHE_LINE_SIZE) != 0) { \
rte_free(x); \
x = NULL; \
+ *(y) = 0; \
} else { \
*y = ((struct bnx2x_dma *)x)->paddr; \
} \
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'y' - possible side-effects?
#1537: FILE: drivers/net/bnx2x/ecore_sp.h:138:
+#define ECORE_ILT_ZALLOC(x, y, size) \
do { \
x = rte_malloc("", sizeof(struct bnx2x_dma),
RTE_CACHE_LINE_SIZE); \
if (x) { \
if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
size, (struct bnx2x_dma *)x, \
+ "ILT", RTE_CACHE_LINE_SIZE) != 0) { \
rte_free(x); \
x = NULL; \
+ *(y) = 0; \
} else { \
*y = ((struct bnx2x_dma *)x)->paddr; \
} \
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sc' - possible side-effects?
#2191: FILE: drivers/net/bnx2x/ecore_sp.h:1967:
+#define PF_MAC_CREDIT_E2(sc, func_num) \
+ ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_MAC_CREDIT_CNT) / \
+ (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sc' - possible side-effects?
>
> doc/guides/nics/bnx2x.rst | 4 +-
> drivers/net/bnx2x/bnx2x.c | 63 +-
> drivers/net/bnx2x/bnx2x.h | 95 +-
> drivers/net/bnx2x/bnx2x_osal.h | 29 +
> drivers/net/bnx2x/bnx2x_rxtx.c | 10 +-
> drivers/net/bnx2x/ecore_fw_defs.h | 252 +-
> drivers/net/bnx2x/ecore_hsi.h | 3508 ++++++++-------
> drivers/net/bnx2x/ecore_init.h | 214 +-
> drivers/net/bnx2x/ecore_init_ops.h | 192 +-
> drivers/net/bnx2x/ecore_mfw_req.h | 11 +-
> drivers/net/bnx2x/ecore_reg.h | 6617 +++++++++++++++++++---------
> drivers/net/bnx2x/ecore_sp.c | 48 +-
> drivers/net/bnx2x/ecore_sp.h | 308 +-
> 13 files changed, 7185 insertions(+), 4166 deletions(-)
> create mode 100644 drivers/net/bnx2x/bnx2x_osal.h
>
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH v3 0/3] net/bnx2x: update to latest FW
2019-10-03 5:57 ` Jerin Jacob
@ 2019-10-03 6:48 ` Rasesh Mody
2019-10-04 9:32 ` Jerin Jacob
0 siblings, 1 reply; 29+ messages in thread
From: Rasesh Mody @ 2019-10-03 6:48 UTC (permalink / raw)
To: Jerin Jacob
Cc: dpdk-dev, Jerin Jacob Kollanukkaran, Ferruh Yigit, GR-Everest-DPDK-Dev
>From: Jerin Jacob <jerinjacobk@gmail.com>
>Sent: Wednesday, October 02, 2019 10:57 PM
>
>On Thu, Oct 3, 2019 at 12:45 AM Rasesh Mody <rmody@marvell.com> wrote:
>>
>> Hi,
>>
>> Currently, BNX2X PMD uses a very old firmware 7.2.51.
>> This patch series updated the base driver to use to latest firmware
>> 7.13.11. The latest firmware comprises of enhancements and fixes.
>>
>> v3:
>> - Addressed gcc 9.2 build issues
>> v2:
>> - Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
>> - Addressed most of checkpatch issues
>>
>> Thanks!
>> -Rasesh
>>
>> Rasesh Mody (3):
>> net/bnx2x: update and reorganize HW registers
>> net/bnx2x: update HSI code
>> net/bnx2x: update to latest FW 7.13.11
>
>I don't think this patch comes as _base_ code, Please fix the trivial and
>genuine check path errors.
These are base driver changes for updating the FW to latest. The remaining checkpatch issues in this patch set are to keep uniformity and readability of the base code.
Cleaning up base code to remove these and other checkpatch issues in same context would be a separate activity(as it would result in lot more changes), independent of this patch set. Next when there is such a checkpatch code cleanup, we'll try to address the issues.
Please apply these changes or let me know if v4 is needed.
Thanks!
-Rasesh
>
>[master][dpdk-next-net-mrvl] $ ./devtools/checkpatches.sh
>
>### net/bnx2x: update HSI code
>
>WARNING:TYPO_SPELLING: 'entires' may be misspelled - perhaps 'entries'?
>#863: FILE: drivers/net/bnx2x/ecore_hsi.h:2844:
>+ /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1
>+ default */
>
>total: 0 errors, 1 warnings, 0 checks, 5425 lines checked
>
>### net/bnx2x: update to latest FW 7.13.11
>
>CHECK:CAMELCASE: Avoid CamelCase: <assertListEntry>
>#174: FILE: drivers/net/bnx2x/ecore_fw_defs.h:18:
>+ (IRO[151].base + ((assertListEntry) * IRO[151].m1))
>
>CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
>#178: FILE: drivers/net/bnx2x/ecore_fw_defs.h:20:
>+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
> ^
>
>CHECK:SPACING: spaces preferred around that '&' (ctx:VxV)
>#178: FILE: drivers/net/bnx2x/ecore_fw_defs.h:20:
>+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
> ^
>
>CHECK:CAMELCASE: Avoid CamelCase: <pfId>
>#178: FILE: drivers/net/bnx2x/ecore_fw_defs.h:20:
>+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
>
>CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
>#189: FILE: drivers/net/bnx2x/ecore_fw_defs.h:23:
>+ (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
> ^
>
>CHECK:SPACING: spaces preferred around that '&' (ctx:VxV)
>#189: FILE: drivers/net/bnx2x/ecore_fw_defs.h:23:
>+ (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
> ^
>
>CHECK:CAMELCASE: Avoid CamelCase: <funcId>
>#193: FILE: drivers/net/bnx2x/ecore_fw_defs.h:26:
>+ (IRO[163].base + ((funcId) * IRO[163].m1))
>
>CHECK:CAMELCASE: Avoid CamelCase: <hcIndex>
>#199: FILE: drivers/net/bnx2x/ecore_fw_defs.h:30:
>+ (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) *
>+ IRO[143].m2))
>
>CHECK:CAMELCASE: Avoid CamelCase: <sbId>
>#199: FILE: drivers/net/bnx2x/ecore_fw_defs.h:30:
>+ (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) *
>+ IRO[143].m2))
>
>CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
>#204: FILE: drivers/net/bnx2x/ecore_fw_defs.h:32:
>+ (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3)
>+ \
> ^
>
>CHECK:SPACING: spaces preferred around that '&' (ctx:VxV)
>#204: FILE: drivers/net/bnx2x/ecore_fw_defs.h:32:
>+ (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3)
>+ \
>
>CHECK:CAMELCASE: Avoid CamelCase: <iscsiEqId>
>
>
> [65/1889]
>#215: FILE: drivers/net/bnx2x/ecore_fw_defs.h:40:
>+ (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) *
>+ IRO[316].m2))
>
>CHECK:CAMELCASE: Avoid CamelCase: <vfId>
>#287: FILE: drivers/net/bnx2x/ecore_fw_defs.h:87:
>+#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
>
>CHECK:CAMELCASE: Avoid CamelCase: <portId>
>#368: FILE: drivers/net/bnx2x/ecore_fw_defs.h:142:
>+ (IRO[187].base + ((portId) * IRO[187].m1))
>
>CHECK:CAMELCASE: Avoid CamelCase: <clientId>
>#414: FILE: drivers/net/bnx2x/ecore_fw_defs.h:172:
>+ (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
>
>CHECK:CAMELCASE: Avoid CamelCase: <qzoneId>
>#420: FILE: drivers/net/bnx2x/ecore_fw_defs.h:175:
>+ (IRO[216].base + ((qzoneId) * IRO[216].m1))
>
>CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
>#498: FILE: drivers/net/bnx2x/ecore_fw_defs.h:241:
>+ (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
> ^
>
>CHECK:SPACING: spaces preferred around that '&' (ctx:VxV)
>#498: FILE: drivers/net/bnx2x/ecore_fw_defs.h:241:
>+ (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
> ^
>
>CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
>#526: FILE: drivers/net/bnx2x/ecore_fw_defs.h:268:
>+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
> ^
>
>CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
>#526: FILE: drivers/net/bnx2x/ecore_fw_defs.h:268:
>+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
> ^
>
>CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
>#526: FILE: drivers/net/bnx2x/ecore_fw_defs.h:268:
>+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
> ^
>
>CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
>#530: FILE: drivers/net/bnx2x/ecore_fw_defs.h:272:
>+#define U_ETH_SGES_PER_PAGE
>(PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
> ^
>
>CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
>#530: FILE: drivers/net/bnx2x/ecore_fw_defs.h:272:
>+#define U_ETH_SGES_PER_PAGE
>(PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
> ^
>
>CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
>#534: FILE: drivers/net/bnx2x/ecore_fw_defs.h:276:
>+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
>
>
>
>
> [16/1889]
>CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
>#530: FILE: drivers/net/bnx2x/ecore_fw_defs.h:272:
>+#define U_ETH_SGES_PER_PAGE
>(PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
> ^
>
>CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
>#534: FILE: drivers/net/bnx2x/ecore_fw_defs.h:276:
>+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
> ^
>
>CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
>#577: FILE: drivers/net/bnx2x/ecore_fw_defs.h:378:
>+#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
> ^
>
>CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around
>'r_order == MAX_RD_ORD'
>#1119: FILE: drivers/net/bnx2x/ecore_init_ops.h:499:
>+ if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order ==
>+ MAX_RD_ORD))
>
>CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-
>effects?
>#1537: FILE: drivers/net/bnx2x/ecore_sp.h:138:
>+#define ECORE_ILT_ZALLOC(x, y, size) \
> do { \
> x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE);
>\
> if (x) { \
> if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
> size, (struct bnx2x_dma *)x, \
>+ "ILT", RTE_CACHE_LINE_SIZE) !=
>+ 0) { \
> rte_free(x); \
> x = NULL; \
>+ *(y) = 0; \
> } else { \
> *y = ((struct bnx2x_dma *)x)->paddr; \
> } \
>
>CHECK:MACRO_ARG_REUSE: Macro argument reuse 'y' - possible side-
>effects?
>#1537: FILE: drivers/net/bnx2x/ecore_sp.h:138:
>+#define ECORE_ILT_ZALLOC(x, y, size) \
> do { \
> x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE);
>\
> if (x) { \
> if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
> size, (struct bnx2x_dma *)x, \
>+ "ILT", RTE_CACHE_LINE_SIZE) !=
>+ 0) { \
> rte_free(x); \
> x = NULL; \
>+ *(y) = 0; \
> } else { \
> *y = ((struct bnx2x_dma *)x)->paddr; \
> } \
>
>CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sc' - possible side-
>effects?
>#2191: FILE: drivers/net/bnx2x/ecore_sp.h:1967:
>+#define PF_MAC_CREDIT_E2(sc, func_num) \
>+ ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) *
>VF_MAC_CREDIT_CNT) / \
>+ (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT)
>
>CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sc' - possible side-
>effects?
>
>
>>
>> doc/guides/nics/bnx2x.rst | 4 +-
>> drivers/net/bnx2x/bnx2x.c | 63 +-
>> drivers/net/bnx2x/bnx2x.h | 95 +-
>> drivers/net/bnx2x/bnx2x_osal.h | 29 +
>> drivers/net/bnx2x/bnx2x_rxtx.c | 10 +-
>> drivers/net/bnx2x/ecore_fw_defs.h | 252 +-
>> drivers/net/bnx2x/ecore_hsi.h | 3508 ++++++++-------
>> drivers/net/bnx2x/ecore_init.h | 214 +-
>> drivers/net/bnx2x/ecore_init_ops.h | 192 +-
>> drivers/net/bnx2x/ecore_mfw_req.h | 11 +-
>> drivers/net/bnx2x/ecore_reg.h | 6617 +++++++++++++++++++---------
>> drivers/net/bnx2x/ecore_sp.c | 48 +-
>> drivers/net/bnx2x/ecore_sp.h | 308 +-
>> 13 files changed, 7185 insertions(+), 4166 deletions(-) create mode
>> 100644 drivers/net/bnx2x/bnx2x_osal.h
>>
>> --
>> 2.18.0
>>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH v3 0/3] net/bnx2x: update to latest FW
2019-10-03 6:48 ` Rasesh Mody
@ 2019-10-04 9:32 ` Jerin Jacob
0 siblings, 0 replies; 29+ messages in thread
From: Jerin Jacob @ 2019-10-04 9:32 UTC (permalink / raw)
To: Rasesh Mody
Cc: dpdk-dev, Jerin Jacob Kollanukkaran, Ferruh Yigit, GR-Everest-DPDK-Dev
On Thu, Oct 3, 2019 at 12:18 PM Rasesh Mody <rmody@marvell.com> wrote:
>
> >From: Jerin Jacob <jerinjacobk@gmail.com>
> >Sent: Wednesday, October 02, 2019 10:57 PM
> >
> >On Thu, Oct 3, 2019 at 12:45 AM Rasesh Mody <rmody@marvell.com> wrote:
> >>
> >> Hi,
> >>
> >> Currently, BNX2X PMD uses a very old firmware 7.2.51.
> >> This patch series updated the base driver to use to latest firmware
> >> 7.13.11. The latest firmware comprises of enhancements and fixes.
> >>
> >> v3:
> >> - Addressed gcc 9.2 build issues
> >> v2:
> >> - Squashed pmd version patch into "net/bnx2x: update to latest FW 7.13.11"
> >> - Addressed most of checkpatch issues
> >>
> >> Thanks!
> >> -Rasesh
> >>
> >> Rasesh Mody (3):
> >> net/bnx2x: update and reorganize HW registers
> >> net/bnx2x: update HSI code
> >> net/bnx2x: update to latest FW 7.13.11
> >
> >I don't think this patch comes as _base_ code, Please fix the trivial and
> >genuine check path errors.
>
> These are base driver changes for updating the FW to latest. The remaining checkpatch issues in this patch set are to keep uniformity and readability of the base code.
> Cleaning up base code to remove these and other checkpatch issues in same context would be a separate activity(as it would result in lot more changes), independent of this patch set. Next when there is such a checkpatch code cleanup, we'll try to address the issues.
>
> Please apply these changes or let me know if v4 is needed.
Fixed WARNING:TYPO_SPELLING warning.
Series applied to dpdk-next-net-mrvl/master. Thanks.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [dpdk-dev] [PATCH v3 1/3] net/bnx2x: update and reorganize HW registers
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (11 preceding siblings ...)
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 0/3] net/bnx2x: update to latest FW Rasesh Mody
@ 2019-10-02 19:14 ` Rasesh Mody
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 2/3] net/bnx2x: update HSI code Rasesh Mody
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 3/3] net/bnx2x: update to latest FW 7.13.11 Rasesh Mody
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-10-02 19:14 UTC (permalink / raw)
To: dev, jerinj, ferruh.yigit; +Cc: Rasesh Mody, GR-Everest-DPDK-Dev
Update and reorganize HW registers in preparation to update the firmware
to version 7.13.11.
Move HW_INTERRUT_ASSERT_SET_0 out from ecore_reg.h to bnx2x.h.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/bnx2x/bnx2x.c | 3 +-
drivers/net/bnx2x/bnx2x.h | 67 +
drivers/net/bnx2x/ecore_reg.h | 6617 ++++++++++++++++++++++-----------
3 files changed, 4553 insertions(+), 2134 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 1a088269f..d552f50e2 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -4095,7 +4095,7 @@ static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
REG_WR(sc, reg_offset, val);
rte_panic("FATAL HW block attention set0 0x%lx",
- (attn & HW_INTERRUT_ASSERT_SET_0));
+ (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
}
}
@@ -10394,7 +10394,6 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
- REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
if (!CHIP_REV_IS_SLOW(sc)) {
/* enable hw interrupt from doorbell Q */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index ceaecb031..1ea8b55c9 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -1714,6 +1714,73 @@ static const uint32_t dmae_reg_go_c[] = {
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
+#define HW_INTERRUT_ASSERT_SET_0 \
+ (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_1 \
+ (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_2 \
+ (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
+ AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
+
+#define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
+ (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
+
+#define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
+
+#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
+
#define MULTI_MASK 0x7f
#define PFS_PER_PORT(sc) \
diff --git a/drivers/net/bnx2x/ecore_reg.h b/drivers/net/bnx2x/ecore_reg.h
index 7af9a2d81..bb92d131f 100644
--- a/drivers/net/bnx2x/ecore_reg.h
+++ b/drivers/net/bnx2x/ecore_reg.h
@@ -13,2105 +13,4417 @@
#ifndef ECORE_REG_H
#define ECORE_REG_H
-
-#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \
- (0x1<<0)
-#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \
- (0x1<<2)
-#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \
- (0x1<<5)
-#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \
- (0x1<<3)
-#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \
- (0x1<<4)
-#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \
- (0x1<<1)
-#define ATC_REG_ATC_INIT_DONE \
- 0x1100bcUL
-#define ATC_REG_ATC_INT_STS_CLR \
- 0x1101c0UL
-#define ATC_REG_ATC_PRTY_MASK \
- 0x1101d8UL
-#define ATC_REG_ATC_PRTY_STS_CLR \
- 0x1101d0UL
-#define BRB1_REG_BRB1_INT_MASK \
- 0x60128UL
-#define BRB1_REG_BRB1_PRTY_MASK \
- 0x60138UL
-#define BRB1_REG_BRB1_PRTY_STS_CLR \
- 0x60130UL
-#define BRB1_REG_MAC_GUARANTIED_0 \
- 0x601e8UL
-#define BRB1_REG_MAC_GUARANTIED_1 \
- 0x60240UL
-#define BRB1_REG_NUM_OF_FULL_BLOCKS \
- 0x60090UL
-#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \
- 0x60078UL
-#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \
- 0x60068UL
-#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \
- 0x60094UL
-#define CCM_REG_CCM_INT_MASK \
- 0xd01e4UL
-#define CCM_REG_CCM_PRTY_MASK \
- 0xd01f4UL
-#define CCM_REG_CCM_PRTY_STS_CLR \
- 0xd01ecUL
-#define CDU_REG_CDU_GLOBAL_PARAMS \
- 0x101020UL
-#define CDU_REG_CDU_INT_MASK \
- 0x10103cUL
-#define CDU_REG_CDU_PRTY_MASK \
- 0x10104cUL
-#define CDU_REG_CDU_PRTY_STS_CLR \
- 0x101044UL
-#define CFC_REG_AC_INIT_DONE \
- 0x104078UL
-#define CFC_REG_CAM_INIT_DONE \
- 0x10407cUL
-#define CFC_REG_CFC_INT_MASK \
- 0x104108UL
-#define CFC_REG_CFC_INT_STS_CLR \
- 0x104100UL
-#define CFC_REG_CFC_PRTY_MASK \
- 0x104118UL
-#define CFC_REG_CFC_PRTY_STS_CLR \
- 0x104110UL
-#define CFC_REG_DEBUG0 \
- 0x104050UL
-#define CFC_REG_INIT_REG \
- 0x10404cUL
-#define CFC_REG_LL_INIT_DONE \
- 0x104074UL
-#define CFC_REG_NUM_LCIDS_INSIDE_PF \
- 0x104120UL
-#define CFC_REG_STRONG_ENABLE_PF \
- 0x104128UL
-#define CFC_REG_WEAK_ENABLE_PF \
- 0x104124UL
-#define CSDM_REG_CSDM_INT_MASK_0 \
- 0xc229cUL
-#define CSDM_REG_CSDM_INT_MASK_1 \
- 0xc22acUL
-#define CSDM_REG_CSDM_PRTY_MASK \
- 0xc22bcUL
-#define CSDM_REG_CSDM_PRTY_STS_CLR \
- 0xc22b4UL
-#define CSEM_REG_CSEM_INT_MASK_0 \
- 0x200110UL
-#define CSEM_REG_CSEM_INT_MASK_1 \
- 0x200120UL
-#define CSEM_REG_CSEM_PRTY_MASK_0 \
- 0x200130UL
-#define CSEM_REG_CSEM_PRTY_MASK_1 \
- 0x200140UL
-#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \
- 0x200128UL
-#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \
- 0x200138UL
-#define CSEM_REG_FAST_MEMORY \
- 0x220000UL
-#define CSEM_REG_INT_TABLE \
- 0x200400UL
-#define CSEM_REG_PASSIVE_BUFFER \
- 0x202000UL
-#define CSEM_REG_PRAM \
- 0x240000UL
-#define CSEM_REG_VFPF_ERR_NUM \
- 0x200380UL
-#define DBG_REG_DBG_PRTY_MASK \
- 0xc0a8UL
-#define DBG_REG_DBG_PRTY_STS_CLR \
- 0xc0a0UL
-#define DMAE_REG_BACKWARD_COMP_EN \
- 0x10207cUL
-#define DMAE_REG_CMD_MEM \
- 0x102400UL
-#define DMAE_REG_DMAE_INT_MASK \
- 0x102054UL
-#define DMAE_REG_DMAE_PRTY_MASK \
- 0x102064UL
-#define DMAE_REG_DMAE_PRTY_STS_CLR \
- 0x10205cUL
-#define DMAE_REG_GO_C0 \
- 0x102080UL
-#define DMAE_REG_GO_C1 \
- 0x102084UL
-#define DMAE_REG_GO_C10 \
- 0x102088UL
-#define DMAE_REG_GO_C11 \
- 0x10208cUL
-#define DMAE_REG_GO_C12 \
- 0x102090UL
-#define DMAE_REG_GO_C13 \
- 0x102094UL
-#define DMAE_REG_GO_C14 \
- 0x102098UL
-#define DMAE_REG_GO_C15 \
- 0x10209cUL
-#define DMAE_REG_GO_C2 \
- 0x1020a0UL
-#define DMAE_REG_GO_C3 \
- 0x1020a4UL
-#define DMAE_REG_GO_C4 \
- 0x1020a8UL
-#define DMAE_REG_GO_C5 \
- 0x1020acUL
-#define DMAE_REG_GO_C6 \
- 0x1020b0UL
-#define DMAE_REG_GO_C7 \
- 0x1020b4UL
-#define DMAE_REG_GO_C8 \
- 0x1020b8UL
-#define DMAE_REG_GO_C9 \
- 0x1020bcUL
-#define DORQ_REG_DORQ_INT_MASK \
- 0x170180UL
-#define DORQ_REG_DORQ_INT_STS_CLR \
- 0x170178UL
-#define DORQ_REG_DORQ_PRTY_MASK \
- 0x170190UL
-#define DORQ_REG_DORQ_PRTY_STS_CLR \
- 0x170188UL
-#define DORQ_REG_DPM_CID_OFST \
- 0x170030UL
-#define DORQ_REG_MAX_RVFID_SIZE \
- 0x1701ecUL
-#define DORQ_REG_NORM_CID_OFST \
- 0x17002cUL
-#define DORQ_REG_PF_USAGE_CNT \
- 0x1701d0UL
-#define DORQ_REG_VF_NORM_CID_BASE \
- 0x1701a0UL
-#define DORQ_REG_VF_NORM_CID_OFST \
- 0x1701f4UL
-#define DORQ_REG_VF_NORM_CID_WND_SIZE \
- 0x1701a4UL
-#define DORQ_REG_VF_NORM_MAX_CID_COUNT \
- 0x1701e4UL
-#define DORQ_REG_VF_NORM_VF_BASE \
- 0x1701a8UL
-#define DORQ_REG_VF_TYPE_MASK_0 \
- 0x170218UL
-#define DORQ_REG_VF_TYPE_MAX_MCID_0 \
- 0x1702d8UL
-#define DORQ_REG_VF_TYPE_MIN_MCID_0 \
- 0x170298UL
-#define DORQ_REG_VF_TYPE_VALUE_0 \
- 0x170258UL
-#define DORQ_REG_VF_USAGE_CNT \
- 0x170320UL
-#define DORQ_REG_VF_USAGE_CT_LIMIT \
- 0x170340UL
-#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \
- (0x1<<4)
-#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \
- (0x1<<0)
-#define HC_CONFIG_0_REG_INT_LINE_EN_0 \
- (0x1<<3)
-#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \
- (0x1<<7)
-#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \
- (0x1<<2)
-#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \
- (0x1<<1)
-#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \
- (0x1<<0)
-#define HC_REG_ATTN_MSG0_ADDR_L \
- 0x108018UL
-#define HC_REG_ATTN_MSG1_ADDR_L \
- 0x108020UL
-#define HC_REG_COMMAND_REG \
- 0x108180UL
-#define HC_REG_CONFIG_0 \
- 0x108000UL
-#define HC_REG_CONFIG_1 \
- 0x108004UL
-#define HC_REG_HC_PRTY_MASK \
- 0x1080a0UL
-#define HC_REG_HC_PRTY_STS_CLR \
- 0x108098UL
-#define HC_REG_INT_MASK \
- 0x108108UL
-#define HC_REG_LEADING_EDGE_0 \
- 0x108040UL
-#define HC_REG_MAIN_MEMORY \
- 0x108800UL
-#define HC_REG_MAIN_MEMORY_SIZE \
- 152
-#define HC_REG_TRAILING_EDGE_0 \
- 0x108044UL
-#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \
- (0x1<<1)
-#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \
- (0x1<<0)
-#define IGU_REG_ATTENTION_ACK_BITS \
- 0x130108UL
-#define IGU_REG_ATTN_MSG_ADDR_H \
- 0x13011cUL
-#define IGU_REG_ATTN_MSG_ADDR_L \
- 0x130120UL
-#define IGU_REG_BLOCK_CONFIGURATION \
- 0x130000UL
-#define IGU_REG_COMMAND_REG_32LSB_DATA \
- 0x130124UL
-#define IGU_REG_COMMAND_REG_CTRL \
- 0x13012cUL
-#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \
- 0x130200UL
-#define IGU_REG_IGU_PRTY_MASK \
- 0x1300a8UL
-#define IGU_REG_IGU_PRTY_STS_CLR \
- 0x1300a0UL
-#define IGU_REG_LEADING_EDGE_LATCH \
- 0x130134UL
-#define IGU_REG_MAPPING_MEMORY \
- 0x131000UL
-#define IGU_REG_MAPPING_MEMORY_SIZE \
- 136
-#define IGU_REG_PBA_STATUS_LSB \
- 0x130138UL
-#define IGU_REG_PBA_STATUS_MSB \
- 0x13013cUL
-#define IGU_REG_PCI_PF_MSIX_EN \
- 0x130144UL
-#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \
- 0x130148UL
-#define IGU_REG_PCI_PF_MSI_EN \
- 0x130140UL
-#define IGU_REG_PENDING_BITS_STATUS \
- 0x130300UL
-#define IGU_REG_PF_CONFIGURATION \
- 0x130154UL
-#define IGU_REG_PROD_CONS_MEMORY \
- 0x132000UL
-#define IGU_REG_RESET_MEMORIES \
- 0x130158UL
-#define IGU_REG_SB_INT_BEFORE_MASK_LSB \
- 0x13015cUL
-#define IGU_REG_SB_INT_BEFORE_MASK_MSB \
- 0x130160UL
-#define IGU_REG_SB_MASK_LSB \
- 0x130164UL
-#define IGU_REG_SB_MASK_MSB \
- 0x130168UL
-#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \
- 0x130800UL
-#define IGU_REG_TRAILING_EDGE_LATCH \
- 0x130104UL
-#define IGU_REG_VF_CONFIGURATION \
- 0x130170UL
-#define MCP_REG_MCPR_ACCESS_LOCK \
- 0x8009c
-#define MCP_REG_MCPR_GP_INPUTS \
- 0x800c0
-#define MCP_REG_MCPR_GP_OENABLE \
- 0x800c8
-#define MCP_REG_MCPR_GP_OUTPUTS \
- 0x800c4
-#define MCP_REG_MCPR_IMC_COMMAND \
- 0x85900
-#define MCP_REG_MCPR_IMC_DATAREG0 \
- 0x85920
-#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \
- 0x85904
-#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \
- 0x86424
-#define MCP_REG_MCPR_NVM_ADDR \
- 0x8640c
-#define MCP_REG_MCPR_NVM_CFG4 \
- 0x8642c
-#define MCP_REG_MCPR_NVM_COMMAND \
- 0x86400
-#define MCP_REG_MCPR_NVM_READ \
- 0x86410
-#define MCP_REG_MCPR_NVM_SW_ARB \
- 0x86420
-#define MCP_REG_MCPR_NVM_WRITE \
- 0x86408
-#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \
- (0x1<<1)
-#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \
- (0x1<<0)
-#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \
- 0xa42cUL
-#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \
- 0xa438UL
-#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \
- 0xa444UL
-#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \
- 0xa450UL
-#define MISC_REG_AEU_AFTER_INVERT_4_MCP \
- 0xa458UL
-#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \
- 0xa700UL
-#define MISC_REG_AEU_CLR_LATCH_SIGNAL \
- 0xa45cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \
- 0xa06cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \
- 0xa07cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \
- 0xa08cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \
- 0xa10cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \
- 0xa11cUL
-#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \
- 0xa12cUL
-#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \
- 0xa078UL
-#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \
- 0xa118UL
-#define MISC_REG_AEU_ENABLE4_NIG_0 \
- 0xa0f8UL
-#define MISC_REG_AEU_ENABLE4_NIG_1 \
- 0xa198UL
-#define MISC_REG_AEU_ENABLE4_PXP_0 \
- 0xa108UL
-#define MISC_REG_AEU_ENABLE4_PXP_1 \
- 0xa1a8UL
-#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \
- 0xa688UL
-#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \
- 0xa6b0UL
-#define MISC_REG_AEU_GENERAL_ATTN_0 \
- 0xa000UL
-#define MISC_REG_AEU_GENERAL_ATTN_1 \
- 0xa004UL
-#define MISC_REG_AEU_GENERAL_ATTN_10 \
- 0xa028UL
-#define MISC_REG_AEU_GENERAL_ATTN_11 \
- 0xa02cUL
-#define MISC_REG_AEU_GENERAL_ATTN_12 \
- 0xa030UL
-#define MISC_REG_AEU_GENERAL_ATTN_2 \
- 0xa008UL
-#define MISC_REG_AEU_GENERAL_ATTN_3 \
- 0xa00cUL
-#define MISC_REG_AEU_GENERAL_ATTN_4 \
- 0xa010UL
-#define MISC_REG_AEU_GENERAL_ATTN_5 \
- 0xa014UL
-#define MISC_REG_AEU_GENERAL_ATTN_6 \
- 0xa018UL
-#define MISC_REG_AEU_GENERAL_ATTN_7 \
- 0xa01cUL
-#define MISC_REG_AEU_GENERAL_ATTN_8 \
- 0xa020UL
-#define MISC_REG_AEU_GENERAL_ATTN_9 \
- 0xa024UL
-#define MISC_REG_AEU_GENERAL_MASK \
- 0xa61cUL
-#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \
- 0xa060UL
-#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \
- 0xa064UL
-#define MISC_REG_BOND_ID \
- 0xa400UL
-#define MISC_REG_CHIP_NUM \
- 0xa408UL
-#define MISC_REG_CHIP_REV \
- 0xa40cUL
-#define MISC_REG_CHIP_TYPE \
- 0xac60UL
-#define MISC_REG_CHIP_TYPE_57811_MASK \
- (1<<1)
-#define MISC_REG_CPMU_LP_DR_ENABLE \
- 0xa858UL
-#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \
- 0xa84cUL
-#define MISC_REG_CPMU_LP_IDLE_THR_P0 \
- 0xa8a0UL
-#define MISC_REG_CPMU_LP_MASK_ENT_P0 \
- 0xa880UL
-#define MISC_REG_CPMU_LP_MASK_EXT_P0 \
- 0xa888UL
-#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \
- 0xa8b8UL
-#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \
- 0xa8bcUL
-#define MISC_REG_DRIVER_CONTROL_1 \
- 0xa510UL
-#define MISC_REG_DRIVER_CONTROL_7 \
- 0xa3c8UL
-#define MISC_REG_FOUR_PORT_PATH_SWAP \
- 0xa75cUL
-#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \
- 0xa738UL
-#define MISC_REG_FOUR_PORT_PORT_SWAP \
- 0xa754UL
-#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \
- 0xa734UL
-#define MISC_REG_GENERIC_CR_0 \
- 0xa460UL
-#define MISC_REG_GENERIC_CR_1 \
- 0xa464UL
-#define MISC_REG_GENERIC_POR_1 \
- 0xa474UL
-#define MISC_REG_GEN_PURP_HWG \
- 0xa9a0UL
-#define MISC_REG_GPIO \
- 0xa490UL
-#define MISC_REG_GPIO_EVENT_EN \
- 0xa2bcUL
-#define MISC_REG_GPIO_INT \
- 0xa494UL
-#define MISC_REG_GRC_RSV_ATTN \
- 0xa3c0UL
-#define MISC_REG_GRC_TIMEOUT_ATTN \
- 0xa3c4UL
-#define MISC_REG_LCPLL_E40_PWRDWN \
- 0xaa74UL
-#define MISC_REG_LCPLL_E40_RESETB_ANA \
- 0xaa78UL
-#define MISC_REG_LCPLL_E40_RESETB_DIG \
- 0xaa7cUL
-#define MISC_REG_MISC_INT_MASK \
- 0xa388UL
-#define MISC_REG_MISC_PRTY_MASK \
- 0xa398UL
-#define MISC_REG_MISC_PRTY_STS_CLR \
- 0xa390UL
-#define MISC_REG_PORT4MODE_EN \
- 0xa750UL
-#define MISC_REG_PORT4MODE_EN_OVWR \
- 0xa720UL
-#define MISC_REG_RESET_REG_1 \
- 0xa580UL
-#define MISC_REG_RESET_REG_2 \
- 0xa590UL
-#define MISC_REG_SHARED_MEM_ADDR \
- 0xa2b4UL
-#define MISC_REG_SPIO \
- 0xa4fcUL
-#define MISC_REG_SPIO_EVENT_EN \
- 0xa2b8UL
-#define MISC_REG_SPIO_INT \
- 0xa500UL
-#define MISC_REG_TWO_PORT_PATH_SWAP \
- 0xa758UL
-#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \
- 0xa72cUL
-#define MISC_REG_UNPREPARED \
- 0xa424UL
-#define MISC_REG_WC0_CTRL_PHY_ADDR \
- 0xa9ccUL
-#define MISC_REG_WC0_RESET \
- 0xac30UL
-#define MISC_REG_XMAC_CORE_PORT_MODE \
- 0xa964UL
-#define MISC_REG_XMAC_PHY_PORT_MODE \
- 0xa960UL
-#define MSTAT_REG_RX_STAT_GR64_LO \
- 0x200UL
-#define MSTAT_REG_TX_STAT_GTXPOK_LO \
- 0UL
-#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \
- (0x1<<0)
-#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \
- (0x1<<0)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \
- (0x1<<0)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \
- (0x1<<9)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \
- (0x1<<15)
-#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \
- (0xf<<18)
-#define NIG_REG_BMAC0_IN_EN \
- 0x100acUL
-#define NIG_REG_BMAC0_OUT_EN \
- 0x100e0UL
-#define NIG_REG_BMAC0_PAUSE_OUT_EN \
- 0x10110UL
-#define NIG_REG_BMAC0_REGS_OUT_EN \
- 0x100e8UL
-#define NIG_REG_BRB0_PAUSE_IN_EN \
- 0x100c4UL
-#define NIG_REG_BRB1_PAUSE_IN_EN \
- 0x100c8UL
-#define NIG_REG_DEBUG_PACKET_LB \
- 0x10800UL
-#define NIG_REG_EGRESS_DRAIN0_MODE \
- 0x10060UL
-#define NIG_REG_EGRESS_EMAC0_OUT_EN \
- 0x10120UL
-#define NIG_REG_EGRESS_EMAC0_PORT \
- 0x10058UL
-#define NIG_REG_EMAC0_IN_EN \
- 0x100a4UL
-#define NIG_REG_EMAC0_PAUSE_OUT_EN \
- 0x10118UL
-#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \
- 0x10494UL
-#define NIG_REG_INGRESS_BMAC0_MEM \
- 0x10c00UL
-#define NIG_REG_INGRESS_BMAC1_MEM \
- 0x11000UL
-#define NIG_REG_INGRESS_EOP_LB_EMPTY \
- 0x104e0UL
-#define NIG_REG_INGRESS_EOP_LB_FIFO \
- 0x104e4UL
-#define NIG_REG_LATCH_BC_0 \
- 0x16210UL
-#define NIG_REG_LATCH_STATUS_0 \
- 0x18000UL
-#define NIG_REG_LED_10G_P0 \
- 0x10320UL
-#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \
- 0x10318UL
-#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \
- 0x10310UL
-#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \
- 0x10308UL
-#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \
- 0x102f8UL
-#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \
- 0x10300UL
-#define NIG_REG_LED_MODE_P0 \
- 0x102f0UL
-#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \
- 0x16070UL
-#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \
- 0x16074UL
-#define NIG_REG_LLFC_ENABLE_0 \
- 0x16208UL
-#define NIG_REG_LLFC_ENABLE_1 \
- 0x1620cUL
-#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \
- 0x16058UL
-#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \
- 0x1605cUL
-#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \
- 0x16060UL
-#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \
- 0x16064UL
-#define NIG_REG_LLFC_OUT_EN_0 \
- 0x160c8UL
-#define NIG_REG_LLFC_OUT_EN_1 \
- 0x160ccUL
-#define NIG_REG_LLH0_BRB1_DRV_MASK \
- 0x10244UL
-#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \
- 0x16048UL
-#define NIG_REG_LLH0_BRB1_NOT_MCP \
- 0x1025cUL
-#define NIG_REG_LLH0_CLS_TYPE \
- 0x16080UL
-#define NIG_REG_LLH0_FUNC_EN \
- 0x160fcUL
-#define NIG_REG_LLH0_FUNC_MEM \
- 0x16180UL
-#define NIG_REG_LLH0_FUNC_MEM_ENABLE \
- 0x16140UL
-#define NIG_REG_LLH0_FUNC_VLAN_ID \
- 0x16100UL
-#define NIG_REG_LLH0_XCM_MASK \
- 0x10130UL
-#define NIG_REG_LLH1_BRB1_NOT_MCP \
- 0x102dcUL
-#define NIG_REG_LLH1_CLS_TYPE \
- 0x16084UL
-#define NIG_REG_LLH1_FUNC_MEM \
- 0x161c0UL
-#define NIG_REG_LLH1_FUNC_MEM_ENABLE \
- 0x16160UL
-#define NIG_REG_LLH1_FUNC_MEM_SIZE \
- 16
-#define NIG_REG_LLH1_MF_MODE \
- 0x18614UL
-#define NIG_REG_LLH1_XCM_MASK \
- 0x10134UL
-#define NIG_REG_LLH_E1HOV_MODE \
- 0x160d8UL
-#define NIG_REG_LLH_MF_MODE \
- 0x16024UL
-#define NIG_REG_MASK_INTERRUPT_PORT0 \
- 0x10330UL
-#define NIG_REG_MASK_INTERRUPT_PORT1 \
- 0x10334UL
-#define NIG_REG_NIG_EMAC0_EN \
- 0x1003cUL
-#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \
- 0x10044UL
-#define NIG_REG_NIG_INT_STS_CLR_0 \
- 0x103b4UL
-#define NIG_REG_NIG_PRTY_MASK \
- 0x103dcUL
-#define NIG_REG_NIG_PRTY_MASK_0 \
- 0x183c8UL
-#define NIG_REG_NIG_PRTY_MASK_1 \
- 0x183d8UL
-#define NIG_REG_NIG_PRTY_STS_CLR \
- 0x103d4UL
-#define NIG_REG_NIG_PRTY_STS_CLR_0 \
- 0x183c0UL
-#define NIG_REG_NIG_PRTY_STS_CLR_1 \
- 0x183d0UL
-#define NIG_REG_P0_HDRS_AFTER_BASIC \
- 0x18038UL
-#define NIG_REG_P0_HWPFC_ENABLE \
- 0x18078UL
-#define NIG_REG_P0_LLH_FUNC_MEM2 \
- 0x18480UL
-#define NIG_REG_P0_MAC_IN_EN \
- 0x185acUL
-#define NIG_REG_P0_MAC_OUT_EN \
- 0x185b0UL
-#define NIG_REG_P0_MAC_PAUSE_OUT_EN \
- 0x185b4UL
-#define NIG_REG_P0_PKT_PRIORITY_TO_COS \
- 0x18054UL
-#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \
- 0x18058UL
-#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \
- 0x1805cUL
-#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \
- 0x186b0UL
-#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \
- 0x186b4UL
-#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \
- 0x186b8UL
-#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \
- 0x186bcUL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \
- 0x180f0UL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
- 0x18688UL
-#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
- 0x1868cUL
-#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \
- 0x180e8UL
-#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
- 0x180ecUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \
- 0x1810cUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \
- 0x18110UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \
- 0x18114UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \
- 0x18118UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \
- 0x1811cUL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \
- 0x186a0UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \
- 0x186a4UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \
- 0x186a8UL
-#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \
- 0x186acUL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \
- 0x180f8UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \
- 0x180fcUL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \
- 0x18100UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \
- 0x18104UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \
- 0x18108UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \
- 0x18690UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \
- 0x18694UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \
- 0x18698UL
-#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \
- 0x1869cUL
-#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \
- 0x180f4UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \
- 0x180e4UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \
- 0x18680UL
-#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \
- 0x18684UL
-#define NIG_REG_P1_HDRS_AFTER_BASIC \
- 0x1818cUL
-#define NIG_REG_P1_HWPFC_ENABLE \
- 0x181d0UL
-#define NIG_REG_P1_LLH_FUNC_MEM2 \
- 0x184c0UL
-#define NIG_REG_P1_MAC_IN_EN \
- 0x185c0UL
-#define NIG_REG_P1_MAC_OUT_EN \
- 0x185c4UL
-#define NIG_REG_P1_MAC_PAUSE_OUT_EN \
- 0x185c8UL
-#define NIG_REG_P1_PKT_PRIORITY_TO_COS \
- 0x181a8UL
-#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \
- 0x181acUL
-#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \
- 0x181b0UL
-#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \
- 0x186f8UL
-#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
- 0x186e8UL
-#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
- 0x186ecUL
-#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \
- 0x18234UL
-#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
- 0x18238UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \
- 0x18258UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \
- 0x1825cUL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \
- 0x18260UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \
- 0x18264UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \
- 0x18268UL
-#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \
- 0x186f4UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \
- 0x18244UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \
- 0x18248UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \
- 0x1824cUL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \
- 0x18250UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \
- 0x18254UL
-#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \
- 0x186f0UL
-#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \
- 0x18240UL
-#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \
- 0x186e0UL
-#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \
- 0x186e4UL
-#define NIG_REG_PAUSE_ENABLE_0 \
- 0x160c0UL
-#define NIG_REG_PAUSE_ENABLE_1 \
- 0x160c4UL
-#define NIG_REG_PORT_SWAP \
- 0x10394UL
-#define NIG_REG_PPP_ENABLE_0 \
- 0x160b0UL
-#define NIG_REG_PPP_ENABLE_1 \
- 0x160b4UL
-#define NIG_REG_PRS_REQ_IN_EN \
- 0x100b8UL
-#define NIG_REG_SERDES0_CTRL_MD_DEVAD \
- 0x10370UL
-#define NIG_REG_SERDES0_CTRL_MD_ST \
- 0x1036cUL
-#define NIG_REG_SERDES0_CTRL_PHY_ADDR \
- 0x10374UL
-#define NIG_REG_SERDES0_STATUS_LINK_STATUS \
- 0x10578UL
-#define NIG_REG_STAT0_BRB_DISCARD \
- 0x105f0UL
-#define NIG_REG_STAT0_BRB_TRUNCATE \
- 0x105f8UL
-#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \
- 0x10750UL
-#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \
- 0x10760UL
-#define NIG_REG_STAT1_BRB_DISCARD \
- 0x10628UL
-#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \
- 0x107a0UL
-#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \
- 0x107b0UL
-#define NIG_REG_STAT2_BRB_OCTET \
- 0x107e0UL
-#define NIG_REG_STATUS_INTERRUPT_PORT0 \
- 0x10328UL
-#define NIG_REG_STRAP_OVERRIDE \
- 0x10398UL
-#define NIG_REG_XCM0_OUT_EN \
- 0x100f0UL
-#define NIG_REG_XCM1_OUT_EN \
- 0x100f4UL
-#define NIG_REG_XGXS0_CTRL_MD_DEVAD \
- 0x1033cUL
-#define NIG_REG_XGXS0_CTRL_MD_ST \
- 0x10338UL
-#define NIG_REG_XGXS0_CTRL_PHY_ADDR \
- 0x10340UL
-#define NIG_REG_XGXS0_STATUS_LINK10G \
- 0x10680UL
-#define NIG_REG_XGXS0_STATUS_LINK_STATUS \
- 0x10684UL
-#define NIG_REG_XGXS_LANE_SEL_P0 \
- 0x102e8UL
-#define NIG_REG_XGXS_SERDES0_MODE_SEL \
- 0x102e0UL
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \
- (0x1<<0)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \
- (0x1<<9)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \
- (0x1<<15)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \
- (0xf<<18)
-#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \
- 18
-#define PBF_REG_COS0_UPPER_BOUND \
- 0x15c05cUL
-#define PBF_REG_COS0_UPPER_BOUND_P0 \
- 0x15c2ccUL
-#define PBF_REG_COS0_UPPER_BOUND_P1 \
- 0x15c2e4UL
-#define PBF_REG_COS0_WEIGHT \
- 0x15c054UL
-#define PBF_REG_COS0_WEIGHT_P0 \
- 0x15c2a8UL
-#define PBF_REG_COS0_WEIGHT_P1 \
- 0x15c2c0UL
-#define PBF_REG_COS1_UPPER_BOUND \
- 0x15c060UL
-#define PBF_REG_COS1_WEIGHT \
- 0x15c058UL
-#define PBF_REG_COS1_WEIGHT_P0 \
- 0x15c2acUL
-#define PBF_REG_COS1_WEIGHT_P1 \
- 0x15c2c4UL
-#define PBF_REG_COS2_WEIGHT_P0 \
- 0x15c2b0UL
-#define PBF_REG_COS2_WEIGHT_P1 \
- 0x15c2c8UL
-#define PBF_REG_COS3_WEIGHT_P0 \
- 0x15c2b4UL
-#define PBF_REG_COS4_WEIGHT_P0 \
- 0x15c2b8UL
-#define PBF_REG_COS5_WEIGHT_P0 \
- 0x15c2bcUL
-#define PBF_REG_CREDIT_LB_Q \
- 0x140338UL
-#define PBF_REG_CREDIT_Q0 \
- 0x14033cUL
-#define PBF_REG_CREDIT_Q1 \
- 0x140340UL
-#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \
- 0x14005cUL
-#define PBF_REG_DISABLE_PF \
- 0x1402e8UL
-#define PBF_REG_DISABLE_VF \
- 0x1402ecUL
-#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \
- 0x15c288UL
-#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \
- 0x15c28cUL
-#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \
- 0x15c278UL
-#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \
- 0x15c27cUL
-#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \
- 0x15c280UL
-#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \
- 0x15c284UL
-#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \
- 0x15c2a0UL
-#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \
- 0x15c2a4UL
-#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \
- 0x15c270UL
-#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \
- 0x15c274UL
-#define PBF_REG_ETS_ENABLED \
- 0x15c050UL
-#define PBF_REG_HDRS_AFTER_BASIC \
- 0x15c0a8UL
-#define PBF_REG_HDRS_AFTER_TAG_0 \
- 0x15c0b8UL
-#define PBF_REG_HIGH_PRIORITY_COS_NUM \
- 0x15c04cUL
-#define PBF_REG_INIT_CRD_LB_Q \
- 0x15c248UL
-#define PBF_REG_INIT_CRD_Q0 \
- 0x15c230UL
-#define PBF_REG_INIT_CRD_Q1 \
- 0x15c234UL
-#define PBF_REG_INIT_P0 \
- 0x140004UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \
- 0x140354UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \
- 0x140358UL
-#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \
- 0x14035cUL
-#define PBF_REG_MUST_HAVE_HDRS \
- 0x15c0c4UL
-#define PBF_REG_NUM_STRICT_ARB_SLOTS \
- 0x15c064UL
-#define PBF_REG_P0_ARB_THRSH \
- 0x1400e4UL
-#define PBF_REG_P0_CREDIT \
- 0x140200UL
-#define PBF_REG_P0_INIT_CRD \
- 0x1400d0UL
-#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \
- 0x140308UL
-#define PBF_REG_P0_PAUSE_ENABLE \
- 0x140014UL
-#define PBF_REG_P0_TQ_LINES_FREED_CNT \
- 0x1402f0UL
-#define PBF_REG_P0_TQ_OCCUPANCY \
- 0x1402fcUL
-#define PBF_REG_P1_CREDIT \
- 0x140208UL
-#define PBF_REG_P1_INIT_CRD \
- 0x1400d4UL
-#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \
- 0x14030cUL
-#define PBF_REG_P1_TQ_LINES_FREED_CNT \
- 0x1402f4UL
-#define PBF_REG_P1_TQ_OCCUPANCY \
- 0x140300UL
-#define PBF_REG_P4_CREDIT \
- 0x140210UL
-#define PBF_REG_P4_INIT_CRD \
- 0x1400e0UL
-#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \
- 0x140310UL
-#define PBF_REG_P4_TQ_LINES_FREED_CNT \
- 0x1402f8UL
-#define PBF_REG_P4_TQ_OCCUPANCY \
- 0x140304UL
-#define PBF_REG_PBF_INT_MASK \
- 0x1401d4UL
-#define PBF_REG_PBF_PRTY_MASK \
- 0x1401e4UL
-#define PBF_REG_PBF_PRTY_STS_CLR \
- 0x1401dcUL
-#define PBF_REG_TAG_ETHERTYPE_0 \
- 0x15c090UL
-#define PBF_REG_TAG_LEN_0 \
- 0x15c09cUL
-#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \
- 0x14038cUL
-#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \
- 0x140390UL
-#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \
- 0x140394UL
-#define PBF_REG_TQ_OCCUPANCY_LB_Q \
- 0x1403a8UL
-#define PBF_REG_TQ_OCCUPANCY_Q0 \
- 0x1403acUL
-#define PBF_REG_TQ_OCCUPANCY_Q1 \
- 0x1403b0UL
-#define PB_REG_PB_INT_MASK \
- 0x28UL
-#define PB_REG_PB_PRTY_MASK \
- 0x38UL
-#define PB_REG_PB_PRTY_STS_CLR \
- 0x30UL
-#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \
- (0x1<<0)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \
- (0x1<<8)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \
- (0x1<<1)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \
- (0x1<<6)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \
- (0x1<<7)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \
- (0x1<<4)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \
- (0x1<<3)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \
- (0x1<<5)
-#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \
- (0x1<<2)
-#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \
- 0x9418UL
-#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
- 0x9478UL
-#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR \
- 0x947cUL
-#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR \
- 0x9480UL
-#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR \
- 0x9474UL
-#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
- 0x942cUL
-#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
- 0x9430UL
-#define PGLUE_B_REG_INTERNAL_VFID_ENABLE \
- 0x9438UL
-#define PGLUE_B_REG_PGLUE_B_INT_STS \
- 0x9298UL
-#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \
- 0x929cUL
-#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \
- 0x92b4UL
-#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \
- 0x92acUL
-#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \
- 0x9458UL
-#define PGLUE_B_REG_TAGS_63_32 \
- 0x9244UL
-#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \
- 0x9470UL
-#define PRS_REG_A_PRSU_20 \
- 0x40134UL
-#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \
- 0x4011cUL
-#define PRS_REG_E1HOV_MODE \
- 0x401c8UL
-#define PRS_REG_HDRS_AFTER_BASIC \
- 0x40238UL
-#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \
- 0x40270UL
-#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \
- 0x40290UL
-#define PRS_REG_HDRS_AFTER_TAG_0 \
- 0x40248UL
-#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \
- 0x40280UL
-#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \
- 0x402a0UL
-#define PRS_REG_MUST_HAVE_HDRS \
- 0x40254UL
-#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \
- 0x4028cUL
-#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \
- 0x402acUL
-#define PRS_REG_NIC_MODE \
- 0x40138UL
-#define PRS_REG_NUM_OF_PACKETS \
- 0x40124UL
-#define PRS_REG_PRS_PRTY_MASK \
- 0x401a4UL
-#define PRS_REG_PRS_PRTY_STS_CLR \
- 0x4019cUL
-#define PRS_REG_TAG_ETHERTYPE_0 \
- 0x401d4UL
-#define PRS_REG_TAG_LEN_0 \
- 0x4022cUL
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \
- (0x1<<19)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \
- (0x1<<20)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \
- (0x1<<22)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \
- (0x1<<23)
-#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \
- (0x1<<24)
-#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \
- (0x1<<7)
-#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \
- (0x1<<7)
-#define PXP2_REG_PGL_ADDR_88_F0 \
- 0x120534UL
-#define PXP2_REG_PGL_ADDR_88_F1 \
- 0x120544UL
-#define PXP2_REG_PGL_ADDR_8C_F0 \
- 0x120538UL
-#define PXP2_REG_PGL_ADDR_8C_F1 \
- 0x120548UL
-#define PXP2_REG_PGL_ADDR_90_F0 \
- 0x12053cUL
-#define PXP2_REG_PGL_ADDR_90_F1 \
- 0x12054cUL
-#define PXP2_REG_PGL_ADDR_94_F0 \
- 0x120540UL
-#define PXP2_REG_PGL_ADDR_94_F1 \
- 0x120550UL
-#define PXP2_REG_PGL_EXP_ROM2 \
- 0x120808UL
-#define PXP2_REG_PGL_PRETEND_FUNC_F0 \
- 0x120674UL
-#define PXP2_REG_PGL_PRETEND_FUNC_F1 \
- 0x120678UL
-#define PXP2_REG_PGL_TAGS_LIMIT \
- 0x1205a8UL
-#define PXP2_REG_PSWRQ_BW_ADD1 \
- 0x1201c0UL
-#define PXP2_REG_PSWRQ_BW_ADD10 \
- 0x1201e4UL
-#define PXP2_REG_PSWRQ_BW_ADD11 \
- 0x1201e8UL
-#define PXP2_REG_PSWRQ_BW_ADD2 \
- 0x1201c4UL
-#define PXP2_REG_PSWRQ_BW_ADD28 \
- 0x120228UL
-#define PXP2_REG_PSWRQ_BW_ADD3 \
- 0x1201c8UL
-#define PXP2_REG_PSWRQ_BW_ADD6 \
- 0x1201d4UL
-#define PXP2_REG_PSWRQ_BW_ADD7 \
- 0x1201d8UL
-#define PXP2_REG_PSWRQ_BW_ADD8 \
- 0x1201dcUL
-#define PXP2_REG_PSWRQ_BW_ADD9 \
- 0x1201e0UL
-#define PXP2_REG_PSWRQ_BW_L1 \
- 0x1202b0UL
-#define PXP2_REG_PSWRQ_BW_L10 \
- 0x1202d4UL
-#define PXP2_REG_PSWRQ_BW_L11 \
- 0x1202d8UL
-#define PXP2_REG_PSWRQ_BW_L2 \
- 0x1202b4UL
-#define PXP2_REG_PSWRQ_BW_L28 \
- 0x120318UL
-#define PXP2_REG_PSWRQ_BW_L3 \
- 0x1202b8UL
-#define PXP2_REG_PSWRQ_BW_L6 \
- 0x1202c4UL
-#define PXP2_REG_PSWRQ_BW_L7 \
- 0x1202c8UL
-#define PXP2_REG_PSWRQ_BW_L8 \
- 0x1202ccUL
-#define PXP2_REG_PSWRQ_BW_L9 \
- 0x1202d0UL
-#define PXP2_REG_PSWRQ_BW_RD \
- 0x120324UL
-#define PXP2_REG_PSWRQ_BW_UB1 \
- 0x120238UL
-#define PXP2_REG_PSWRQ_BW_UB10 \
- 0x12025cUL
-#define PXP2_REG_PSWRQ_BW_UB11 \
- 0x120260UL
-#define PXP2_REG_PSWRQ_BW_UB2 \
- 0x12023cUL
-#define PXP2_REG_PSWRQ_BW_UB28 \
- 0x1202a0UL
-#define PXP2_REG_PSWRQ_BW_UB3 \
- 0x120240UL
-#define PXP2_REG_PSWRQ_BW_UB6 \
- 0x12024cUL
-#define PXP2_REG_PSWRQ_BW_UB7 \
- 0x120250UL
-#define PXP2_REG_PSWRQ_BW_UB8 \
- 0x120254UL
-#define PXP2_REG_PSWRQ_BW_UB9 \
- 0x120258UL
-#define PXP2_REG_PSWRQ_BW_WR \
- 0x120328UL
-#define PXP2_REG_PSWRQ_CDU0_L2P \
- 0x120000UL
-#define PXP2_REG_PSWRQ_QM0_L2P \
- 0x120038UL
-#define PXP2_REG_PSWRQ_SRC0_L2P \
- 0x120054UL
-#define PXP2_REG_PSWRQ_TM0_L2P \
- 0x12001cUL
-#define PXP2_REG_PXP2_INT_MASK_0 \
- 0x120578UL
-#define PXP2_REG_PXP2_INT_MASK_1 \
- 0x120614UL
-#define PXP2_REG_PXP2_INT_STS_0 \
- 0x12056cUL
-#define PXP2_REG_PXP2_INT_STS_1 \
- 0x120608UL
-#define PXP2_REG_PXP2_INT_STS_CLR_0 \
- 0x120570UL
-#define PXP2_REG_PXP2_PRTY_MASK_0 \
- 0x120588UL
-#define PXP2_REG_PXP2_PRTY_MASK_1 \
- 0x120598UL
-#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \
- 0x120580UL
-#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \
- 0x120590UL
-#define PXP2_REG_RD_BLK_CNT \
- 0x120418UL
-#define PXP2_REG_RD_CDURD_SWAP_MODE \
- 0x120404UL
-#define PXP2_REG_RD_DISABLE_INPUTS \
- 0x120374UL
-#define PXP2_REG_RD_INIT_DONE \
- 0x120370UL
-#define PXP2_REG_RD_PBF_SWAP_MODE \
- 0x1203f4UL
-#define PXP2_REG_RD_PORT_IS_IDLE_0 \
- 0x12041cUL
-#define PXP2_REG_RD_PORT_IS_IDLE_1 \
- 0x120420UL
-#define PXP2_REG_RD_QM_SWAP_MODE \
- 0x1203f8UL
-#define PXP2_REG_RD_SRC_SWAP_MODE \
- 0x120400UL
-#define PXP2_REG_RD_SR_CNT \
- 0x120414UL
-#define PXP2_REG_RD_START_INIT \
- 0x12036cUL
-#define PXP2_REG_RD_TM_SWAP_MODE \
- 0x1203fcUL
-#define PXP2_REG_RQ_BW_RD_ADD0 \
- 0x1201bcUL
-#define PXP2_REG_RQ_BW_RD_ADD12 \
- 0x1201ecUL
-#define PXP2_REG_RQ_BW_RD_ADD13 \
- 0x1201f0UL
-#define PXP2_REG_RQ_BW_RD_ADD14 \
- 0x1201f4UL
-#define PXP2_REG_RQ_BW_RD_ADD15 \
- 0x1201f8UL
-#define PXP2_REG_RQ_BW_RD_ADD16 \
- 0x1201fcUL
-#define PXP2_REG_RQ_BW_RD_ADD17 \
- 0x120200UL
-#define PXP2_REG_RQ_BW_RD_ADD18 \
- 0x120204UL
-#define PXP2_REG_RQ_BW_RD_ADD19 \
- 0x120208UL
-#define PXP2_REG_RQ_BW_RD_ADD20 \
- 0x12020cUL
-#define PXP2_REG_RQ_BW_RD_ADD22 \
- 0x120210UL
-#define PXP2_REG_RQ_BW_RD_ADD23 \
- 0x120214UL
-#define PXP2_REG_RQ_BW_RD_ADD24 \
- 0x120218UL
-#define PXP2_REG_RQ_BW_RD_ADD25 \
- 0x12021cUL
-#define PXP2_REG_RQ_BW_RD_ADD26 \
- 0x120220UL
-#define PXP2_REG_RQ_BW_RD_ADD27 \
- 0x120224UL
-#define PXP2_REG_RQ_BW_RD_ADD4 \
- 0x1201ccUL
-#define PXP2_REG_RQ_BW_RD_ADD5 \
- 0x1201d0UL
-#define PXP2_REG_RQ_BW_RD_L0 \
- 0x1202acUL
-#define PXP2_REG_RQ_BW_RD_L12 \
- 0x1202dcUL
-#define PXP2_REG_RQ_BW_RD_L13 \
- 0x1202e0UL
-#define PXP2_REG_RQ_BW_RD_L14 \
- 0x1202e4UL
-#define PXP2_REG_RQ_BW_RD_L15 \
- 0x1202e8UL
-#define PXP2_REG_RQ_BW_RD_L16 \
- 0x1202ecUL
-#define PXP2_REG_RQ_BW_RD_L17 \
- 0x1202f0UL
-#define PXP2_REG_RQ_BW_RD_L18 \
- 0x1202f4UL
-#define PXP2_REG_RQ_BW_RD_L19 \
- 0x1202f8UL
-#define PXP2_REG_RQ_BW_RD_L20 \
- 0x1202fcUL
-#define PXP2_REG_RQ_BW_RD_L22 \
- 0x120300UL
-#define PXP2_REG_RQ_BW_RD_L23 \
- 0x120304UL
-#define PXP2_REG_RQ_BW_RD_L24 \
- 0x120308UL
-#define PXP2_REG_RQ_BW_RD_L25 \
- 0x12030cUL
-#define PXP2_REG_RQ_BW_RD_L26 \
- 0x120310UL
-#define PXP2_REG_RQ_BW_RD_L27 \
- 0x120314UL
-#define PXP2_REG_RQ_BW_RD_L4 \
- 0x1202bcUL
-#define PXP2_REG_RQ_BW_RD_L5 \
- 0x1202c0UL
-#define PXP2_REG_RQ_BW_RD_UBOUND0 \
- 0x120234UL
-#define PXP2_REG_RQ_BW_RD_UBOUND12 \
- 0x120264UL
-#define PXP2_REG_RQ_BW_RD_UBOUND13 \
- 0x120268UL
-#define PXP2_REG_RQ_BW_RD_UBOUND14 \
- 0x12026cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND15 \
- 0x120270UL
-#define PXP2_REG_RQ_BW_RD_UBOUND16 \
- 0x120274UL
-#define PXP2_REG_RQ_BW_RD_UBOUND17 \
- 0x120278UL
-#define PXP2_REG_RQ_BW_RD_UBOUND18 \
- 0x12027cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND19 \
- 0x120280UL
-#define PXP2_REG_RQ_BW_RD_UBOUND20 \
- 0x120284UL
-#define PXP2_REG_RQ_BW_RD_UBOUND22 \
- 0x120288UL
-#define PXP2_REG_RQ_BW_RD_UBOUND23 \
- 0x12028cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND24 \
- 0x120290UL
-#define PXP2_REG_RQ_BW_RD_UBOUND25 \
- 0x120294UL
-#define PXP2_REG_RQ_BW_RD_UBOUND26 \
- 0x120298UL
-#define PXP2_REG_RQ_BW_RD_UBOUND27 \
- 0x12029cUL
-#define PXP2_REG_RQ_BW_RD_UBOUND4 \
- 0x120244UL
-#define PXP2_REG_RQ_BW_RD_UBOUND5 \
- 0x120248UL
-#define PXP2_REG_RQ_BW_WR_ADD29 \
- 0x12022cUL
-#define PXP2_REG_RQ_BW_WR_ADD30 \
- 0x120230UL
-#define PXP2_REG_RQ_BW_WR_L29 \
- 0x12031cUL
-#define PXP2_REG_RQ_BW_WR_L30 \
- 0x120320UL
-#define PXP2_REG_RQ_BW_WR_UBOUND29 \
- 0x1202a4UL
-#define PXP2_REG_RQ_BW_WR_UBOUND30 \
- 0x1202a8UL
-#define PXP2_REG_RQ_CDU_ENDIAN_M \
- 0x1201a0UL
-#define PXP2_REG_RQ_CDU_FIRST_ILT \
- 0x12061cUL
-#define PXP2_REG_RQ_CDU_LAST_ILT \
- 0x120620UL
-#define PXP2_REG_RQ_CDU_P_SIZE \
- 0x120018UL
-#define PXP2_REG_RQ_CFG_DONE \
- 0x1201b4UL
-#define PXP2_REG_RQ_DBG_ENDIAN_M \
- 0x1201a4UL
-#define PXP2_REG_RQ_DISABLE_INPUTS \
- 0x120330UL
-#define PXP2_REG_RQ_DRAM_ALIGN \
- 0x1205b0UL
-#define PXP2_REG_RQ_DRAM_ALIGN_RD \
- 0x12092cUL
-#define PXP2_REG_RQ_DRAM_ALIGN_SEL \
- 0x120930UL
-#define PXP2_REG_RQ_HC_ENDIAN_M \
- 0x1201a8UL
-#define PXP2_REG_RQ_ONCHIP_AT \
- 0x122000UL
-#define PXP2_REG_RQ_ONCHIP_AT_B0 \
- 0x128000UL
-#define PXP2_REG_RQ_PDR_LIMIT \
- 0x12033cUL
-#define PXP2_REG_RQ_QM_ENDIAN_M \
- 0x120194UL
-#define PXP2_REG_RQ_QM_FIRST_ILT \
- 0x120634UL
-#define PXP2_REG_RQ_QM_LAST_ILT \
- 0x120638UL
-#define PXP2_REG_RQ_QM_P_SIZE \
- 0x120050UL
-#define PXP2_REG_RQ_RBC_DONE \
- 0x1201b0UL
-#define PXP2_REG_RQ_RD_MBS0 \
- 0x120160UL
-#define PXP2_REG_RQ_RD_MBS1 \
- 0x120168UL
-#define PXP2_REG_RQ_SRC_ENDIAN_M \
- 0x12019cUL
-#define PXP2_REG_RQ_SRC_FIRST_ILT \
- 0x12063cUL
-#define PXP2_REG_RQ_SRC_LAST_ILT \
- 0x120640UL
-#define PXP2_REG_RQ_SRC_P_SIZE \
- 0x12006cUL
-#define PXP2_REG_RQ_TM_ENDIAN_M \
- 0x120198UL
-#define PXP2_REG_RQ_TM_FIRST_ILT \
- 0x120644UL
-#define PXP2_REG_RQ_TM_LAST_ILT \
- 0x120648UL
-#define PXP2_REG_RQ_TM_P_SIZE \
- 0x120034UL
-#define PXP2_REG_RQ_WR_MBS0 \
- 0x12015cUL
-#define PXP2_REG_RQ_WR_MBS1 \
- 0x120164UL
-#define PXP2_REG_WR_CDU_MPS \
- 0x1205f0UL
-#define PXP2_REG_WR_CSDM_MPS \
- 0x1205d0UL
-#define PXP2_REG_WR_DBG_MPS \
- 0x1205e8UL
-#define PXP2_REG_WR_DMAE_MPS \
- 0x1205ecUL
-#define PXP2_REG_WR_HC_MPS \
- 0x1205c8UL
-#define PXP2_REG_WR_QM_MPS \
- 0x1205dcUL
-#define PXP2_REG_WR_SRC_MPS \
- 0x1205e4UL
-#define PXP2_REG_WR_TM_MPS \
- 0x1205e0UL
-#define PXP2_REG_WR_TSDM_MPS \
- 0x1205d4UL
-#define PXP2_REG_WR_USDMDP_TH \
- 0x120348UL
-#define PXP2_REG_WR_USDM_MPS \
- 0x1205ccUL
-#define PXP2_REG_WR_XSDM_MPS \
- 0x1205d8UL
-#define PXP_REG_HST_DISCARD_DOORBELLS \
- 0x1030a4UL
-#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \
- 0x1030a8UL
-#define PXP_REG_HST_ZONE_PERMISSION_TABLE \
- 0x103400UL
-#define PXP_REG_PXP_INT_MASK_0 \
- 0x103074UL
-#define PXP_REG_PXP_INT_MASK_1 \
- 0x103084UL
-#define PXP_REG_PXP_INT_STS_CLR_0 \
- 0x10306cUL
-#define PXP_REG_PXP_INT_STS_CLR_1 \
- 0x10307cUL
-#define PXP_REG_PXP_PRTY_MASK \
- 0x103094UL
-#define PXP_REG_PXP_PRTY_STS_CLR \
- 0x10308cUL
-#define QM_REG_BASEADDR \
- 0x168900UL
-#define QM_REG_BASEADDR_EXT_A \
- 0x16e100UL
-#define QM_REG_BYTECRDCMDQ_0 \
- 0x16e6e8UL
-#define QM_REG_CONNNUM_0 \
- 0x168020UL
-#define QM_REG_PF_EN \
- 0x16e70cUL
-#define QM_REG_PF_USG_CNT_0 \
- 0x16e040UL
-#define QM_REG_PTRTBL \
- 0x168a00UL
-#define QM_REG_PTRTBL_EXT_A \
- 0x16e200UL
-#define QM_REG_QM_INT_MASK \
- 0x168444UL
-#define QM_REG_QM_PRTY_MASK \
- 0x168454UL
-#define QM_REG_QM_PRTY_STS_CLR \
- 0x16844cUL
-#define QM_REG_QVOQIDX_0 \
- 0x1680f4UL
-#define QM_REG_SOFT_RESET \
- 0x168428UL
-#define QM_REG_VOQQMASK_0_LSB \
- 0x168240UL
-#define SEM_FAST_REG_PARITY_RST \
- 0x18840UL
-#define SRC_REG_COUNTFREE0 \
- 0x40500UL
-#define SRC_REG_FIRSTFREE0 \
- 0x40510UL
-#define SRC_REG_KEYSEARCH_0 \
- 0x40458UL
-#define SRC_REG_KEYSEARCH_1 \
- 0x4045cUL
-#define SRC_REG_KEYSEARCH_2 \
- 0x40460UL
-#define SRC_REG_KEYSEARCH_3 \
- 0x40464UL
-#define SRC_REG_KEYSEARCH_4 \
- 0x40468UL
-#define SRC_REG_KEYSEARCH_5 \
- 0x4046cUL
-#define SRC_REG_KEYSEARCH_6 \
- 0x40470UL
-#define SRC_REG_KEYSEARCH_7 \
- 0x40474UL
-#define SRC_REG_KEYSEARCH_8 \
- 0x40478UL
-#define SRC_REG_KEYSEARCH_9 \
- 0x4047cUL
-#define SRC_REG_LASTFREE0 \
- 0x40530UL
-#define SRC_REG_NUMBER_HASH_BITS0 \
- 0x40400UL
-#define SRC_REG_SOFT_RST \
- 0x4049cUL
-#define SRC_REG_SRC_PRTY_MASK \
- 0x404c8UL
-#define SRC_REG_SRC_PRTY_STS_CLR \
- 0x404c0UL
-#define TCM_REG_PRS_IFEN \
- 0x50020UL
-#define TCM_REG_TCM_INT_MASK \
- 0x501dcUL
-#define TCM_REG_TCM_PRTY_MASK \
- 0x501ecUL
-#define TCM_REG_TCM_PRTY_STS_CLR \
- 0x501e4UL
-#define TM_REG_EN_LINEAR0_TIMER \
- 0x164014UL
-#define TM_REG_LIN0_MAX_ACTIVE_CID \
- 0x164048UL
-#define TM_REG_LIN0_NUM_SCANS \
- 0x1640a0UL
-#define TM_REG_LIN0_SCAN_ON \
- 0x1640d0UL
-#define TM_REG_LIN0_SCAN_TIME \
- 0x16403cUL
-#define TM_REG_LIN0_VNIC_UC \
- 0x164128UL
-#define TM_REG_TM_INT_MASK \
- 0x1640fcUL
-#define TM_REG_TM_PRTY_MASK \
- 0x16410cUL
-#define TM_REG_TM_PRTY_STS_CLR \
- 0x164104UL
-#define TSDM_REG_ENABLE_IN1 \
- 0x42238UL
-#define TSDM_REG_TSDM_INT_MASK_0 \
- 0x4229cUL
-#define TSDM_REG_TSDM_INT_MASK_1 \
- 0x422acUL
-#define TSDM_REG_TSDM_PRTY_MASK \
- 0x422bcUL
-#define TSDM_REG_TSDM_PRTY_STS_CLR \
- 0x422b4UL
-#define TSEM_REG_FAST_MEMORY \
- 0x1a0000UL
-#define TSEM_REG_INT_TABLE \
- 0x180400UL
-#define TSEM_REG_PASSIVE_BUFFER \
- 0x181000UL
-#define TSEM_REG_PRAM \
- 0x1c0000UL
-#define TSEM_REG_TSEM_INT_MASK_0 \
- 0x180100UL
-#define TSEM_REG_TSEM_INT_MASK_1 \
- 0x180110UL
-#define TSEM_REG_TSEM_PRTY_MASK_0 \
- 0x180120UL
-#define TSEM_REG_TSEM_PRTY_MASK_1 \
- 0x180130UL
-#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \
- 0x180118UL
-#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \
- 0x180128UL
-#define TSEM_REG_VFPF_ERR_NUM \
- 0x180380UL
-#define UCM_REG_UCM_INT_MASK \
- 0xe01d4UL
-#define UCM_REG_UCM_PRTY_MASK \
- 0xe01e4UL
-#define UCM_REG_UCM_PRTY_STS_CLR \
- 0xe01dcUL
-#define UMAC_COMMAND_CONFIG_REG_HD_ENA \
- (0x1<<10)
-#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \
- (0x1<<28)
-#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \
- (0x1<<15)
-#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \
- (0x1<<24)
-#define UMAC_COMMAND_CONFIG_REG_PAD_EN \
- (0x1<<5)
-#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \
- (0x1<<8)
-#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \
- (0x1<<4)
-#define UMAC_COMMAND_CONFIG_REG_RX_ENA \
- (0x1<<1)
-#define UMAC_COMMAND_CONFIG_REG_SW_RESET \
- (0x1<<13)
-#define UMAC_COMMAND_CONFIG_REG_TX_ENA \
- (0x1<<0)
-#define UMAC_REG_COMMAND_CONFIG \
- 0x8UL
-#define UMAC_REG_EEE_WAKE_TIMER \
- 0x6cUL
-#define UMAC_REG_MAC_ADDR0 \
- 0xcUL
-#define UMAC_REG_MAC_ADDR1 \
- 0x10UL
-#define UMAC_REG_MAXFR \
- 0x14UL
-#define UMAC_REG_UMAC_EEE_CTRL \
- 0x64UL
-#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \
- (0x1<<3)
-#define USDM_REG_USDM_INT_MASK_0 \
- 0xc42a0UL
-#define USDM_REG_USDM_INT_MASK_1 \
- 0xc42b0UL
-#define USDM_REG_USDM_PRTY_MASK \
- 0xc42c0UL
-#define USDM_REG_USDM_PRTY_STS_CLR \
- 0xc42b8UL
-#define USEM_REG_FAST_MEMORY \
- 0x320000UL
-#define USEM_REG_INT_TABLE \
- 0x300400UL
-#define USEM_REG_PASSIVE_BUFFER \
- 0x302000UL
-#define USEM_REG_PRAM \
- 0x340000UL
-#define USEM_REG_USEM_INT_MASK_0 \
- 0x300110UL
-#define USEM_REG_USEM_INT_MASK_1 \
- 0x300120UL
-#define USEM_REG_USEM_PRTY_MASK_0 \
- 0x300130UL
-#define USEM_REG_USEM_PRTY_MASK_1 \
- 0x300140UL
-#define USEM_REG_USEM_PRTY_STS_CLR_0 \
- 0x300128UL
-#define USEM_REG_USEM_PRTY_STS_CLR_1 \
- 0x300138UL
-#define USEM_REG_VFPF_ERR_NUM \
- 0x300380UL
-#define VFC_MEMORIES_RST_REG_CAM_RST \
- (0x1<<0)
-#define VFC_MEMORIES_RST_REG_RAM_RST \
- (0x1<<1)
-#define VFC_REG_MEMORIES_RST \
- 0x1943cUL
-#define XCM_REG_XCM_INT_MASK \
- 0x202b4UL
-#define XCM_REG_XCM_PRTY_MASK \
- 0x202c4UL
-#define XCM_REG_XCM_PRTY_STS_CLR \
- 0x202bcUL
-#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \
- (0x1<<0)
-#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \
- (0x1<<1)
-#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \
- (0x1<<2)
-#define XMAC_CTRL_REG_RX_EN \
- (0x1<<1)
-#define XMAC_CTRL_REG_SOFT_RESET \
- (0x1<<6)
-#define XMAC_CTRL_REG_TX_EN \
- (0x1<<0)
-#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \
- (0x1<<7)
-#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \
- (0x1<<18)
-#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \
- (0x1<<17)
-#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \
- (0x1<<1)
-#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \
- (0x1<<0)
-#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \
- (0x1<<3)
-#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \
- (0x1<<4)
-#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \
- (0x1<<5)
-#define XMAC_REG_CLEAR_RX_LSS_STATUS \
- 0x60UL
-#define XMAC_REG_CTRL \
- 0UL
-#define XMAC_REG_CTRL_SA_HI \
- 0x2cUL
-#define XMAC_REG_CTRL_SA_LO \
- 0x28UL
-#define XMAC_REG_EEE_CTRL \
- 0xd8UL
-#define XMAC_REG_EEE_TIMERS_HI \
- 0xe4UL
-#define XMAC_REG_PAUSE_CTRL \
- 0x68UL
-#define XMAC_REG_PFC_CTRL \
- 0x70UL
-#define XMAC_REG_PFC_CTRL_HI \
- 0x74UL
-#define XMAC_REG_RX_LSS_CTRL \
- 0x50UL
-#define XMAC_REG_RX_LSS_STATUS \
- 0x58UL
-#define XMAC_REG_RX_MAX_SIZE \
- 0x40UL
-#define XMAC_REG_TX_CTRL \
- 0x20UL
-#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \
- (0x1<<0)
-#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \
- (0x1<<1)
-#define XSDM_REG_OPERATION_GEN \
- 0x1664c4UL
-#define XSDM_REG_XSDM_INT_MASK_0 \
- 0x16629cUL
-#define XSDM_REG_XSDM_INT_MASK_1 \
- 0x1662acUL
-#define XSDM_REG_XSDM_PRTY_MASK \
- 0x1662bcUL
-#define XSDM_REG_XSDM_PRTY_STS_CLR \
- 0x1662b4UL
-#define XSEM_REG_FAST_MEMORY \
- 0x2a0000UL
-#define XSEM_REG_INT_TABLE \
- 0x280400UL
-#define XSEM_REG_PASSIVE_BUFFER \
- 0x282000UL
-#define XSEM_REG_PRAM \
- 0x2c0000UL
-#define XSEM_REG_VFPF_ERR_NUM \
- 0x280380UL
-#define XSEM_REG_XSEM_INT_MASK_0 \
- 0x280110UL
-#define XSEM_REG_XSEM_INT_MASK_1 \
- 0x280120UL
-#define XSEM_REG_XSEM_PRTY_MASK_0 \
- 0x280130UL
-#define XSEM_REG_XSEM_PRTY_MASK_1 \
- 0x280140UL
-#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \
- 0x280128UL
-#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \
- 0x280138UL
-#define MCPR_ACCESS_LOCK_LOCK (1L<<31)
-#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
-#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
-#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
-#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
-#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
-#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
-#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
-#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
-#define MCPR_NVM_COMMAND_DOIT (1L<<4)
-#define MCPR_NVM_COMMAND_DONE (1L<<3)
-#define MCPR_NVM_COMMAND_FIRST (1L<<7)
-#define MCPR_NVM_COMMAND_LAST (1L<<8)
-#define MCPR_NVM_COMMAND_WR (1L<<5)
-#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
-#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
-#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
-
-
-#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
-#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
-#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
-#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
-#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
-#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
-#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
-#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
-#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
-#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
-#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
-#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
-#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
-#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
-#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
-#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
-#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
-#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
-#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
-#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
-#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
-#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
-#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
-#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
-#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
-#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
-#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
-#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
-#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
-#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
-#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
-
-
-#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
-#define EMAC_LED_100MB_OVERRIDE (1L<<2)
-#define EMAC_LED_10MB_OVERRIDE (1L<<3)
-#define EMAC_LED_OVERRIDE (1L<<0)
-#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
-#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
-#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
-#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
-#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
-#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
-#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
-#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
-#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
-#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
-#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
-#define EMAC_MDIO_STATUS_10MB (1L<<1)
-#define EMAC_MODE_25G_MODE (1L<<5)
-#define EMAC_MODE_HALF_DUPLEX (1L<<1)
-#define EMAC_MODE_PORT_GMII (2L<<2)
-#define EMAC_MODE_PORT_MII (1L<<2)
-#define EMAC_MODE_PORT_MII_10M (3L<<2)
-#define EMAC_MODE_RESET (1L<<0)
-#define EMAC_REG_EMAC_LED 0xc
-#define EMAC_REG_EMAC_MAC_MATCH 0x10
-#define EMAC_REG_EMAC_MDIO_COMM 0xac
-#define EMAC_REG_EMAC_MDIO_MODE 0xb4
-#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
-#define EMAC_REG_EMAC_MODE 0x0
-#define EMAC_REG_EMAC_RX_MODE 0xc8
-#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
-#define EMAC_REG_EMAC_RX_STAT_AC 0x180
-#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
-#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
-#define EMAC_REG_EMAC_TX_MODE 0xbc
-#define EMAC_REG_EMAC_TX_STAT_AC 0x280
-#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
-#define EMAC_REG_RX_PFC_MODE 0x320
-#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
-#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
-#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
-#define EMAC_REG_RX_PFC_PARAM 0x324
-#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
-#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
-#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
-#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
-#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
-#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
-#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
-#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
-#define EMAC_RX_MODE_FLOW_EN (1L<<2)
-#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
-#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
-#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
-#define EMAC_RX_MODE_RESET (1L<<0)
-#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
-#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
-#define EMAC_TX_MODE_FLOW_EN (1L<<4)
-#define EMAC_TX_MODE_RESET (1L<<0)
-
-
-#define MISC_REGISTERS_GPIO_0 0
-#define MISC_REGISTERS_GPIO_1 1
-#define MISC_REGISTERS_GPIO_2 2
-#define MISC_REGISTERS_GPIO_3 3
-#define MISC_REGISTERS_GPIO_CLR_POS 16
-#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
-#define MISC_REGISTERS_GPIO_FLOAT_POS 24
-#define MISC_REGISTERS_GPIO_HIGH 1
-#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
-#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
-#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
-#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
-#define MISC_REGISTERS_GPIO_INT_SET_POS 16
-#define MISC_REGISTERS_GPIO_LOW 0
-#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
-#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
-#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
-#define MISC_REGISTERS_GPIO_SET_POS 8
-#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
-#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \
- (0x1<<19)
-#define MISC_REGISTERS_RESET_REG_1_RST_HC \
- (0x1<<29)
-#define MISC_REGISTERS_RESET_REG_1_RST_PXP \
- (0x1<<26)
-#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \
- (0x1<<27)
-#define MISC_REGISTERS_RESET_REG_1_RST_QM \
- (0x1<<17)
-#define MISC_REGISTERS_RESET_REG_1_SET 0x584
-#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
-#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \
- (0x1<<24)
-#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \
- (0x1<<25)
-#define MISC_REGISTERS_RESET_REG_2_PGLC \
- (0x1<<19)
-#define MISC_REGISTERS_RESET_REG_2_RST_ATC \
- (0x1<<17)
-#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \
- (0x1<<14)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
-#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \
- (0x1<<15)
-#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
-#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
-#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \
- (0x1<<11)
-#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \
- (0x1<<13)
-#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \
- (0x1<<16)
-#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
-#define MISC_REGISTERS_RESET_REG_2_SET 0x594
-#define MISC_REGISTERS_RESET_REG_2_UMAC0 \
- (0x1<<20)
-#define MISC_REGISTERS_RESET_REG_2_UMAC1 \
- (0x1<<21)
-#define MISC_REGISTERS_RESET_REG_2_XMAC \
- (0x1<<22)
-#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \
- (0x1<<23)
-#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
-#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
-#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
-#define MISC_SPIO_CLR_POS 16
-#define MISC_SPIO_FLOAT (0xffL<<24)
-#define MISC_SPIO_FLOAT_POS 24
-#define MISC_SPIO_INPUT_HI_Z 2
-#define MISC_SPIO_INT_OLD_SET_POS 16
-#define MISC_SPIO_OUTPUT_HIGH 1
-#define MISC_SPIO_OUTPUT_LOW 0
-#define MISC_SPIO_SET_POS 8
-#define MISC_SPIO_SPIO4 0x10
-#define MISC_SPIO_SPIO5 0x20
-#define HW_LOCK_MAX_RESOURCE_VALUE 31
-#define HW_LOCK_RESOURCE_DRV_FLAGS 10
-#define HW_LOCK_RESOURCE_GPIO 1
-#define HW_LOCK_RESOURCE_MDIO 0
-#define HW_LOCK_RESOURCE_NVRAM 12
-#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
-#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
-#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
-#define HW_LOCK_RESOURCE_RECOVERY_REG 11
-#define HW_LOCK_RESOURCE_RESET 5
-#define HW_LOCK_RESOURCE_SPIO 2
-
-
-#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
-#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
-#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1U<<31)
-#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
-#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
-#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
-#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
-#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
-#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
-#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
-#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
-#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
-#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
-#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
-#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
-#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
-#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
-#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
-#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
-#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
-#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
-#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
-#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
-#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
-#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
-#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
-#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
-#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
-#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
-#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
-#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
-#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
-#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
-#define HW_PRTY_ASSERT_SET_0 \
-(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_1 \
-(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_2 \
-(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
-#define HW_PRTY_ASSERT_SET_3 \
-(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
-#define HW_PRTY_ASSERT_SET_4 \
-(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
-#define HW_INTERRUT_ASSERT_SET_0 \
-(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
-#define HW_INTERRUT_ASSERT_SET_1 \
-(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
-#define HW_INTERRUT_ASSERT_SET_2 \
-(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
- AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
-
-
+#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1 << 0)
+#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1 << 2)
+#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1 << 5)
+#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1 << 3)
+#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1 << 4)
+#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1 << 1)
+/* [R 1] ATC initalization done */
+#define ATC_REG_ATC_INIT_DONE 0x1100bc
+/* [RW 6] Interrupt mask register #0 read/write */
+#define ATC_REG_ATC_INT_MASK 0x1101c8
+/* [R 6] Interrupt register #0 read */
+#define ATC_REG_ATC_INT_STS 0x1101bc
+/* [RC 6] Interrupt register #0 read clear */
+#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
+/* [RW 5] Parity mask register #0 read/write */
+#define ATC_REG_ATC_PRTY_MASK 0x1101d8
+/* [R 5] Parity register #0 read */
+#define ATC_REG_ATC_PRTY_STS 0x1101cc
+/* [RC 5] Parity register #0 read clear */
+#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
+/* [RW 19] Interrupt mask register #0 read/write */
+#define BRB1_REG_BRB1_INT_MASK 0x60128
+/* [R 19] Interrupt register #0 read */
+#define BRB1_REG_BRB1_INT_STS 0x6011c
+/* [RC 19] Interrupt register #0 read clear */
+#define BRB1_REG_BRB1_INT_STS_CLR 0x60120
+/* [RW 4] Parity mask register #0 read/write */
+#define BRB1_REG_BRB1_PRTY_MASK 0x60138
+/* [R 4] Parity register #0 read */
+#define BRB1_REG_BRB1_PRTY_STS 0x6012c
+/* [RC 4] Parity register #0 read clear */
+#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
+/* [RW 11] The number of blocks guarantied for the MAC port. The register is
+ * applicable only when per_class_guaranty_mode is reset.
+ */
+#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
+#define BRB1_REG_MAC_GUARANTIED_1 0x60240
+/* [R 24] The number of full blocks. */
+#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
+/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
+#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
+/* [RW 10] Write client 0: Assert pause threshold. Not Functional */
+#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
+/* [R 24] The number of full blocks occpied by port. */
+#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
+/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
+#define CCM_REG_CAM_OCCUP 0xd0188
+/* [RW 11] Interrupt mask register #0 read/write */
+#define CCM_REG_CCM_INT_MASK 0xd01e4
+/* [R 11] Interrupt register #0 read */
+#define CCM_REG_CCM_INT_STS 0xd01d8
+/* [RC 11] Interrupt register #0 read clear */
+#define CCM_REG_CCM_INT_STS_CLR 0xd01dc
+/* [RW 27] Parity mask register #0 read/write */
+#define CCM_REG_CCM_PRTY_MASK 0xd01f4
+/* [R 27] Parity register #0 read */
+#define CCM_REG_CCM_PRTY_STS 0xd01e8
+/* [RC 27] Parity register #0 read clear */
+#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define CCM_REG_CFC_INIT_CRD 0xd0204
+/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define CCM_REG_CQM_INIT_CRD 0xd020c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the SDM interface is detected.
+ */
+#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
+/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define CCM_REG_FIC0_INIT_CRD 0xd0210
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define CCM_REG_FIC1_INIT_CRD 0xd0214
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the pbf interface is detected.
+ */
+#define CCM_REG_PBF_LENGTH_MIS 0xd0180
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the STORM interface is detected.
+ */
+#define CCM_REG_STORM_LENGTH_MIS 0xd016c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the tsem interface is detected.
+ */
+#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
+/* [RC 1] Set when message length mismatch (relative to last indication) at
+ * the usem interface is detected.
+ */
+#define CCM_REG_USEM_LENGTH_MIS 0xd017c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the xsem interface is detected.
+ */
+#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
+/* [RW 19] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - message length; [12:6] - message
+ * pointer; 18:13] - next pointer.
+ */
+#define CCM_REG_XX_DESCR_TABLE 0xd0300
+#define CCM_REG_XX_DESCR_TABLE_SIZE 24
+/* [R 7] Used to read the value of XX protection Free counter. */
+#define CCM_REG_XX_FREE 0xd0184
+#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
+/* [RW 7] Interrupt mask register #0 read/write */
+#define CDU_REG_CDU_INT_MASK 0x10103c
+/* [R 7] Interrupt register #0 read */
+#define CDU_REG_CDU_INT_STS 0x101030
+/* [RC 7] Interrupt register #0 read clear */
+#define CDU_REG_CDU_INT_STS_CLR 0x101034
+/* [RW 5] Parity mask register #0 read/write */
+#define CDU_REG_CDU_PRTY_MASK 0x10104c
+/* [R 5] Parity register #0 read */
+#define CDU_REG_CDU_PRTY_STS 0x101040
+/* [RC 5] Parity register #0 read clear */
+#define CDU_REG_CDU_PRTY_STS_CLR 0x101044
+/* [RW 32] logging of error data in case of a CDU load error:
+ * {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
+ * ype_error; ctual_active; ctual_compressed_context};
+ */
+#define CDU_REG_ERROR_DATA 0x101014
+/* [RW 13] activity counter ram access */
+#define CFC_REG_ACTIVITY_COUNTER 0x104400
+#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
+/* [R 1] indication the initializing the activity counter by the hardware
+ * was done.
+ */
+#define CFC_REG_AC_INIT_DONE 0x104078
+/* [R 1] indication the initializing the cams by the hardware was done. */
+#define CFC_REG_CAM_INIT_DONE 0x10407c
+/* [RW 2] Interrupt mask register #0 read/write */
+#define CFC_REG_CFC_INT_MASK 0x104108
+/* [R 2] Interrupt register #0 read */
+#define CFC_REG_CFC_INT_STS 0x1040fc
+/* [RC 2] Interrupt register #0 read clear */
+#define CFC_REG_CFC_INT_STS_CLR 0x104100
+/* [RW 6] Parity mask register #0 read/write */
+#define CFC_REG_CFC_PRTY_MASK 0x104118
+/* [R 6] Parity register #0 read */
+#define CFC_REG_CFC_PRTY_STS 0x10410c
+/* [RC 6] Parity register #0 read clear */
+#define CFC_REG_CFC_PRTY_STS_CLR 0x104110
+/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
+#define CFC_REG_CID_CAM 0x104800
+#define CFC_REG_DEBUG0 0x104050
+/* [R 16] CFC error vector. when the CFC detects an internal error it will
+ * set one of these bits. the bit description can be found in CFC
+ * specifications
+ */
+#define CFC_REG_ERROR_VECTOR 0x10403c
+/* [WB 97] LCID info ram access = {96-vpf; 5:93-pfid; 2:89-type;
+ * 8:85-action; 4-paddrv; 3:20-paddr; 9:4-rstates; -lsf; :0-lstate}
+ */
+#define CFC_REG_INFO_RAM 0x105000
+#define CFC_REG_INFO_RAM_SIZE 1024
+#define CFC_REG_INIT_REG 0x10404c
+/* [RW 22] Link List ram access; data = {prev_pfid; rev_lcid; ext_pfid;
+ * ext_lcid}
+ */
+#define CFC_REG_LINK_LIST 0x104c00
+#define CFC_REG_LINK_LIST_SIZE 256
+/* [R 1] indication the initializing the link list by the hardware was done. */
+#define CFC_REG_LL_INIT_DONE 0x104074
+/* [R 9] Number of allocated LCIDs which are at empty state */
+#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
+/* [R 9] Number of Arriving LCIDs in Link List Block */
+#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
+#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
+/* [R 9] Number of Leaving LCIDs in Link List Block */
+#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
+#define CFC_REG_STRONG_ENABLE_PF 0x104128
+#define CFC_REG_WEAK_ENABLE_PF 0x104124
+/* [RW 32] Interrupt mask register #0 read/write */
+#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
+#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
+/* [R 32] Interrupt register #0 read */
+#define CSDM_REG_CSDM_INT_STS_0 0xc2290
+#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
+/* [RC 32] Interrupt register #0 read clear */
+#define CSDM_REG_CSDM_INT_STS_CLR_0 0xc2294
+#define CSDM_REG_CSDM_INT_STS_CLR_1 0xc22a4
+/* [RW 11] Parity mask register #0 read/write */
+#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
+/* [R 11] Parity register #0 read */
+#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
+/* [RC 11] Parity register #0 read clear */
+#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define CSEM_REG_CSEM_INT_MASK_0 0x200110
+#define CSEM_REG_CSEM_INT_MASK_1 0x200120
+/* [R 32] Interrupt register #0 read */
+#define CSEM_REG_CSEM_INT_STS_0 0x200104
+#define CSEM_REG_CSEM_INT_STS_1 0x200114
+/* [RC 32] Interrupt register #0 read clear */
+#define CSEM_REG_CSEM_INT_STS_CLR_0 0x200108
+#define CSEM_REG_CSEM_INT_STS_CLR_1 0x200118
+/* [RW 32] Parity mask register #0 read/write */
+#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
+#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
+/* [R 32] Parity register #0 read */
+#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
+#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
+/* [RC 32] Parity register #0 read clear */
+#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
+#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each
+ * SEM_FAST register offset.
+ */
+#define CSEM_REG_FAST_MEMORY 0x220000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define CSEM_REG_INT_TABLE 0x200400
+/* [WB 128] Debug only. Passive buffer memory */
+#define CSEM_REG_PASSIVE_BUFFER 0x202000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define CSEM_REG_PRAM 0x240000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
+ */
+#define CSEM_REG_VFPF_ERR_NUM 0x200380
+/* [RW 2] Interrupt mask register #0 read/write */
+#define DBG_REG_DBG_INT_MASK 0xc098
+/* [R 2] Interrupt register #0 read */
+#define DBG_REG_DBG_INT_STS 0xc08c
+/* [RC 2] Interrupt register #0 read clear */
+#define DBG_REG_DBG_INT_STS_CLR 0xc090
+/* [RW 1] Parity mask register #0 read/write */
+#define DBG_REG_DBG_PRTY_MASK 0xc0a8
+/* [R 1] Parity register #0 read */
+#define DBG_REG_DBG_PRTY_STS 0xc09c
+/* [RC 1] Parity register #0 read clear */
+#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
+/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
+ * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID = 0;
+ * 4.Completion function=0; 5.Error handling = 0
+ */
+#define DMAE_REG_BACKWARD_COMP_EN 0x10207c
+/* [RW 32] Commands memory. The address to command X; row Y is to calculated
+ * as 14 * X+Y.
+ */
+#define DMAE_REG_CMD_MEM 0x102400
+#define DMAE_REG_CMD_MEM_SIZE 224
+/* [RW 2] Interrupt mask register #0 read/write */
+#define DMAE_REG_DMAE_INT_MASK 0x102054
+/* [R 2] Interrupt register #0 read */
+#define DMAE_REG_DMAE_INT_STS 0x102048
+/* [RC 2] Interrupt register #0 read clear */
+#define DMAE_REG_DMAE_INT_STS_CLR 0x10204c
+/* [RW 4] Parity mask register #0 read/write */
+#define DMAE_REG_DMAE_PRTY_MASK 0x102064
+/* [R 4] Parity register #0 read */
+#define DMAE_REG_DMAE_PRTY_STS 0x102058
+/* [RC 4] Parity register #0 read clear */
+#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
+/* [RW 1] Command 0 go. */
+#define DMAE_REG_GO_C0 0x102080
+/* [RW 1] Command 1 go. */
+#define DMAE_REG_GO_C1 0x102084
+/* [RW 1] Command 10 go. */
+#define DMAE_REG_GO_C10 0x102088
+/* [RW 1] Command 11 go. */
+#define DMAE_REG_GO_C11 0x10208c
+/* [RW 1] Command 12 go. */
+#define DMAE_REG_GO_C12 0x102090
+/* [RW 1] Command 13 go. */
+#define DMAE_REG_GO_C13 0x102094
+/* [RW 1] Command 14 go. */
+#define DMAE_REG_GO_C14 0x102098
+/* [RW 1] Command 15 go. */
+#define DMAE_REG_GO_C15 0x10209c
+/* [RW 1] Command 2 go. */
+#define DMAE_REG_GO_C2 0x1020a0
+/* [RW 1] Command 3 go. */
+#define DMAE_REG_GO_C3 0x1020a4
+/* [RW 1] Command 4 go. */
+#define DMAE_REG_GO_C4 0x1020a8
+/* [RW 1] Command 5 go. */
+#define DMAE_REG_GO_C5 0x1020ac
+/* [RW 1] Command 6 go. */
+#define DMAE_REG_GO_C6 0x1020b0
+/* [RW 1] Command 7 go. */
+#define DMAE_REG_GO_C7 0x1020b4
+/* [RW 1] Command 8 go. */
+#define DMAE_REG_GO_C8 0x1020b8
+/* [RW 1] Command 9 go. */
+#define DMAE_REG_GO_C9 0x1020bc
+/* [RW 32] Doorbell address for RBC doorbells (function 0). */
+#define DORQ_REG_DB_ADDR0 0x17008c
+/* [RW 6] Interrupt mask register #0 read/write */
+#define DORQ_REG_DORQ_INT_MASK 0x170180
+/* [R 6] Interrupt register #0 read */
+#define DORQ_REG_DORQ_INT_STS 0x170174
+/* [RC 6] Interrupt register #0 read clear */
+#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
+/* [RW 2] Parity mask register #0 read/write */
+#define DORQ_REG_DORQ_PRTY_MASK 0x170190
+/* [R 2] Parity register #0 read */
+#define DORQ_REG_DORQ_PRTY_STS 0x170184
+/* [RC 2] Parity register #0 read clear */
+#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
+/* [R 13] Current value of the DQ FIFO fill level according to following
+ * pointer. The range is 0 - 256 FIFO rows; where each row stands for the
+ * doorbell.
+ */
+#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
+/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
+ * equal to full threshold; reset on full clear.
+ */
+#define DORQ_REG_DQ_FULL_ST 0x1700c0
+#define DORQ_REG_MAX_RVFID_SIZE 0x1701ec
+#define DORQ_REG_MODE_ACT 0x170008
+/* [RW 5] The normal mode CID extraction offset. */
+#define DORQ_REG_NORM_CID_OFST 0x17002c
+#define DORQ_REG_PF_USAGE_CNT 0x1701d0
+/* [R 4] Current value of response A counter credit. Initial credit is
+ * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+ * register.
+ */
+#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
+/* [R 4] Current value of response B counter credit. Initial credit is
+ * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+ * register.
+ */
+#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
+#define DORQ_REG_VF_NORM_CID_BASE 0x1701a0
+#define DORQ_REG_VF_NORM_CID_OFST 0x1701f4
+#define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4
+#define DORQ_REG_VF_NORM_VF_BASE 0x1701a8
+/* [RW 10] VF type validation mask value */
+#define DORQ_REG_VF_TYPE_MASK_0 0x170218
+/* [RW 17] VF type validation Min MCID value */
+#define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8
+/* [RW 17] VF type validation Max MCID value */
+#define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298
+/* [RW 10] VF type validation comp value */
+#define DORQ_REG_VF_TYPE_VALUE_0 0x170258
+#define DORQ_REG_VF_USAGE_CNT 0x170320
+#define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340
+#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1 << 4)
+#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1 << 0)
+#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1 << 3)
+#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1 << 7)
+#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1 << 2)
+#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1 << 1)
+#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1 << 0)
+#define HC_REG_AGG_INT_0 0x108050
+#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
+#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
+#define HC_REG_COMMAND_REG 0x108180
+#define HC_REG_CONFIG_0 0x108000
+#define HC_REG_CONFIG_1 0x108004
+/* [RW 7] Interrupt mask register #0 read/write */
+#define HC_REG_HC_INT_MASK 0x108090
+/* [R 7] Interrupt register #0 read */
+#define HC_REG_HC_INT_STS 0x108084
+/* [RC 7] Interrupt register #0 read clear */
+#define HC_REG_HC_INT_STS_CLR 0x108088
+/* [RW 3] Parity mask register #0 read/write */
+#define HC_REG_HC_PRTY_MASK 0x1080a0
+/* [R 3] Parity register #0 read */
+#define HC_REG_HC_PRTY_STS 0x108094
+/* [RC 3] Parity register #0 read clear */
+#define HC_REG_HC_PRTY_STS_CLR 0x108098
+#define HC_REG_INT_MASK 0x108108
+#define HC_REG_LEADING_EDGE_0 0x108040
+#define HC_REG_MAIN_MEMORY 0x108800
+#define HC_REG_MAIN_MEMORY_SIZE 152
+#define HC_REG_TRAILING_EDGE_0 0x108044
+#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1 << 1)
+#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1 << 0)
+#define IGU_REG_ATTENTION_ACK_BITS 0x130108
+/* [R 4] Debug: attn_fsm */
+#define IGU_REG_ATTN_FSM 0x130054
+#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
+#define IGU_REG_ATTN_MSG_ADDR_L 0x130120
+/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
+ * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
+ * write done didn't receive.
+ */
+#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
+#define IGU_REG_BLOCK_CONFIGURATION 0x130000
+#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
+#define IGU_REG_COMMAND_REG_CTRL 0x13012c
+/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
+ * is clear. The bits in this registers are set and clear via the producer
+ * command. Data valid only in addresses 0-4. all the rest are zero.
+ */
+#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
+/* [R 5] Debug: ctrl_fsm */
+#define IGU_REG_CTRL_FSM 0x130064
+/* [R 1] data available for error memory. If this bit is clear do not red
+ * from error_handling_memory.
+ */
+#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
+/* [RW 11] Interrupt mask register #0 read/write */
+#define IGU_REG_IGU_INT_MASK 0x130098
+/* [R 11] Interrupt register #0 read */
+#define IGU_REG_IGU_INT_STS 0x13008c
+/* [RC 11] Interrupt register #0 read clear */
+#define IGU_REG_IGU_INT_STS_CLR 0x130090
+/* [RW 11] Parity mask register #0 read/write */
+#define IGU_REG_IGU_PRTY_MASK 0x1300a8
+/* [R 11] Parity register #0 read */
+#define IGU_REG_IGU_PRTY_STS 0x13009c
+/* [RC 11] Parity register #0 read clear */
+#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
+/* [R 4] Debug: int_handle_fsm */
+#define IGU_REG_INT_HANDLE_FSM 0x130050
+#define IGU_REG_LEADING_EDGE_LATCH 0x130134
+/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
+ * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
+ * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number);
+ */
+#define IGU_REG_MAPPING_MEMORY 0x131000
+#define IGU_REG_MAPPING_MEMORY_SIZE 136
+#define IGU_REG_PBA_STATUS_LSB 0x130138
+#define IGU_REG_PBA_STATUS_MSB 0x13013c
+#define IGU_REG_PCI_PF_MSIX_EN 0x130144
+#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
+#define IGU_REG_PCI_PF_MSI_EN 0x130140
+/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
+ * pending; 1 = pending. Pendings means interrupt was asserted; and write
+ * done was not received. Data valid only in addresses 0-4. all the rest are
+ * zero.
+ */
+#define IGU_REG_PENDING_BITS_STATUS 0x130300
+#define IGU_REG_PF_CONFIGURATION 0x130154
+/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
+ * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
+ * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
+ * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
+ * - In backward compatible mode; for non default SB; each even line in the
+ * memory holds the U producer and each odd line hold the C producer. The
+ * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
+ * last 20 producers are for the DSB for each PF. each PF has five segments
+ * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
+ * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods;
+ */
+#define IGU_REG_PROD_CONS_MEMORY 0x132000
+/* [R 3] Debug: pxp_arb_fsm */
+#define IGU_REG_PXP_ARB_FSM 0x130068
+/* [RW 6] Write one for each bit will reset the appropriate memory. When the
+ * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
+ * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
+ * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics;
+ */
+#define IGU_REG_RESET_MEMORIES 0x130158
+/* [R 4] Debug: sb_ctrl_fsm */
+#define IGU_REG_SB_CTRL_FSM 0x13004c
+#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
+#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
+#define IGU_REG_SB_MASK_LSB 0x130164
+#define IGU_REG_SB_MASK_MSB 0x130168
+/* [RW 16] Number of command that were dropped without causing an interrupt
+ * due to: read access for WO BAR address; or write access for RO BAR
+ * address or any access for reserved address or PCI function error is set
+ * and address is not MSIX; PBA or cleanup
+ */
+#define IGU_REG_SILENT_DROP 0x13016c
+/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
+ * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
+ * PF; 68-71 number of ATTN messages per PF
+ */
+#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
+#define IGU_REG_TRAILING_EDGE_LATCH 0x130104
+#define IGU_REG_VF_CONFIGURATION 0x130170
+/* [WB_R 32] Each bit represent write done pending bits status for that SB
+ * (MSI/MSIX message was sent and write done was not received yet). 0 =
+ * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero.
+ */
+#define IGU_REG_WRITE_DONE_PENDING 0x130480
+#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
+#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
+#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
+#define MCP_REG_MCPR_GP_INPUTS 0x800c0
+#define MCP_REG_MCPR_GP_OENABLE 0x800c8
+#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
+#define MCP_REG_MCPR_IMC_COMMAND 0x85900
+#define MCP_REG_MCPR_IMC_DATAREG0 0x85920
+#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
+#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
+#define MCP_REG_MCPR_NVM_ADDR 0x8640c
+#define MCP_REG_MCPR_NVM_CFG4 0x8642c
+#define MCP_REG_MCPR_NVM_COMMAND 0x86400
+#define MCP_REG_MCPR_NVM_READ 0x86410
+#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
+#define MCP_REG_MCPR_NVM_WRITE 0x86408
+#define MCP_REG_MCPR_SCRATCH 0xa0000
+#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1 << 1)
+#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1 << 0)
+/* [R 32] read first 32 bit after inversion of function 0. mapped as
+ * follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
+ * [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
+ * GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
+ * glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
+ * [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
+ * MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
+ * Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
+ * interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
+ * error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
+ * interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30]
+ * PBClient Parity error; [31] PBClient Hw interrupt;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
+/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
+ * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+ * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+ * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+ * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+ * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+ * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+ * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+ * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+ * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+ * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+ * Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31]
+ * PBClient Hw interrupt;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
+/* [R 32] read second 32 bit after inversion of function 0. mapped as
+ * follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error;
+ * [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
+ * [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
+ * XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+ * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+ * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+ * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+ * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+ * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+ * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+ * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
+/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
+ * PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw
+ * interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
+ * Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
+ * interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+ * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+ * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+ * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+ * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+ * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+ * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+ * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
+/* [R 32] read third 32 bit after inversion of function 0. mapped as
+ * follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
+ * error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
+ * PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+ * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+ * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+ * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+ * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+ * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+ * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+ * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+ * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+ * attn1;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
+/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
+ * CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
+ * Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
+ * Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
+ * error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
+ * interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
+ * MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
+ * Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
+ * timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
+ * func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
+ * func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
+ * timers attn_4 func1; [30] General attn0; [31] General attn1;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
+/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
+ * follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
+/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
+ * General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
+ * [4] General attn6; [5] General attn7; [6] General attn8; [7] General
+ * attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
+ * General attn13; [12] General attn14; [13] General attn15; [14] General
+ * attn16; [15] General attn17; [16] General attn18; [17] General attn19;
+ * [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
+ * RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
+ * RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
+ * attention; [27] GRC Latched reserved access attention; [28] MCP Latched
+ * rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
+ * ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
+/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
+ * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved;
+ */
+#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
+/* [W 14] write to this register results with the clear of the latched
+ * signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
+ * d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
+ * latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
+ * GRC Latched reserved access attention; one in d7 clears Latched
+ * rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
+ * Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
+ * ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
+ * pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
+ * from this register return zero
+ */
+#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
+/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+ * 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw
+ * interrupt;
+ */
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
+/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
+ * 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw
+ * interrupt;
+ */
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
+/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
+/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
+/* [RW 32] fourth 32b for enabling the output for close the gate nig. Mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
+#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
+/* [RW 32] fourth 32b for enabling the output for close the gate pxp. Mapped
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
+#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
+/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
+ * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved;
+ */
+#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
+/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
+ * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
+ * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
+ * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
+ * parity; [31-10] Reserved;
+ */
+#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
+/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
+ * 128 bit vector
+ */
+#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
+#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
+#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
+#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
+#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
+#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
+#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
+#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
+#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
+#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
+#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
+#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
+#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
+#define MISC_REG_AEU_GENERAL_MASK 0xa61c
+/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
+ * [9:8] = reserved. 0 = mask; 1 = unmask
+ */
+#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
+#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
+/* [RW 1] If set a system kill occurred. Reset on POR reset. */
+#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
+/* [RW 32] Represent the status of the input vector to the AEU when a system
+ * kill occurred. The register is reset in por reset. Mapped as follows: [0]
+ * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+ * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+ * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+ * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+ * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+ * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+ * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+ * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+ * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+ * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+ * Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31]
+ * PBClient Hw interrupt. Reset on POR reset.
+ */
+#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
+#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
+#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
+#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
+/* [R 32] This field indicates the type of the device. '0' - 2 Ports; '1' -
+ * 1 Port. Global register.
+ */
+#define MISC_REG_BOND_ID 0xa400
+/* [R 16] These bits indicate the part number for the chip. Global register. */
+#define MISC_REG_CHIP_NUM 0xa408
+/* [R 4] These bits indicate the base revision of the chip. This value
+ * starts at 0x0 for the A0 tape-out and increments by one for each
+ * all-layer tape-out. Global register.
+ */
+#define MISC_REG_CHIP_REV 0xa40c
+/* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
+ * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
+ * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1].
+ */
+#define MISC_REG_CHIP_TYPE 0xac60
+#define MISC_REG_CHIP_TYPE_57811_MASK (1 << 1)
+#define MISC_REG_CPMU_LP_DR_ENABLE 0xa858
+/* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
+ * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
+ * 25MHz. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c
+/* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
+ * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0
+/* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
+ * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
+ * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
+ * the FW command that all Queues are empty is disabled. When 0 indicates
+ * that the FW command that all Queues are empty is enabled. [2] - FW Early
+ * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early
+ * Exit command is disabled. When 0 indicates that the FW Early Exit command
+ * is enabled. This bit applicable only in the EXIT Events Mask registers.
+ * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
+ * is disabled. When 0 indicates that the PBF Request indication is enabled.
+ * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
+ * Request indication is disabled. When 0 indicates that the Tx Other Than
+ * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
+ * indicates that the RX EEE LPI Status indication is disabled. When 0
+ * indicates that the RX EEE LPI Status indication is enabled. In the EXIT
+ * Events Masks registers; this bit masks the falling edge detect of the LPI
+ * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
+ * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
+ * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
+ * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
+ * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
+ * IDLE indication is disabled. When 0 indicates that the QM IDLE indication
+ * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
+ * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
+ * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
+ * Status Mask. When 1 indicates that the L1 Status indication from the PCIE
+ * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
+ * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this
+ * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
+ * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
+ * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
+ * indicates that the P0 EEE LPI REQ indication is disabled. When =0
+ * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
+ * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
+ * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
+ * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
+ * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
+ * REQ indication is disabled. When =0 indicates that the L1 indication is
+ * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
+ * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx
+ * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
+ * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
+ * bit is applicable only in the EXIT Events Masks registers. [17] - L1
+ * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling
+ * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
+ * When =0 indicates that the L1 Status Falling Edge Detect indication from
+ * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
+ * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880
+/* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
+ * that the Vmain SM end state is disabled. When 0 indicates that the Vmain
+ * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
+ * that the FW command that all Queues are empty is disabled. When 0
+ * indicates that the FW command that all Queues are empty is enabled. [2] -
+ * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW
+ * Early Exit command is disabled. When 0 indicates that the FW Early Exit
+ * command is enabled. This bit applicable only in the EXIT Events Mask
+ * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
+ * indication is disabled. When 0 indicates that the PBF Request indication
+ * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
+ * Than PBF Request indication is disabled. When 0 indicates that the Tx
+ * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
+ * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.
+ * When 0 indicates that the RX LPI Status indication is enabled. In the
+ * EXIT Events Masks registers; this bit masks the falling edge detect of
+ * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
+ * indicates that the Tx Pause indication is disabled. When 0 indicates that
+ * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
+ * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
+ * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
+ * indicates that the QM IDLE indication is disabled. When 0 indicates that
+ * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]
+ * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
+ * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
+ * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
+ * Status indication from the PCIE CORE is disabled. When 0 indicates that
+ * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the
+ * EXIT Events Masks registers; this bit masks the falling edge detect of
+ * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
+ * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
+ * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
+ * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
+ * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
+ * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
+ * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
+ * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
+ * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
+ * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
+ * indicates that the L1 REQ indication is disabled. When =0 indicates that
+ * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
+ * When =1 indicates that the RX EEE LPI Status Falling Edge Detect
+ * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
+ * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE
+ * LPI is on - off). This bit is applicable only in the EXIT Events Masks
+ * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
+ * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled
+ * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
+ * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
+ * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.
+ * Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888
+/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
+ * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
+ * register. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
+/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
+ * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
+ * register. Reset on hard reset.
+ */
+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
+/* [RW 32] The following driver registers(1...16) represent 16 drivers and
+ * 32 clients. Each client can be controlled by one driver only. One in each
+ * bit represent that this driver control the appropriate client (Ex: bit 5
+ * is set means this driver control client number 5). addr1 = set; addr0 =
+ * clear; read from both addresses will give the same result = status. write
+ * to address 1 will set a request to control all the clients that their
+ * appropriate bit (in the write command) is set. if the client is free (the
+ * appropriate bit in all the other drivers is clear) one will be written to
+ * that driver register; if the client isn't free the bit will remain zero.
+ * if the appropriate bit is set (the driver request to gain control on a
+ * client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
+ * interrupt will be asserted). write to address 0 will set a request to
+ * free all the clients that their appropriate bit (in the write command) is
+ * set. if the appropriate bit is clear (the driver request to free a client
+ * it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
+ * be asserted).
+ */
+#define MISC_REG_DRIVER_CONTROL_1 0xa510
+#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
+/* [R 1] Status of four port mode path swap input pin. */
+#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
+/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
+ * the path_swap output is equal to 4 port mode path swap input pin; if it
+ * is 1 - the path_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the path_swap output. Reset on Hard reset.
+ */
+#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
+/* [R 1] Status of 4 port mode port swap input pin. */
+#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
+/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
+ * the port_swap output is equal to 4 port mode port swap input pin; if it
+ * is 1 - the port_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the port_swap output. Reset on Hard reset.
+ */
+#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
+/* [RW 32] Debug only: spare RW register reset by core reset. Global
+ * register. Reset on core reset.
+ */
+#define MISC_REG_GENERIC_CR_0 0xa460
+#define MISC_REG_GENERIC_CR_1 0xa464
+/* [RW 32] Debug only: spare RW register reset by por reset. Global
+ * register. Reset on POR reset.
+ */
+#define MISC_REG_GENERIC_POR_1 0xa474
+/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
+ * use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
+ * can not be configured as an output. Each output has its output enable in
+ * the MCP register space; but this bit needs to be set to make use of that.
+ * Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
+ * set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
+ * When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
+ * the i/o to an output and will drive the TimeSync output. Bit[31:7]:
+ * spare. Global register. Reset by hard reset.
+ */
+#define MISC_REG_GEN_PURP_HWG 0xa9a0
+/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
+ * these bits is written as a '1'; the corresponding GPIO bit will turn off
+ * it's drivers and become an input. This is the reset state of all GPIO
+ * pins. The read value of these bits will be a '1' if that last command
+ * (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
+ * [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
+ * as a '1'; the corresponding GPIO bit will drive low. The read value of
+ * these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
+ * this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
+ * SET When any of these bits is written as a '1'; the corresponding GPIO
+ * bit will drive high (if it has that capability). The read value of these
+ * bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
+ * bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
+ * RO; These bits indicate the read value of each of the eight GPIO pins.
+ * This is the result value of the pin; not the drive value. Writing these
+ * bits will have not effect. Global register.
+ */
+#define MISC_REG_GPIO 0xa490
+/* [RW 8] These bits enable the GPIO_INTs to signals event to the
+ * IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
+ * p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
+ * [7] p1_gpio_3; Global register.
+ */
+#define MISC_REG_GPIO_EVENT_EN 0xa2bc
+/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
+ * '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
+ * This will acknowledge an interrupt on the falling edge of corresponding
+ * GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
+ * Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
+ * register. This will acknowledge an interrupt on the rising edge of
+ * corresponding GPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
+ * OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
+ * value. When the ~INT_STATE bit is set; this bit indicates the OLD value
+ * of the pin such that if ~INT_STATE is set and this bit is '0'; then the
+ * interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
+ * is '1'; then the interrupt is due to a high to low edge (reset value 0).
+ * [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
+ * current GPIO interrupt state for each GPIO pin. This bit is cleared when
+ * the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
+ * set when the GPIO input does not match the current value in #OLD_VALUE
+ * (reset value 0). Global register.
+ */
+#define MISC_REG_GPIO_INT 0xa494
+/* [R 28] this field hold the last information that caused reserved
+ * attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ * [27:24] the master that caused the attention - according to the following
+ * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+ * dbu; 8 = dmae
+ */
+#define MISC_REG_GRC_RSV_ATTN 0xa3c0
+/* [R 28] this field hold the last information that caused timeout
+ * attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ * [27:24] the master that caused the attention - according to the following
+ * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+ * dbu; 8 = dmae
+ */
+#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
+/* [R 10] Holds the last FID that caused timeout attention. Need to be used
+ * in conjunction with ~misc_registers_timeout_attn; where 3 bits of
+ * function (3 lsb) are also represented. Bit[2:0] - PFID; bit[3] - VFID
+ * valid; bit[9:4] - VFID. Global register.
+ */
+#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa714
+/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
+ * reset.
+ */
+#define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
+/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
+#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
+/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
+ * reset.
+ */
+#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
+/* [RW 8] Interrupt mask register #0 read/write */
+#define MISC_REG_MISC_INT_MASK 0xa388
+/* [R 8] Interrupt register #0 read */
+#define MISC_REG_MISC_INT_STS 0xa37c
+/* [RC 8] Interrupt register #0 read clear */
+#define MISC_REG_MISC_INT_STS_CLR 0xa380
+/* [RW 1] Parity mask register #0 read/write */
+#define MISC_REG_MISC_PRTY_MASK 0xa398
+/* [R 1] Parity register #0 read */
+#define MISC_REG_MISC_PRTY_STS 0xa38c
+/* [RC 1] Parity register #0 read clear */
+#define MISC_REG_MISC_PRTY_STS_CLR 0xa390
+/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
+ * assertion. Global register.
+ */
+#define MISC_REG_PCIE_HOT_RESET 0xa618
+/* [R 1] Status of 4 port mode enable input pin. */
+#define MISC_REG_PORT4MODE_EN 0xa750
+/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
+ * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
+ * the port4mode_en output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the port4mode_en output. Reset on Hard reset.
+ */
+#define MISC_REG_PORT4MODE_EN_OVWR 0xa720
+/* [RW 32] reset reg#1; rite/read one = the specific block is out of reset;
+ * write/read zero = the specific block is in reset; addr 0-wr- the write
+ * value will be written to the register; addr 1-set - one will be written
+ * to all the bits that have the value of one in the data written (bits that
+ * have the value of zero will not be change) ; addr 2-clear - zero will be
+ * written to all the bits that have the value of one in the data written
+ * (bits that have the value of zero will not be change); addr 3-ignore;
+ * read ignore from all addr except addr 00; inside order of the bits is:
+ * [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5]
+ * rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10]
+ * rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15]
+ * rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20]
+ * rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25]
+ * rst_cfc; [26] rst_pxp_hst; [27] rst_pxpv (global register); [28]
+ * rst_rbcp; [29] rst_hc; [30] rst_dmae; [31] rst_semi_rtc;
+ */
+#define MISC_REG_RESET_REG_1 0xa580
+#define MISC_REG_RESET_REG_2 0xa590
+/* [RW 22] 22 bit GRC address where the scratch-pad of the MCP that is
+ * shared with the driver resides
+ */
+#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
+/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
+ * the corresponding SPIO bit will turn off it's drivers and become an
+ * input. This is the reset state of all SPIO pins. The read value of these
+ * bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
+ * bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
+ * is written as a '1'; the corresponding SPIO bit will drive low. The read
+ * value of these bits will be a '1' if that last command (#SET; #CLR; or
+ * #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
+ * these bits is written as a '1'; the corresponding SPIO bit will drive
+ * high (if it has that capability). The read value of these bits will be a
+ * '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
+ * (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
+ * each of the eight SPIO pins. This is the result value of the pin; not the
+ * drive value. Writing these bits will have not effect. Each 8 bits field
+ * is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
+ * from VAUX. (This is an output pin only; the FLOAT field is not applicable
+ * for this pin); [1] VAUX Disable; when pulsed low; disables supply form
+ * VAUX. (This is an output pin only; FLOAT field is not applicable for this
+ * pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
+ * select VAUX supply. (This is an output pin only; it is not controlled by
+ * the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
+ * field is not applicable for this pin; only the VALUE fields is relevant -
+ * it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
+ * Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
+ * device ID select; read by UMP firmware. Global register.
+ */
+#define MISC_REG_SPIO 0xa4fc
+/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
+ * according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
+ * [7:6] reserved. Global register.
+ */
+#define MISC_REG_SPIO_EVENT_EN 0xa2b8
+/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
+ * corresponding bit in the #OLD_VALUE register. This will acknowledge an
+ * interrupt on the falling edge of corresponding SPIO input (reset value
+ * 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
+ * in the #OLD_VALUE register. This will acknowledge an interrupt on the
+ * rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
+ * RO; These bits indicate the old value of the SPIO input value. When the
+ * ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
+ * that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
+ * to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
+ * interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
+ * RO; These bits indicate the current SPIO interrupt state for each SPIO
+ * pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
+ * command bit is written. This bit is set when the SPIO input does not
+ * match the current value in #OLD_VALUE (reset value 0). Global register.
+ */
+#define MISC_REG_SPIO_INT 0xa500
+/* [R 1] Status of two port mode path swap input pin. */
+#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
+/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
+ * path_swap output is equal to 2 port mode path swap input pin; if it is 1
+ * - the path_swap output is equal to bit[1] of this register; [1] -
+ * Overwrite value. If bit[0] of this register is 1 this is the value that
+ * receives the path_swap output. Reset on Hard reset.
+ */
+#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
+/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
+ * loaded; 0-prepare; -unprepare. Global register. Reset on hard reset.
+ */
+#define MISC_REG_UNPREPARED 0xa424
+/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
+ * not it is the recipient of the message on the MDIO interface. The value
+ * is compared to the value on ctrl_md_devad. Drives output
+ * misc_xgxs0_phy_addr. Global register.
+ */
+#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
+/* [RW 10] reset reg#3; rite/read one = the specific block is out of reset;
+ * write/read zero = the specific block is in reset; addr 0-wr- the write
+ * value will be written to the register; addr 1-set - one will be written
+ * to all the bits that have the value of one in the data written (bits that
+ * have the value of zero will not be change) ; addr 2-clear - zero will be
+ * written to all the bits that have the value of one in the data written
+ * (bits that have the value of zero will not be change); addr 3-ignore;
+ * read ignore from all addr except addr 00. [0]: rstb_hw: Active low reset
+ * which when asserted drives entire WC into the reset state. All flops
+ * which within WC are driven into an initial state; as well as the analog
+ * core. Output clocks txck_out; rxck0_10g; and clk_25 will be driven to 0
+ * upon its assertion. [1]: iddq. Enables iddq testing where the supply
+ * current (Idd) is measured in the quiescent state. [2]: pwrdwn: Active
+ * high control which forces the analog core of the WC into power-down mode;
+ * and forces digital logic of the WC into reset. Output clock (refclk)
+ * remains active. [3]: pwrdwn_sd: Power down signal detect. [4]:
+ * txd10g_fifo_rstb: Transmit 10Gbps FIFO reset; active low. Used to reset
+ * the transmit FIFO used in xlgmii operation. [8:5]: txd1g_fifo_rstb:
+ * Transmit 1Gbps FIFO reset; active low. Used to reset the per-lane
+ * transmit FIFOs used in the mii/gmii operation. [9]:
+ * txd10g_fifo_rstb_dxgxs1: Transmit 10Gbps DXGXS FIFO reset; active low.
+ * Used to reset the transmit FIFO used in the DXGXS logic in xlgmii
+ * operation. Global register.
+ */
+#define MISC_REG_WC0_RESET 0xac30
+/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
+ * side. This should be less than or equal to phy_port_mode; if some of the
+ * ports are not used. This enables reduction of frequency on the core side.
+ * This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
+ * Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
+ * input for the XMAC_MP core; and should be changed only while reset is
+ * held low. Reset on Hard reset.
+ */
+#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
+/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
+ * Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
+ * 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
+ * XMAC_MP core; and should be changed only while reset is held low. Reset
+ * on Hard reset.
+ */
+#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
+/* [RW 1] Interrupt mask register #0 read/write */
+#define MSTAT_REG_MSTAT_INT_MASK 0x7fc
+/* [R 1] Interrupt register #0 read */
+#define MSTAT_REG_MSTAT_INT_STS 0x7f0
+/* [RC 1] Interrupt register #0 read clear */
+#define MSTAT_REG_MSTAT_INT_STS_CLR 0x7f4
+/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
+ * Reads from this register will clear bits 31:0.
+ */
+#define MSTAT_REG_RX_STAT_GR64_LO 0x200
+/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
+ * 31:0. Reads from this register will clear bits 31:0.
+ */
+#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
+#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1 << 0)
+#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1 << 0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1 << 0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1 << 9)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1 << 15)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf << 18)
+/* [R 1] Input enable for RX_BMAC0 IF */
+#define NIG_REG_BMAC0_IN_EN 0x100ac
+/* [R 1] output enable for TX_BMAC0 IF */
+#define NIG_REG_BMAC0_OUT_EN 0x100e0
+/* [R 1] output enable for TX BMAC pause port 0 IF */
+#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
+/* [R 1] output enable for RX_BMAC0_REGS IF */
+#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
+/* [RW 1] output enable for RX BRB1 port0 IF */
+#define NIG_REG_BRB0_OUT_EN 0x100f8
+/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
+#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
+/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
+#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
+/* [WB_W 90] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
+ * error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
+ * 72:73]-vnic_num; 89:74]-sideband_info
+ */
+#define NIG_REG_DEBUG_PACKET_LB 0x10800
+/* [R 1] FIFO empty in DEBUG_FIFO in NIG_TX_DBG */
+#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418
+/* [R 1] FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT0 */
+#define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420
+/* [R 1] FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT1 */
+#define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862c
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634
+/* [R 1] PBF FIFO empty flag. */
+#define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638
+/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
+ * packets from PBFare not forwarded to the MAC and just deleted from FIFO.
+ * First packet may be deleted from the middle. And last packet will be
+ * always deleted till the end.
+ */
+#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
+/* [R 1] Output enable to EMAC0 */
+#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
+/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
+ * to emac for port0; other way to bmac for port0
+ */
+#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
+/* [R 1] FIFO empty in MNG_FIFO in NIG_TX_PORT0 */
+#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460
+/* [R 1] FIFO empty in MNG_FIFO in NIG_TX_PORT1 */
+#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474
+/* [RW 1] Input enable for TX UMP management packet port0 IF */
+#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
+/* [R 1] Input enable for RX_EMAC0 IF */
+#define NIG_REG_EMAC0_IN_EN 0x100a4
+/* [R 1] output enable for TX EMAC pause port 0 IF */
+#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
+/* [R 1] status from emac0. This bit is set when MDINT from either the
+ * EXT_MDINT pin or from the Copper PHY is driven low. This condition must
+ * be cleared in the attached PHY device that is driving the MINT pin.
+ */
+#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
+/* [R 48] This address space contains BMAC0 registers. The BMAC registers
+ * are described in appendix A. In order to access the BMAC0 registers; the
+ * base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
+ * added to each BMAC register offset
+ */
+#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
+/* [R 48] This address space contains BMAC1 registers. The BMAC registers
+ * are described in appendix A. In order to access the BMAC0 registers; the
+ * base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
+ * added to each BMAC register offset
+ */
+#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
+/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
+/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
+ * packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16]
+ */
+#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
+/* [R 1] FIFO empty in EOP descriptor FIFO of port 0 in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ec
+/* [R 1] FIFO empty in EOP descriptor FIFO of port 1 in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8
+/* [R 1] FIFO empty in PBF_DELAY_lb_FIFO in NIG_RX_lb */
+#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508
+/* [R 1] FIFO empty in dscr_fifo in NIG_RX_RMP block */
+#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530
+/* [R 1] FIFO empty in dscr_fifo in NIG_RX_RMP block */
+#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538
+/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
+ * logic for interrupts must be used. Enable per bit of interrupt of
+ * ~latch_status.latch_status
+ */
+#define NIG_REG_LATCH_BC_0 0x16210
+/* [RW 27] Latch for each interrupt from Unicore.b[0]
+ * status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
+ * b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
+ * b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
+ * b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
+ * b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
+ * b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
+ * b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
+ * b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
+ * b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
+ * b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
+ * b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
+ * b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs
+ */
+#define NIG_REG_LATCH_STATUS_0 0x18000
+/* [RW 1] led 10g for port 0 */
+#define NIG_REG_LED_10G_P0 0x10320
+/* [RW 1] Port0: This bit is set to enable the use of the
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
+ * defined below. If this bit is cleared; then the blink rate will be about
+ * 8Hz.
+ */
+#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
+/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
+ * Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
+ * is reset to 0x080; giving a default blink period of approximately 8Hz.
+ */
+#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
+/* [RW 1] Port0: If set along with the
+ * s_led_control_override_traffic_p0.led_control_override_traffic_p0
+ * bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
+ * bit; the Traffic LED will blink with the blink rate specified in
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+ * ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+ * fields.
+ */
+#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
+/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
+ * Traffic LED will then be controlled via bit ~nig_registers_
+ * led_control_traffic_p0.led_control_traffic_p0 and bit
+ * ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0
+ */
+#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
+/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
+ * turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
+ * set; the LED will blink with blink rate specified in
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+ * ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+ * fields.
+ */
+#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
+/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
+ * 9-11PHY7; 12 MAC4; 13-15 PHY10;
+ */
+#define NIG_REG_LED_MODE_P0 0x102f0
+/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
+ * tsdm enable; b2- usdm enable
+ */
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
+/* [RW 1] SAFC enable for port0. This register may get 1 only when
+ * ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
+ * port
+ */
+#define NIG_REG_LLFC_ENABLE_0 0x16208
+#define NIG_REG_LLFC_ENABLE_1 0x1620c
+/* [RW 16] classes are high-priority for port0 */
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
+/* [RW 16] classes are low-priority for port0 */
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
+/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
+#define NIG_REG_LLFC_OUT_EN_0 0x160c8
+#define NIG_REG_LLFC_OUT_EN_1 0x160cc
+#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
+#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
+#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
+#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
+/* [RW 2] Determine the classification participants. 0: no classification.1:
+ * classification upon VLAN id. 2: classification upon MAC address. 3:
+ * classification upon both VLAN id & MAC addr.
+ */
+#define NIG_REG_LLH0_CLS_TYPE 0x16080
+#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
+#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
+/* [RW 16] destination TCP address 1. The LLH will look for this address in
+ * all incoming packets.
+ */
+#define NIG_REG_LLH0_DEST_TCP_0 0x10220
+/* [RW 16] destination UDP address 1 The LLH will look for this address in
+ * all incoming packets.
+ */
+#define NIG_REG_LLH0_DEST_UDP_0 0x10214
+/* [R 1] FIFO empty in LLH port0 */
+#define NIG_REG_LLH0_FIFO_EMPTY 0x10548
+#define NIG_REG_LLH0_FUNC_EN 0x160fc
+#define NIG_REG_LLH0_FUNC_MEM 0x16180
+#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
+#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
+/* [RW 1] Determine the IP version to look for in
+ * ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4
+ */
+#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
+/* [RW 1] t bit for llh0 */
+#define NIG_REG_LLH0_T_BIT 0x10074
+/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
+#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
+#define NIG_REG_LLH0_XCM_MASK 0x10130
+#define NIG_REG_LLH1_BRB1_DRV_MASK_MF 0x1604c
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
+/* [RW 2] Determine the classification participants. 0: no classification.1:
+ * classification upon VLAN id. 2: classification upon MAC address. 3:
+ * classification upon both VLAN id & MAC addr.
+ */
+#define NIG_REG_LLH1_CLS_TYPE 0x16084
+/* [R 1] FIFO empty in LLH port1 */
+#define NIG_REG_LLH1_FIFO_EMPTY 0x10558
+#define NIG_REG_LLH1_FUNC_EN 0x16104
+#define NIG_REG_LLH1_FUNC_MEM 0x161c0
+#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
+#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
+/* [RW 1] When this bit is set; the LLH will classify the packet before
+ * sending it to the BRB or calculating WoL on it. This bit controls port 1
+ * only. The legacy llh_multi_function_mode bit controls port 0.
+ */
+#define NIG_REG_LLH1_MF_MODE 0x18614
+#define NIG_REG_LLH1_XCM_MASK 0x10134
+/* [RW 1] When this bit is set; the LLH will expect all packets to be with
+ * outer VLAN. This is not applicable to E2.
+ */
+#define NIG_REG_LLH_E1HOV_MODE 0x160d8
+/* [RW 16] Outer VLAN type identifier for multi-function mode. In non
+ * multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
+ */
+#define NIG_REG_LLH_E1HOV_TYPE_1 0x16028
+/* [RW 1] When this bit is set; the LLH will classify the packet before
+ * sending it to the BRB or calculating WoL on it. This bit is applicable to
+ * both ports 0 and 1 for E2. This bit only controls port 0 in E3.
+ */
+#define NIG_REG_LLH_MF_MODE 0x16024
+#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
+#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
+/* [R 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
+#define NIG_REG_NIG_EMAC0_EN 0x1003c
+/* [R 1] Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0
+ * to strip the CRC from the ingress packets.
+ */
+#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
+/* [RW 32] Interrupt mask register #0 read/write */
+#define NIG_REG_NIG_INT_MASK_0 0x103bc
+#define NIG_REG_NIG_INT_MASK_1 0x103cc
+/* [R 32] Interrupt register #0 read */
+#define NIG_REG_NIG_INT_STS_0 0x103b0
+#define NIG_REG_NIG_INT_STS_1 0x103c0
+/* [RC 32] Interrupt register #0 read clear */
+#define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
+#define NIG_REG_NIG_INT_STS_CLR_1 0x103c4
+/* [R 32] Legacy E1 and E1H location for parity error mask register. */
+#define NIG_REG_NIG_PRTY_MASK 0x103dc
+/* [RW 32] Parity mask register #0 read/write */
+#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
+#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
+/* [R 32] Legacy E1 and E1H location for parity error status register. */
+#define NIG_REG_NIG_PRTY_STS 0x103d0
+/* [R 32] Parity register #0 read */
+#define NIG_REG_NIG_PRTY_STS_0 0x183bc
+#define NIG_REG_NIG_PRTY_STS_1 0x183cc
+/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
+#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
+/* [RC 32] Parity register #0 read clear */
+#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
+#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
+/* [R 1] Indication that HBUF descriptor FIFO is empty. */
+#define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header.
+ */
+#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
+/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
+ * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
+ * disabled when this bit is set.
+ */
+#define NIG_REG_P0_HWPFC_ENABLE 0x18078
+#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
+/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Writing a 1 to bit 16
+ * will clear the buffer.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
+ * packets only and require that the packet is IPv4 for the rules to match.
+ * Note that rules 4-7 are for IPv6 packets only and require that the packet
+ * is IPv6 for the rules to match.
+ */
+#define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4
+/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
+#define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac
+/* [RW 1] Input enable for RX MAC interface. */
+#define NIG_REG_P0_MAC_IN_EN 0x185ac
+/* [RW 1] Output enable for TX MAC interface */
+#define NIG_REG_P0_MAC_OUT_EN 0x185b0
+/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
+#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
+/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
+ * future expansion) each priority is to be mapped to. Bits 3:0 specify the
+ * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
+ * priority field is extracted from the outer-most VLAN in receive packet.
+ * Only COS 0 and COS 1 are supported in E2.
+ */
+#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
+/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
+ * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
+ * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
+ * frame format in timesync event detection on RX side. Bit 3 enables
+ * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
+ * detection on TX side. Bit 5 enables V2 frame format in timesync event
+ * detection on TX side. Note that for HW to detect PTP packet and extract
+ * data from the packet, at least one of the version bits of that traffic
+ * direction has to be enabled.
+ */
+#define NIG_REG_P0_PTP_EN 0x18788
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
+ * priority is mapped to COS 0 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
+ * priority is mapped to COS 1 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
+ * priority is mapped to COS 2 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
+ * priority is mapped to COS 3 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
+ * priority is mapped to COS 4 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
+ * priority is mapped to COS 5 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
+/* [R 1] RX FIFO for receiving data from MAC is empty. */
+#define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570
+/* [R 1] TLLH FIFO is empty. */
+#define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308
+/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Bit 17 indicates that
+ * the sequence ID is valid and it is waiting for the TX timestamp value.
+ * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
+ * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules.
+ */
+#define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4
+/* [R 15] Specify which of the credit registers the client is to be mapped
+ * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
+ * clients that are not subject to WFQ credit blocking - their
+ * specifications here are not used.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
+/* [RW 32] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
+/* [RW 4] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
+/* [RW 9] Specify whether the client competes directly in the strict
+ * priority arbiter. The bits are mapped according to client ID (client IDs
+ * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
+ * Default value is set to enable strict priorities for all clients.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
+/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
+ * bits are mapped according to client ID (client IDs are defined in
+ * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
+ * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
+ * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
+ * 0 for not using WFQ credit blocking.
+ */
+#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
+/* [RW 32] Specify the upper bound that credit register 0 is allowed to
+ * reach.
+ */
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
+/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
+ * when it is time to increment.
+ */
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
+/* [RW 12] Specify the number of strict priority arbitration slots between
+ * two round-robin arbitration slots to avoid starvation. A value of 0 means
+ * no strict priority cycles - the strict priority with anti-starvation
+ * arbiter becomes a round-robin arbiter.
+ */
+#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
+/* [R 15] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
+ * are for priority 0 client; bits [14:12] are for priority 4 client. The
+ * clients are assigned the following IDs: 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
+ * for management at priority 0; debug traffic at priorities 1 and 2; COS0
+ * traffic at priority 3; and COS1 traffic at priority 4.
+ */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
+/* [RW 32] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter.
+ */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
+/* [RW 4] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter.
+ */
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
+/* [R 1] TX FIFO for transmitting data to MAC is empty. */
+#define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578
+/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
+ * packets to BRB LB interface to forward the packet to the host. All
+ * packets from MCP are forwarded to the network when this bit is cleared -
+ * regardless of the configured destination in tx_mng_destination register.
+ * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
+ * for BRB LB interface is bypassed and PBF LB traffic is always selected to
+ * send to BRB LB.
+ */
+#define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4
+/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
+ * forwarded to the host.
+ */
+#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8
+/* [R 1] Indication that HBUF descriptor FIFO is empty. */
+#define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header.
+ */
+#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
+/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
+ * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
+ * disabled when this bit is set.
+ */
+#define NIG_REG_P1_HWPFC_ENABLE 0x181d0
+#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
+/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Writing a 1 to bit 16
+ * will clear the buffer.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
+ * packets only and require that the packet is IPv4 for the rules to match.
+ * Note that rules 4-7 are for IPv6 packets only and require that the packet
+ * is IPv6 for the rules to match.
+ */
+#define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc
+/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
+#define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4
+/* [RW 1] Input enable for RX MAC interface. */
+#define NIG_REG_P1_MAC_IN_EN 0x185c0
+/* [RW 1] Output enable for TX MAC interface */
+#define NIG_REG_P1_MAC_OUT_EN 0x185c4
+/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
+#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
+/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
+ * future expansion) each priority is to be mapped to. Bits 3:0 specify the
+ * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
+ * priority field is extracted from the outer-most VLAN in receive packet.
+ * Only COS 0 and COS 1 are supported in E2.
+ */
+#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
+/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
+ * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
+ * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
+ * frame format in timesync event detection on RX side. Bit 3 enables
+ * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
+ * detection on TX side. Bit 5 enables V2 frame format in timesync event
+ * detection on TX side. Note that for HW to detect PTP packet and extract
+ * data from the packet, at least one of the version bits of that traffic
+ * direction has to be enabled.
+ */
+#define NIG_REG_P1_PTP_EN 0x187b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
+ * priority is mapped to COS 0 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
+ * priority is mapped to COS 1 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
+/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
+ * priority is mapped to COS 2 when the corresponding mask bit is 1. More
+ * than one bit may be set; allowing multiple priorities to be mapped to one
+ * COS.
+ */
+#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
+/* [R 1] RX FIFO for receiving data from MAC is empty. */
+#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
+/* [R 1] TLLH FIFO is empty. */
+#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
+/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Bit 17 indicates that
+ * the sequence ID is valid and it is waiting for the TX timestamp value.
+ * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
+ * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules.
+ */
+#define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc
+/* [RW 32] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients. Note also that there are
+ * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
+ * credit registers 0-5 are valid. This register should be configured
+ * appropriately before enabling WFQ.
+ */
+#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
+/* [RW 4] Specify which of the credit registers the client is to be mapped
+ * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
+ * for client 0; bits [35:32] are for client 8. For clients that are not
+ * subject to WFQ credit blocking - their specifications here are not used.
+ * This is a new register (with 2_) added in E3 B0 to accommodate the 9
+ * input clients to ETS arbiter. The reset default is set for management and
+ * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
+ * use credit registers 0-5 respectively (0x543210876). Note that credit
+ * registers can not be shared between clients. Note also that there are
+ * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
+ * credit registers 0-5 are valid. This register should be configured
+ * appropriately before enabling WFQ.
+ */
+#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
+/* [RW 9] Specify whether the client competes directly in the strict
+ * priority arbiter. The bits are mapped according to client ID (client IDs
+ * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
+ * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
+ * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
+ * Default value is set to enable strict priorities for all clients.
+ */
+#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
+/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
+ * bits are mapped according to client ID (client IDs are defined in
+ * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
+ * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
+ * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
+ * 0 for not using WFQ credit blocking.
+ */
+#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
+/* [RW 32] Specify the upper bound that credit register 0 is allowed to
+ * reach.
+ */
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
+/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
+ * when it is time to increment.
+ */
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
+/* [RW 12] Specify the number of strict priority arbitration slots between
+ * two round-robin arbitration slots to avoid starvation. A value of 0 means
+ * no strict priority cycles - the strict priority with anti-starvation
+ * arbiter becomes a round-robin arbiter.
+ */
+#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
+/* [RW 32] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter. Note that this register
+ * is the same as the one for port 0, except that port 1 only has COS 0-2
+ * traffic. There is no traffic for COS 3-5 of port 1.
+ */
+#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
+/* [RW 4] Specify the client number to be assigned to each priority of the
+ * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
+ * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
+ * client; bits [35-32] are for priority 8 client. The clients are assigned
+ * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
+ * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
+ * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
+ * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
+ * accommodate the 9 input clients to ETS arbiter. Note that this register
+ * is the same as the one for port 0, except that port 1 only has COS 0-2
+ * traffic. There is no traffic for COS 3-5 of port 1.
+ */
+#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
+/* [R 1] TX FIFO for transmitting data to MAC is empty. */
+#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
+/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
+ * packets to BRB LB interface to forward the packet to the host. All
+ * packets from MCP are forwarded to the network when this bit is cleared -
+ * regardless of the configured destination in tx_mng_destination register.
+ */
+#define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8
+/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
+ * forwarded to the host.
+ */
+#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
+/* [RW 1] Pause enable for port0. This register may get 1 only when
+ * ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
+ * port
+ */
+#define NIG_REG_PAUSE_ENABLE_0 0x160c0
+#define NIG_REG_PAUSE_ENABLE_1 0x160c4
+/* [RW 1] Value of this register will be transmitted to port swap when
+ * ~nig_registers_strap_override.strap_override =1
+ */
+#define NIG_REG_PORT_SWAP 0x10394
+/* [RW 1] PPP enable for port0. This register may get 1 only when
+ * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
+ * same port
+ */
+#define NIG_REG_PPP_ENABLE_0 0x160b0
+#define NIG_REG_PPP_ENABLE_1 0x160b4
+/* [RW 1] Input enable for RX parser request IF */
+#define NIG_REG_PRS_REQ_IN_EN 0x100b8
+/* [R 5] control to serdes - CL45 DEVAD */
+#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
+/* [R 1] control to serdes; 0 - clause 45; 1 - clause 22 */
+#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
+/* [R 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
+#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
+/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
+#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
+/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
+ * for port 0 COS0
+ */
+#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
+/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
+ * for port 0 COS0
+ */
+#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
+/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
+ * between 1024 and 1522 bytes for port0
+ */
+#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
+/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
+ * between 1523 bytes and above for port0
+ */
+#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
+/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
+ * for port 1 COS0
+ */
+#define NIG_REG_STAT1_BRB_DISCARD 0x10628
+/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
+ * between 1024 and 1522 bytes for port1
+ */
+#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
+/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
+ * between 1523 bytes and above for port1
+ */
+#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
+/* [WB_R 64] Rx statistics : User octets received for LP */
+#define NIG_REG_STAT2_BRB_OCTET 0x107e0
+#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
+/* [RW 1] port swap mux selection. If this register equal to 0 then port
+ * swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
+ * ort swap is equal to ~nig_registers_port_swap.port_swap
+ */
+#define NIG_REG_STRAP_OVERRIDE 0x10398
+/* [WB 64] Addresses for TimeSync related registers in the timesync
+ * generator sub-module.
+ */
+#define NIG_REG_TIMESYNC_GEN_REG 0x18800
+/* [RW 1] output enable for RX_XCM0 IF */
+#define NIG_REG_XCM0_OUT_EN 0x100f0
+/* [RW 1] output enable for RX_XCM1 IF */
+#define NIG_REG_XCM1_OUT_EN 0x100f4
+/* [R 1] control to xgxs - remote PHY in-band MDIO */
+#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
+/* [R 5] control to xgxs - CL45 DEVAD */
+#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
+/* [R 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
+#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
+/* [R 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
+#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
+/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
+#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
+/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
+#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
+/* [R 2] selection for XGXS lane of port 0 in NIG_MUX block */
+#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
+/* [R 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
+#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1 << 0)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1 << 9)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1 << 15)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf << 18)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
+/* [RW 1] Interrupt mask register #0 read/write */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_MASK 0xcc
+/* [R 1] Interrupt register #0 read */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS 0xc0
+/* [RC 1] Interrupt register #0 read clear */
+#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS_CLR 0xc4
+/* [R 31] Removed for E3 B0 -The upper bound of the weight of COS0 in the
+ * ETS command arbiter.
+ */
+#define PBF_REG_COS0_UPPER_BOUND 0x15c05c
+/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
+ * of port 0.
+ */
+#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
+/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
+ * of port 1.
+ */
+#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
+/* [R 31] Removed for E3 B0 - The weight of COS0 in the ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT 0x15c054
+/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
+/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
+/* [R 31] Removed for E3 B0 -The upper bound of the weight of COS1 in the
+ * ETS command arbiter.
+ */
+#define PBF_REG_COS1_UPPER_BOUND 0x15c060
+/* [R 31] Removed for E3 B0 - The weight of COS1 in the ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT 0x15c058
+/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
+/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
+/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
+#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
+/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
+#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
+/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
+#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
+/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
+#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
+/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
+#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
+/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_LB_Q 0x140338
+/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q0 0x14033c
+/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q1 0x140340
+/* [R 11] Current credit for queue 2 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q2 0x140344
+/* [R 11] Current credit for queue 3 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q3 0x140348
+/* [R 11] Current credit for queue 4 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q4 0x14034c
+/* [R 11] Current credit for queue 5 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_CREDIT_Q5 0x140350
+/* [R 1] Removed for E3 B0 - Disable processing further tasks from port 0
+ * (after ending the current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
+/* [R 1] Removed for E3 B0 - Disable processing further tasks from port 1
+ * (after ending the current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bc
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1cc
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+ * current task in process).
+ */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0
+#define PBF_REG_DISABLE_PF 0x1402e8
+#define PBF_REG_DISABLE_VF 0x1402ec
+/* [RW 18] For port 0: For each client that is subject to WFQ (the
+ * corresponding bit is 1); indicates to which of the credit registers this
+ * client is mapped. For clients which are not credit blocked; their mapping
+ * is dont care.
+ */
+#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
+/* [RW 9] For port 1: For each client that is subject to WFQ (the
+ * corresponding bit is 1); indicates to which of the credit registers this
+ * client is mapped. For clients which are not credit blocked; their mapping
+ * is dont care.
+ */
+#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
+/* [RW 6] For port 0: Bit per client to indicate if the client competes in
+ * the strict priority arbiter directly (corresponding bit = 1); or first
+ * goes to the RR arbiter (corresponding bit = 0); and then competes in the
+ * lowest priority in the strict-priority arbiter.
+ */
+#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
+/* [RW 3] For port 1: Bit per client to indicate if the client competes in
+ * the strict priority arbiter directly (corresponding bit = 1); or first
+ * goes to the RR arbiter (corresponding bit = 0); and then competes in the
+ * lowest priority in the strict-priority arbiter.
+ */
+#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
+/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
+ * WFQ credit blocking (corresponding bit = 1).
+ */
+#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
+/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
+ * WFQ credit blocking (corresponding bit = 1).
+ */
+#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
+/* [RW 16] For port 0: The number of strict priority arbitration slots
+ * between 2 RR arbitration slots. A value of 0 means no strict priority
+ * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
+ * arbiter.
+ */
+#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
+/* [RW 16] For port 1: The number of strict priority arbitration slots
+ * between 2 RR arbitration slots. A value of 0 means no strict priority
+ * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
+ * arbiter.
+ */
+#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
+/* [RW 18] For port 0: Indicates which client is connected to each priority
+ * in the strict-priority arbiter. Priority 0 is the highest priority, and
+ * priority 5 is the lowest; to which the RR output is connected to (this is
+ * not configurable).
+ */
+#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
+/* [RW 9] For port 1: Indicates which client is connected to each priority
+ * in the strict-priority arbiter. Priority 0 is the highest priority, and
+ * priority 5 is the lowest; to which the RR output is connected to (this is
+ * not configurable).
+ */
+#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
+/* [R 1] Removed for E3 B0 - Indicates that ETS is performed between the
+ * COSes in the command arbiter. If reset strict priority w/ anti-starvation
+ * will be performed w/o WFQ.
+ */
+#define PBF_REG_ETS_ENABLED 0x15c050
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header.
+ */
+#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
+#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
+/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
+ * priority in the command arbiter.
+ */
+#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
+/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_LB_Q 0x15c248
+/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q0 0x15c230
+/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q1 0x15c234
+/* [RW 11] Initial credit for queue 2 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q2 0x15c238
+/* [RW 11] Initial credit for queue 3 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q3 0x15c23c
+/* [RW 11] Initial credit for queue 4 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q4 0x15c240
+/* [RW 11] Initial credit for queue 5 in the tx port buffers in 16 byte
+ * lines.
+ */
+#define PBF_REG_INIT_CRD_Q5 0x15c244
+/* [R 1] Removed for E3 B0 - Init bit for port 0. When set the initial
+ * credit of port 0 is copied to the credit register. Should be set and then
+ * reset after the configuration of the port has ended.
+ */
+#define PBF_REG_INIT_P0 0x140004
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * the LB queue. Reset upon init.
+ */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * queue 0. Reset upon init.
+ */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * queue 1. Reset upon init.
+ */
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
+/* [RW 1] Enable for mac interface 0. */
+#define PBF_REG_MAC_IF0_ENABLE 0x140030
+/* [RW 6] Bit-map indicating which headers must appear in the packet */
+#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
+/* [R 16] Removed for E3 B0 - The number of strict priority arbitration
+ * slots between 2 RR arbitration slots. A value of 0 means no strict
+ * priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a
+ * RR arbiter.
+ */
+#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
+/* [R 11] Removed for E3 B0 - Port 0 threshold used by arbiter in 16 byte
+ * lines used when pause not suppoterd.
+ */
+#define PBF_REG_P0_ARB_THRSH 0x1400e4
+/* [R 11] Removed for E3 B0 - Current credit for port 0 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P0_CREDIT 0x140200
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P0_INIT_CRD 0x1400d0
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 0. Reset upon init.
+ */
+#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
+/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
+#define PBF_REG_P0_PAUSE_ENABLE 0x140014
+/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
+#define PBF_REG_P0_TASK_CNT 0x140204
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 0. Reset upon init.
+ */
+#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
+#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
+/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P1_CREDIT 0x140208
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P1_INIT_CRD 0x1400d4
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 1. Reset upon init.
+ */
+#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
+/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
+#define PBF_REG_P1_TASK_CNT 0x14020c
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 1. Reset upon init.
+ */
+#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
+#define PBF_REG_P1_TQ_OCCUPANCY 0x140300
+/* [R 11] Removed for E3 B0 - Current credit for port 4 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P4_CREDIT 0x140210
+/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
+ * buffers in 16 byte lines.
+ */
+#define PBF_REG_P4_INIT_CRD 0x1400e0
+/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
+ * port 4. Reset upon init.
+ */
+#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
+/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
+#define PBF_REG_P4_TASK_CNT 0x140214
+/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
+ * freed from the task queue of port 4. Reset upon init.
+ */
+#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
+/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
+#define PBF_REG_P4_TQ_OCCUPANCY 0x140304
+/* [RW 7] Interrupt mask register #0 read/write */
+#define PBF_REG_PBF_INT_MASK 0x1401d4
+/* [R 7] Interrupt register #0 read */
+#define PBF_REG_PBF_INT_STS 0x1401c8
+/* [RC 7] Interrupt register #0 read clear */
+#define PBF_REG_PBF_INT_STS_CLR 0x1401cc
+/* [RW 28] Parity mask register #0 read/write */
+#define PBF_REG_PBF_PRTY_MASK 0x1401e4
+/* [R 28] Parity register #0 read */
+#define PBF_REG_PBF_PRTY_STS 0x1401d8
+/* [RC 28] Parity register #0 read clear */
+#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
+/* [RW 16] The Ethernet type value for L2 tag 0 */
+#define PBF_REG_TAG_ETHERTYPE_0 0x15c090
+/* [RW 4] The length of the info field for L2 tag 0. The length is between
+ * 2B and 14B; in 2B granularity
+ */
+#define PBF_REG_TAG_LEN_0 0x15c09c
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_LB_Q 0x140370
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q0 0x140374
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q1 0x140378
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q2 0x14037c
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q3 0x140380
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q4 0x140384
+/* [R 8] Number of tasks in queue 0 task queue. */
+#define PBF_REG_TASK_CNT_Q5 0x140388
+/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
+ * queue. Reset upon init.
+ */
+#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
+/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
+ * queue 0. Reset upon init.
+ */
+#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
+/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
+ * Reset upon init.
+ */
+#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
+/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
+ * queue.
+ */
+#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
+/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
+#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
+/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
+#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
+/* [RW 16] One of 8 values that should be compared to type in Ethernet
+ * parsing. If there is a match; the field after Ethernet is the first VLAN.
+ * Reset value is 0x8100 which is the standard VLAN type. Note that when
+ * checking second VLAN; type is compared only to 0x8100.
+ */
+#define PBF_REG_VLAN_TYPE_0 0x15c06c
+/* [RW 2] Interrupt mask register #0 read/write */
+#define PB_REG_PB_INT_MASK 0x28
+/* [R 2] Interrupt register #0 read */
+#define PB_REG_PB_INT_STS 0x1c
+/* [RC 2] Interrupt register #0 read clear */
+#define PB_REG_PB_INT_STS_CLR 0x20
+/* [RW 4] Parity mask register #0 read/write */
+#define PB_REG_PB_PRTY_MASK 0x38
+/* [R 4] Parity register #0 read */
+#define PB_REG_PB_PRTY_STS 0x2c
+/* [RC 4] Parity register #0 read clear */
+#define PB_REG_PB_PRTY_STS_CLR 0x30
+#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1 << 0)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1 << 8)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1 << 1)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1 << 6)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1 << 7)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1 << 4)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1 << 3)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1 << 5)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1 << 2)
+/* [R 8] Config space A attention dirty bits. Each bit indicates that the
+ * corresponding PF generates config space A attention. Set by PXP. Reset by
+ * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
+ * from both paths.
+ */
+#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
+/* [R 8] Config space B attention dirty bits. Each bit indicates that the
+ * corresponding PF generates config space B attention. Set by PXP. Reset by
+ * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
+ * from both paths.
+ */
+#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
+/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
+ * that the FLR register of the corresponding PF was set. Set by PXP. Reset
+ * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
+ * from both paths.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
+/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
+ * to a bit in this register in order to clear the corresponding bit in
+ * flr_request_pf_7_0 register. Note: register contains bits from both
+ * paths.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
+/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
+/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
+/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
+/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
+ * indicates that the FLR register of the corresponding VF was set. Set by
+ * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.
+ */
+#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
+/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
+ * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
+ * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
+ * arrived with a correctable error. Bit 3 - Configuration RW arrived with
+ * an uncorrectable error. Bit 4 - Completion with Configuration Request
+ * Retry Status. Bit 5 - Expansion ROM access received with a write request.
+ * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
+ * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
+ * and pcie_rx_last not asserted.
+ */
+#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
+/* [W 7] Writing 1 to each bit in this register clears a corresponding error
+ * details register and enables logging new error details. Bit 0 - clears
+ * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears
+ * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS
+ * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32
+ * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -
+ * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears
+ * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6
+ * - clears TCPL_IN_TWO_RCBS_DETAILS.
+ */
+#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c
+/* [RW 11] Interrupt mask register #0 read/write */
+#define PGLUE_B_REG_PGLUE_B_INT_MASK 0x92a4
+/* [R 11] Interrupt register #0 read */
+#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
+/* [RC 11] Interrupt register #0 read clear */
+#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
+/* [RW 2] Parity mask register #0 read/write */
+#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
+/* [R 2] Parity register #0 read */
+#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
+/* [RC 2] Parity register #0 read clear */
+#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
+/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
+ * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
+ * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
+ * completer abort. 3 - Illegal value for this field. [12] valid - indicates
+ * if there was a completion error since the last time this register was
+ * cleared.
+ */
+#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
+/* [R 18] Details of first ATS Translation Completion request received with
+ * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
+ * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
+ * unsupported request. 2 - completer abort. 3 - Illegal value for this
+ * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
+ * completion error since the last time this register was cleared.
+ */
+#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
+/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
+ * a bit in this register in order to clear the corresponding bit in
+ * shadow_bme_pf_7_0 register. MCP should never use this unless a
+ * work-around is needed. Note: register contains bits from both paths.
+ */
+#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
+/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
+ * VF enable register of the corresponding PF is written to 0 and was
+ * previously 1. Set by PXP. Reset by MCP writing 1 to
+ * sr_iov_disabled_request_clr. Note: register contains bits from both
+ * paths.
+ */
+#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
+/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
+ * completion did not return yet. 1 - tag is unused. Same functionality as
+ * pxp2_registers_pgl_exp_rom_data2 for tags 0-31.
+ */
+#define PGLUE_B_REG_TAGS_63_32 0x9244
+/* [R 32] Address [31:0] of first read request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
+/* [R 32] Address [63:32] of first read request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
+/* [R 31] Details of first read request not submitted due to error. [4:0]
+ * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
+ * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
+ * VFID.
+ */
+#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
+/* [R 26] Details of first read request not submitted due to error. [15:0]
+ * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
+ * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
+ * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
+ * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
+ * indicates if there was a request not submitted due to error since the
+ * last time this register was cleared.
+ */
+#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
+/* [R 32] Address [31:0] of first write request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
+/* [R 32] Address [63:32] of first write request not submitted due to error */
+#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
+/* [R 31] Details of first write request not submitted due to error. [4:0]
+ * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
+ * - VFID.
+ */
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
+/* [R 26] Details of first write request not submitted due to error. [15:0]
+ * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
+ * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
+ * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
+ * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
+ * indicates if there was a request not submitted due to error since the
+ * last time this register was cleared.
+ */
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
+/* [R 26] Details of first target VF request accessing VF GRC space that
+ * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
+ * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
+ * request accessing VF GRC space that failed permission check since the
+ * last time this register was cleared. Permission checks are: function
+ * permission; R/W permission; address range permission.
+ */
+#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
+/* [R 31] Details of first target VF request with length violation (too many
+ * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
+ * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
+ * valid - indicates if there was a request with length violation since the
+ * last time this register was cleared. Length violations: length of more
+ * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
+ * length is more than 1 DW.
+ */
+#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
+/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
+ * that there was a completion with uncorrectable error for the
+ * corresponding PF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_pf_7_0_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
+/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
+ * to a bit in this register in order to clear the corresponding bit in
+ * flr_request_pf_7_0 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
+/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_127_96_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
+/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
+ * writes 1 to a bit in this register in order to clear the corresponding
+ * bit in was_error_vf_127_96 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
+/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_31_0_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
+/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_31_0 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
+/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_63_32_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
+/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_63_32 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
+/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
+ * indicates that there was a completion with uncorrectable error for the
+ * corresponding VF. Set by PXP. Reset by MCP writing 1 to
+ * was_error_vf_95_64_clr.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
+/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
+ * 1 to a bit in this register in order to clear the corresponding bit in
+ * was_error_vf_95_64 register.
+ */
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
+#define PRS_REG_A_PRSU_20 0x40134
+/* [R 8] debug only: CFC load request current credit. Transaction based. */
+#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
+/* [R 8] debug only: CFC search request current credit. Transaction based. */
+#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
+/* [RW 6] The initial credit for the search message to the CFC interface.
+ * Credit is transaction based.
+ */
+#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
+/* [RW 24] CID for port 0 if no match */
+#define PRS_REG_CID_PORT_0 0x400fc
+/* [RW 1] Indicates if in outer vlan mode. 0=non-outer-vlan mode; 1 = outer
+ * vlan mode.
+ */
+#define PRS_REG_E1HOV_MODE 0x401c8
+/* [R 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header.
+ */
+#define PRS_REG_HDRS_AFTER_BASIC 0x40238
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
+ * Ethernet header for port 0 packets.
+ */
+#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
+#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
+/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
+#define PRS_REG_HDRS_AFTER_TAG_0 0x40248
+/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
+ * port 0 packets
+ */
+#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
+#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
+/* [R 6] Bit-map indicating which headers must appear in the packet */
+#define PRS_REG_MUST_HAVE_HDRS 0x40254
+/* [RW 6] Bit-map indicating which headers must appear in the packet for
+ * port 0 packets
+ */
+#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
+#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
+#define PRS_REG_NIC_MODE 0x40138
+/* [ST 24] The number of input packets */
+#define PRS_REG_NUM_OF_PACKETS 0x40124
+/* [R 2] debug only: Number of pending requests for CAC on port 0. */
+#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
+/* [R 2] debug only: Number of pending requests for header parsing. */
+#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
+/* [RW 1] Interrupt mask register #0 read/write */
+#define PRS_REG_PRS_INT_MASK 0x40194
+/* [R 1] Interrupt register #0 read */
+#define PRS_REG_PRS_INT_STS 0x40188
+/* [RC 1] Interrupt register #0 read clear */
+#define PRS_REG_PRS_INT_STS_CLR 0x4018c
+/* [RW 8] Parity mask register #0 read/write */
+#define PRS_REG_PRS_PRTY_MASK 0x401a4
+/* [R 8] Parity register #0 read */
+#define PRS_REG_PRS_PRTY_STS 0x40198
+/* [RC 8] Parity register #0 read clear */
+#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
+/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
+ * serail number was released by SDM but cannot be used because a previous
+ * serial number was not released.
+ */
+#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
+/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
+ * serail number was released by SDM but cannot be used because a previous
+ * serial number was not released.
+ */
+#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
+/* [R 4] debug only: SRC current credit. Transaction based. */
+#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
+/* [RW 16] The Ethernet type value for L2 tag 0 */
+#define PRS_REG_TAG_ETHERTYPE_0 0x401d4
+/* [RW 4] The length of the info field for L2 tag 0. The length is between
+ * 2B and 14B; in 2B granularity
+ */
+#define PRS_REG_TAG_LEN_0 0x4022c
+/* [R 8] debug only: TCM current credit. Cycle based. */
+#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
+/* [R 8] debug only: TSDM current credit. Transaction based. */
+#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
+/* [RW 16] One of 8 values that should be compared to type in Ethernet
+ * parsing. If there is a match; the field after Ethernet is the first VLAN.
+ * Reset value is 0x8100 which is the standard VLAN type. Note that when
+ * checking second VLAN; type is compared only to 0x8100.
+ */
+#define PRS_REG_VLAN_TYPE_0 0x401a8
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1 << 19)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1 << 20)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1 << 22)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1 << 23)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1 << 24)
+#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1 << 7)
+#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1 << 7)
+/* [R 7] Debug only: Number of used entries in the data FIFO */
+#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
+/* [R 7] Debug only: Number of used entries in the header FIFO */
+#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
+#define PXP2_REG_PGL_ADDR_88_F0 0x120534
+/* [R 32] GRC address for configuration access to PCIE config address 0x88.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register
+ */
+#define PXP2_REG_PGL_ADDR_88_F1 0x120544
+#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
+/* [R 32] GRC address for configuration access to PCIE config address 0x8c.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register
+ */
+#define PXP2_REG_PGL_ADDR_8C_F1 0x120548
+#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
+/* [R 32] GRC address for configuration access to PCIE config address 0x90.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register
+ */
+#define PXP2_REG_PGL_ADDR_90_F1 0x12054c
+#define PXP2_REG_PGL_ADDR_94_F0 0x120540
+/* [R 32] GRC address for configuration access to PCIE config address 0x94.
+ * any write to this PCIE address will cause a GRC write access to the
+ * address that's in t this register
+ */
+#define PXP2_REG_PGL_ADDR_94_F1 0x120550
+/* [RW 32] third dword data of expansion rom request. this register is
+ * special. reading from it provides a vector outstanding read requests. if
+ * a bit is zero it means that a read request on the corresponding tag did
+ * not finish yet (not all completions have arrived for it)
+ */
+#define PXP2_REG_PGL_EXP_ROM2 0x120808
+/* [RW 16] this field allows one function to pretend being another function
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated. Bits [15] - force. Bits [14] - path
+ * ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits
+ * [2:0] - PFID.
+ */
+#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
+/* [RW 16] this field allows one function to pretend being another function
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated. Bits [15] - force. Bits [14] - path
+ * ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits
+ * [2:0] - PFID.
+ */
+#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
+/* [R 1] this bit indicates that a read request was blocked because of
+ * bus_master_en was deasserted
+ */
+#define PXP2_REG_PGL_READ_BLOCKED 0x120568
+#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
+/* [R 21] debug only */
+#define PXP2_REG_PGL_TXW_CDTS 0x12052c
+/* [R 1] this bit indicates that a write request was blocked because of
+ * bus_master_en was deasserted
+ */
+#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
+#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
+#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
+#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
+#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
+#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
+#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
+#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
+#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
+#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
+#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
+#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
+#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
+#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
+#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
+#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
+#define PXP2_REG_PSWRQ_BW_L28 0x120318
+#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
+#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
+#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
+#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
+#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
+#define PXP2_REG_PSWRQ_BW_RD 0x120324
+#define PXP2_REG_PSWRQ_BW_UB1 0x120238
+#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
+#define PXP2_REG_PSWRQ_BW_UB11 0x120260
+#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
+#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
+#define PXP2_REG_PSWRQ_BW_UB3 0x120240
+#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
+#define PXP2_REG_PSWRQ_BW_UB7 0x120250
+#define PXP2_REG_PSWRQ_BW_UB8 0x120254
+#define PXP2_REG_PSWRQ_BW_UB9 0x120258
+#define PXP2_REG_PSWRQ_BW_WR 0x120328
+#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
+#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
+#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
+#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
+#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define PXP2_REG_PXP2_INT_MASK_0 0x120578
+#define PXP2_REG_PXP2_INT_MASK_1 0x120614
+/* [R 32] Interrupt register #0 read */
+#define PXP2_REG_PXP2_INT_STS_0 0x12056c
+#define PXP2_REG_PXP2_INT_STS_1 0x120608
+/* [RC 32] Interrupt register #0 read clear */
+#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
+#define PXP2_REG_PXP2_INT_STS_CLR_1 0x12060c
+/* [RW 32] Parity mask register #0 read/write */
+#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
+#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
+/* [R 32] Parity register #0 read */
+#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
+#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
+/* [RC 32] Parity register #0 read clear */
+#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
+#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
+/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
+ * indication about backpressure)
+ */
+#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
+/* [R 8] Debug only: The blocks counter - number of unused block ids */
+#define PXP2_REG_RD_BLK_CNT 0x120418
+/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
+ * Must be bigger than 6. Normally should not be changed.
+ */
+#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
+/* [RW 2] CDU byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
+/* [R 29] Details of first request with error on receive side: [15:0] - Echo
+ * ID. [28:16] - sub-request length plus start_offset_2_0 minus 1.
+ */
+#define PXP2_REG_RD_CPL_ERR_DETAILS 0x120778
+/* [R 10] Details of first request with error on receive side: [4:0] - VQ
+ * ID. [8:5] - client ID. [9] - valid - indicates if there was a completion
+ * error since the last time this register was read.
+ */
+#define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077c
+/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
+#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
+/* [R 1] PSWRD internal memories initialization is done */
+#define PXP2_REG_RD_INIT_DONE 0x120370
+/* [R 1] Debug only: Indication if delivery ports are idle */
+#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
+#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
+/* [RW 2] QM byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
+/* [RW 2] SRC byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
+/* [R 7] Debug only: The SR counter - number of unused sub request ids */
+#define PXP2_REG_RD_SR_CNT 0x120414
+/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
+ * be bigger than 1. Normally should not be changed.
+ */
+#define PXP2_REG_RD_SR_NUM_CFG 0x120408
+/* [RW 1] Signals the PSWRD block to start initializing internal memories */
+#define PXP2_REG_RD_START_INIT 0x12036c
+/* [RW 2] TM byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
+/* [RW 10] Bandwidth addition to VQ0 write requests */
+#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
+/* [RW 10] Bandwidth addition to VQ12 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
+/* [RW 10] Bandwidth addition to VQ13 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
+/* [RW 10] Bandwidth addition to VQ14 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
+/* [RW 10] Bandwidth addition to VQ15 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
+/* [RW 10] Bandwidth addition to VQ16 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
+/* [RW 10] Bandwidth addition to VQ17 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
+/* [RW 10] Bandwidth addition to VQ18 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
+/* [RW 10] Bandwidth addition to VQ19 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
+/* [RW 10] Bandwidth addition to VQ20 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
+/* [RW 10] Bandwidth addition to VQ22 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
+/* [RW 10] Bandwidth addition to VQ23 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
+/* [RW 10] Bandwidth addition to VQ24 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
+/* [RW 10] Bandwidth addition to VQ25 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
+/* [RW 10] Bandwidth addition to VQ26 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
+/* [RW 10] Bandwidth addition to VQ27 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
+/* [RW 10] Bandwidth addition to VQ4 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
+/* [RW 10] Bandwidth addition to VQ5 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
+/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
+#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
+/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
+#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
+/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
+#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
+/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
+#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
+/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
+#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
+/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
+#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
+/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
+#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
+/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
+#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
+/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
+#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
+/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
+#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
+/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
+#define PXP2_REG_RQ_BW_RD_L22 0x120300
+/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
+#define PXP2_REG_RQ_BW_RD_L23 0x120304
+/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
+#define PXP2_REG_RQ_BW_RD_L24 0x120308
+/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
+#define PXP2_REG_RQ_BW_RD_L25 0x12030c
+/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
+#define PXP2_REG_RQ_BW_RD_L26 0x120310
+/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
+#define PXP2_REG_RQ_BW_RD_L27 0x120314
+/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
+#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
+/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
+#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
+/* [RW 7] Bandwidth upper bound for VQ0 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
+/* [RW 7] Bandwidth upper bound for VQ12 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
+/* [RW 7] Bandwidth upper bound for VQ13 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
+/* [RW 7] Bandwidth upper bound for VQ14 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
+/* [RW 7] Bandwidth upper bound for VQ15 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
+/* [RW 7] Bandwidth upper bound for VQ16 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
+/* [RW 7] Bandwidth upper bound for VQ17 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
+/* [RW 7] Bandwidth upper bound for VQ18 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
+/* [RW 7] Bandwidth upper bound for VQ19 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
+/* [RW 7] Bandwidth upper bound for VQ20 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
+/* [RW 7] Bandwidth upper bound for VQ22 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
+/* [RW 7] Bandwidth upper bound for VQ23 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
+/* [RW 7] Bandwidth upper bound for VQ24 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
+/* [RW 7] Bandwidth upper bound for VQ25 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
+/* [RW 7] Bandwidth upper bound for VQ26 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
+/* [RW 7] Bandwidth upper bound for VQ27 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
+/* [RW 7] Bandwidth upper bound for VQ4 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
+/* [RW 7] Bandwidth upper bound for VQ5 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
+/* [RW 10] Bandwidth addition to VQ29 write requests */
+#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
+/* [RW 10] Bandwidth addition to VQ30 write requests */
+#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
+/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
+#define PXP2_REG_RQ_BW_WR_L29 0x12031c
+/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
+#define PXP2_REG_RQ_BW_WR_L30 0x120320
+/* [RW 7] Bandwidth upper bound for VQ29 */
+#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
+/* [RW 7] Bandwidth upper bound for VQ30 */
+#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
+/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
+#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
+/* [RW 2] Endian mode for cdu */
+#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
+#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
+#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
+/* [RW 4] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M
+ */
+#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
+/* [R 1] 1' indicates that the requester has finished its internal
+ * configuration
+ */
+#define PXP2_REG_RQ_CFG_DONE 0x1201b4
+/* [RW 2] Endian mode for debug */
+#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
+/* [RW 1] When '1'; requests will enter input buffers but wont get out
+ * towards the glue
+ */
+#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
+/* [RW 4] Determines alignment of write SRs when a request is split into
+ * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
+ * aligned. 4 - 512B aligned.
+ */
+#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
+/* [RW 4] Determines alignment of read SRs when a request is split into
+ * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
+ * aligned. 4 - 512B aligned.
+ */
+#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
+/* [RW 1] when set the new alignment method (E2) will be applied; when reset
+ * the original alignment method (E1 E1H) will be applied
+ */
+#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
+/* [R 32] Status signals in pswrq_garb module */
+#define PXP2_REG_RQ_GARB 0x120748
+/* [RW 2] Endian mode for hc */
+#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
+/* [WB 53] Onchip address table */
+#define PXP2_REG_RQ_ONCHIP_AT 0x122000
+/* [WB 53] Onchip address table - B0 */
+#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
+/* [RW 13] Pending read limiter threshold; in Dwords */
+#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
+/* [RW 2] Endian mode for qm */
+#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
+#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
+#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
+/* [RW 4] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M
+ */
+#define PXP2_REG_RQ_QM_P_SIZE 0x120050
+/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
+#define PXP2_REG_RQ_RBC_DONE 0x1201b0
+/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
+ * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K
+ */
+#define PXP2_REG_RQ_RD_MBS0 0x120160
+/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
+ * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K
+ */
+#define PXP2_REG_RQ_RD_MBS1 0x120168
+/* [RW 2] Endian mode for src */
+#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
+#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
+#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
+/* [RW 4] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M
+ */
+#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
+/* [RW 2] Endian mode for tm */
+#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
+#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
+#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
+/* [RW 4] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
+ * -128k; -256k; -512k; -1M; -2M; 0-4M
+ */
+#define PXP2_REG_RQ_TM_P_SIZE 0x120034
+/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
+#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
+/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
+#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
+/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
+#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
+/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
+#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
+/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
+#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
+/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
+#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
+/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
+#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
+/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
+#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
+/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
+#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
+/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
+#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
+/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
+#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
+/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
+#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
+/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
+#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
+/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
+#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
+/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
+#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
+/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
+#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
+/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
+#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
+/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
+#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
+/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
+#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
+/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
+#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
+/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
+#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
+/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
+#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
+/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
+#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
+/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
+#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
+/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
+#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
+/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
+#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
+/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
+#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
+/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
+#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
+/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
+#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
+/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
+#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
+/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
+#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
+/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
+#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
+/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
+#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
+/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
+#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
+/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
+ * 001:256B; 010: 512B;
+ */
+#define PXP2_REG_RQ_WR_MBS0 0x12015c
+/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
+ * 001:256B; 010: 512B;
+ */
+#define PXP2_REG_RQ_WR_MBS1 0x120164
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_CDU_MPS 0x1205f0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_CSDM_MPS 0x1205d0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_DBG_MPS 0x1205e8
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_DMAE_MPS 0x1205ec
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_HC_MPS 0x1205c8
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_QM_MPS 0x1205dc
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_SRC_MPS 0x1205e4
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_TM_MPS 0x1205e0
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_TSDM_MPS 0x1205d4
+/* [RW 9] a. When pxp2.wr_th_mode_usdmdp = 0 (E1.5-65 mode) should be
+ * initialized to (MPS/32); b. When pxp2.wr_th_mode_usdmdp = 1 (E1.5-90;
+ * enhanced mode) and pxp2.wr_usdmdp_outst_req is different than default (3)
+ * should be initialized to (pxp2.wr_usdmdp_outst_req x MPS/32); when
+ * pxp2.wr_usdmdp_outst_req is 3 the reset value is the correct
+ * configuration
+ */
+#define PXP2_REG_WR_USDMDP_TH 0x120348
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_USDM_MPS 0x1205cc
+/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
+ * buffer reaches this number has_payload will be asserted. 1024B is not a
+ * real MPS; it is a way of indicating that the client needs to wait for EOP
+ * before asserting has_payload. Register should be initialized according to
+ * has_payload value.
+ */
+#define PXP2_REG_WR_XSDM_MPS 0x1205d8
+/* [R 1] debug only: Indication if PSWHST arbiter is idle */
+#define PXP_REG_HST_ARB_IS_IDLE 0x103004
+/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
+ * this client is waiting for the arbiter.
+ */
+#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
+/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
+ * block. Should be used for close the gates.
+ */
+#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
+/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
+ * should update according to 'hst_discard_doorbells' register when the state
+ * machine is idle
+ */
+#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
+/* [RW 1] When 1; new internal writes arriving to the block are discarded.
+ * Should be used for close the gates.
+ */
+#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
+/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
+ * means this PSWHST is discarding inputs from this client. Each bit should
+ * update according to 'hst_discard_internal_writes' register when the state
+ * machine is idle.
+ */
+#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
+/* [R 1] 1 - An incorrect access is logged. The valid bit is reset when the
+ * relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
+ */
+#define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030cc
+/* [R 1] 1- permission violation data is logged. The valid bit is reset when
+ * the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
+ */
+#define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0
+/* [R 15] The FID of the first access to a disabled VF; the format is
+ * [14:12] - pfid; [11:6] - vfid; [5] - vf_valid; [4:1] - client (0 USDM; 1
+ * CSDM; 2 XSDM; 3 TSDM; 4 HC; 5 GRC; 6 DQ; 7 RESERVED SPACE; 8 ATC); [0] -
+ * w_nr(0-read req; 1- write req). The data is written only when the valid
+ * bit is reset. and it is stays stable until it is reset by the read from
+ * interrupt_clr register
+ */
+#define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b8
+/* [R 1] 1 - An error request is logged and wasn't handled yet. The valid
+ * bit is reset when the relevant interrupt register is read
+ * (PXP_REG_INT_STS_CLR_1)
+ */
+#define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bc
+/* [RW 7] Indirect access to the permission table. The fields are : {Valid;
+ * VFID[5:0]}
+ */
+#define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400
+/* [RW 32] Interrupt mask register #0 read/write */
+#define PXP_REG_PXP_INT_MASK_0 0x103074
+#define PXP_REG_PXP_INT_MASK_1 0x103084
+/* [R 32] Interrupt register #0 read */
+#define PXP_REG_PXP_INT_STS_0 0x103068
+#define PXP_REG_PXP_INT_STS_1 0x103078
+/* [RC 32] Interrupt register #0 read clear */
+#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
+#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
+/* [RW 27] Parity mask register #0 read/write */
+#define PXP_REG_PXP_PRTY_MASK 0x103094
+/* [R 27] Parity register #0 read */
+#define PXP_REG_PXP_PRTY_STS 0x103088
+/* [RC 27] Parity register #0 read clear */
+#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
+/* [RW 32] The base logical address (in bytes) of each physical queue. The
+ * index I represents the physical queue number. The 12 lsbs are ignore and
+ * considered zero so practically there are only 20 bits in this register;
+ * queues 63-0
+ */
+#define QM_REG_BASEADDR 0x168900
+/* [R 32] NOT USED */
+#define QM_REG_BASEADDR_EXT_A 0x16e100
+/* [R 18] The credit value for byte credit 0. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD0 0x16e6fc
+/* [R 18] The credit value for byte credit 1. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD1 0x16e700
+/* [R 18] The credit value for byte credit 2. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD2 0x16e704
+/* [R 18] The credit value for byte credit 3. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD3 0x16e7ac
+/* [R 18] The credit value for byte credit 4. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD4 0x16e7b0
+/* [R 18] The credit value for byte credit 5. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD5 0x16e7b4
+/* [R 18] The credit value for byte credit 6. The value is 2s complement
+ * value (i.e. msb is used for the sign).
+ */
+#define QM_REG_BYTECRD6 0x16e7b8
+/* [R 32] NOT USED - removed for E3 B0 */
+#define QM_REG_BYTECRDCMDQ_0 0x16e6e8
+/* [RC 32] byte credit update error register; b2-b0: byte credit id (pbf
+ * error); b3 - reserved (zero filled); b6-b4: byte credit id (storm
+ * increment error); b7 - reserved (zero filled); b10-b8: byte credit id
+ * (storm decrement error); b11 - reserved (zero filled); b12: pbf error
+ * valid; b13: storm increment error valid; b14: storm decrement error
+ * valid; b15: reserved; b22-b16: byte credit warning (warning = decremented
+ * below zero). mask bit per voq counter; b31-b23: reserved; NOTE: VOQ id-s
+ * represent HW
+ */
+#define QM_REG_BYTECRDERRREG 0x16e708
+/* [RW 17] The initial byte credit value for all counters */
+#define QM_REG_BYTECRDINITVAL 0x168238
+/* [RW 20] The number of connections divided by 16 which dictates the size
+ * of each queue which belongs to even function number.
+ */
+#define QM_REG_CONNNUM_0 0x168020
+/* [R 6] Keep the fill level of the fifo from write client 4 */
+#define QM_REG_CQM_WRC_FIFOLVL 0x168018
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ0
+ */
+#define QM_REG_FWVOQ0TOHWVOQ 0x16e7bc
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ1
+ */
+#define QM_REG_FWVOQ1TOHWVOQ 0x16e7c0
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ2
+ */
+#define QM_REG_FWVOQ2TOHWVOQ 0x16e7c4
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ3
+ */
+#define QM_REG_FWVOQ3TOHWVOQ 0x16e7c8
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ4
+ */
+#define QM_REG_FWVOQ4TOHWVOQ 0x16e7cc
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ5
+ */
+#define QM_REG_FWVOQ5TOHWVOQ 0x16e7d0
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ6
+ */
+#define QM_REG_FWVOQ6TOHWVOQ 0x16e7d4
+/* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of
+ * FW (virtual) VOQ7
+ */
+#define QM_REG_FWVOQ7TOHWVOQ 0x16e7d8
+/* [RC 1] A flag to indicate that overflow error occurred in one of the
+ * queues.
+ */
+#define QM_REG_OVFERROR 0x16805c
+/* [RC 6] the Q were the qverflow occurs */
+#define QM_REG_OVFQNUM 0x168058
+/* [R 16] Pause state for physical queues 15-0 */
+#define QM_REG_PAUSESTATE0 0x168410
+/* [R 16] Pause state for physical queues 31-16 */
+#define QM_REG_PAUSESTATE1 0x168414
+/* [R 16] Pause state for physical queues 47-32 */
+#define QM_REG_PAUSESTATE2 0x16e684
+/* [R 16] Pause state for physical queues 63-48 */
+#define QM_REG_PAUSESTATE3 0x16e688
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE4 0x16e68c
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE5 0x16e690
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE6 0x16e694
+/* [R 16] NOT USED */
+#define QM_REG_PAUSESTATE7 0x16e698
+#define QM_REG_PF_EN 0x16e70c
+/* [R 24] The number of tasks stored in the QM for the PF. only even
+ * functions are valid in E2 (odd I registers will be hard wired to 0)
+ */
+#define QM_REG_PF_USG_CNT_0 0x16e040
+/* [R 16] NOT USED */
+#define QM_REG_PORT0BYTECRD 0x168300
+/* [R 16] NOT USED */
+#define QM_REG_PORT1BYTECRD 0x168304
+/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
+ * ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
+ * bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;
+ */
+#define QM_REG_PTRTBL 0x168a00
+/* [R 54] NOT USED */
+#define QM_REG_PTRTBL_EXT_A 0x16e200
+/* [RW 14] Interrupt mask register #0 read/write */
+#define QM_REG_QM_INT_MASK 0x168444
+/* [R 14] Interrupt register #0 read */
+#define QM_REG_QM_INT_STS 0x168438
+/* [RC 14] Interrupt register #0 read clear */
+#define QM_REG_QM_INT_STS_CLR 0x16843c
+/* [RW 12] Parity mask register #0 read/write */
+#define QM_REG_QM_PRTY_MASK 0x168454
+/* [R 12] Parity register #0 read */
+#define QM_REG_QM_PRTY_STS 0x168448
+/* [RC 12] Parity register #0 read clear */
+#define QM_REG_QM_PRTY_STS_CLR 0x16844c
+/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
+#define QM_REG_QSTATUS_HIGH 0x16802c
+/* [R 32] NOT USED */
+#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
+/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
+#define QM_REG_QSTATUS_LOW 0x168028
+/* [R 32] NOT USED */
+#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
+/* [R 24] The number of tasks queued for each queue; queues 63-0 */
+#define QM_REG_QTASKCTR_0 0x168308
+/* [R 24] NOT USED */
+#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
+/* [RW 4] Queue tied to VOQ */
+#define QM_REG_QVOQIDX_0 0x1680f4
+/* [RW 1] Initialization bit command */
+#define QM_REG_SOFT_RESET 0x168428
+/* [R 6] Keep the fill level of the fifo from write client 3 */
+#define QM_REG_TQM_WRC_FIFOLVL 0x168010
+/* [R 6] Keep the fill level of the fifo from write client 2 */
+#define QM_REG_UQM_WRC_FIFOLVL 0x168008
+/* [RC 32] VOQ credit update error register; b3-b0: voq id (pbf error);
+ * b7-b4: voq id (storm increment error); b11-b8: voq id (storm decrement
+ * error); b12: pbf error valid; b13: storm increment error valid; b14:
+ * storm decrement error valid; b15: reserved; b27-b16: voq warning
+ * (warning = decremented below zero). mask bit per voq counter; b31-b28:
+ * reserved; NOTE: VOQ id-s represent HW VOQ id
+ */
+#define QM_REG_VOQCRDERRREG 0x168408
+/* [R 17] The credit value for each VOQ. The value is 2s complement value
+ * (i.e. msb is used for the sign).
+ */
+#define QM_REG_VOQCREDIT_0 0x1682d0
+#define QM_REG_VOQCREDIT_1 0x1682d4
+#define QM_REG_VOQCREDIT_2 0x1682d8
+#define QM_REG_VOQCREDIT_3 0x1682dc
+#define QM_REG_VOQCREDIT_4 0x1682e0
+#define QM_REG_VOQCREDIT_5 0x1682e4
+#define QM_REG_VOQCREDIT_6 0x1682e8
+/* [RW 16] The init and maximum credit for each VoQ */
+#define QM_REG_VOQINITCREDIT_0 0x168060
+#define QM_REG_VOQINITCREDIT_1 0x168064
+#define QM_REG_VOQINITCREDIT_2 0x168068
+#define QM_REG_VOQINITCREDIT_3 0x16806c
+#define QM_REG_VOQINITCREDIT_4 0x168070
+#define QM_REG_VOQINITCREDIT_5 0x168074
+#define QM_REG_VOQINITCREDIT_6 0x168078
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_0_LSB 0x168240
+/* [R 6] Keep the fill level of the fifo from write client 1 */
+#define QM_REG_XQM_WRC_FIFOLVL 0x168000
+/* [W 1] reset to parity interrupt */
+#define SEM_FAST_REG_PARITY_RST 0x18840
+/* [RW 1] Interrupt mask register #0 read/write */
+#define SEM_FAST_REG_SEM_FAST_INT_MASK 0x1fff0
+/* [R 1] Interrupt register #0 read */
+#define SEM_FAST_REG_SEM_FAST_INT_STS 0x1fffc
+/* [RC 1] Interrupt register #0 read clear */
+#define SEM_FAST_REG_SEM_FAST_INT_STS_CLR 0x1fff8
+/* [RW 1] Parity mask register #0 read/write */
+#define SEM_FAST_REG_SEM_FAST_PRTY_MASK 0x1ffe0
+/* [R 1] Parity register #0 read */
+#define SEM_FAST_REG_SEM_FAST_PRTY_STS 0x1ffec
+/* [RC 1] Parity register #0 read clear */
+#define SEM_FAST_REG_SEM_FAST_PRTY_STS_CLR 0x1ffe8
+#define SRC_REG_COUNTFREE0 0x40500
+#define SRC_REG_FIRSTFREE0 0x40510
+#define SRC_REG_KEYRSS0_0 0x40408
+#define SRC_REG_KEYRSS0_7 0x40424
+#define SRC_REG_KEYSEARCH_0 0x40458
+#define SRC_REG_KEYSEARCH_1 0x4045c
+#define SRC_REG_KEYSEARCH_2 0x40460
+#define SRC_REG_KEYSEARCH_3 0x40464
+#define SRC_REG_KEYSEARCH_4 0x40468
+#define SRC_REG_KEYSEARCH_5 0x4046c
+#define SRC_REG_KEYSEARCH_6 0x40470
+#define SRC_REG_KEYSEARCH_7 0x40474
+#define SRC_REG_KEYSEARCH_8 0x40478
+#define SRC_REG_KEYSEARCH_9 0x4047c
+#define SRC_REG_LASTFREE0 0x40530
+#define SRC_REG_NUMBER_HASH_BITS0 0x40400
+/* [RW 1] Reset internal state machines. */
+#define SRC_REG_SOFT_RST 0x4049c
+/* [RW 3] Interrupt mask register #0 read/write */
+#define SRC_REG_SRC_INT_MASK 0x404b8
+/* [R 3] Interrupt register #0 read */
+#define SRC_REG_SRC_INT_STS 0x404ac
+/* [RC 3] Interrupt register #0 read clear */
+#define SRC_REG_SRC_INT_STS_CLR 0x404b0
+/* [RW 3] Parity mask register #0 read/write */
+#define SRC_REG_SRC_PRTY_MASK 0x404c8
+/* [R 3] Parity register #0 read */
+#define SRC_REG_SRC_PRTY_STS 0x404bc
+/* [RC 3] Parity register #0 read clear */
+#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
+/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
+#define TCM_REG_CAM_OCCUP 0x5017c
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define TCM_REG_CFC_INIT_CRD 0x50204
+/* [RC 1] Message length mismatch (relative to last indication) at the In#9
+ * interface.
+ */
+#define TCM_REG_CSEM_LENGTH_MIS 0x50174
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define TCM_REG_FIC0_INIT_CRD 0x5020c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define TCM_REG_FIC1_INIT_CRD 0x50210
+/* [RC 1] Message length mismatch (relative to last indication) at the In#7
+ * interface.
+ */
+#define TCM_REG_PBF_LENGTH_MIS 0x5016c
+/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define TCM_REG_PRS_IFEN 0x50020
+/* [RC 1] Message length mismatch (relative to last indication) at the In#6
+ * interface.
+ */
+#define TCM_REG_PRS_LENGTH_MIS 0x50168
+/* [RC 1] Message length mismatch (relative to last indication) at the STORM
+ * interface.
+ */
+#define TCM_REG_STORM_LENGTH_MIS 0x50160
+/* [RW 11] Interrupt mask register #0 read/write */
+#define TCM_REG_TCM_INT_MASK 0x501dc
+/* [R 11] Interrupt register #0 read */
+#define TCM_REG_TCM_INT_STS 0x501d0
+/* [RC 11] Interrupt register #0 read clear */
+#define TCM_REG_TCM_INT_STS_CLR 0x501d4
+/* [RW 27] Parity mask register #0 read/write */
+#define TCM_REG_TCM_PRTY_MASK 0x501ec
+/* [R 27] Parity register #0 read */
+#define TCM_REG_TCM_PRTY_STS 0x501e0
+/* [RC 27] Parity register #0 read clear */
+#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define TCM_REG_TQM_INIT_CRD 0x5021c
+/* [RC 1] Message length mismatch (relative to last indication) at the SDM
+ * interface.
+ */
+#define TCM_REG_TSDM_LENGTH_MIS 0x50164
+/* [RC 1] Message length mismatch (relative to last indication) at the In#8
+ * interface.
+ */
+#define TCM_REG_USEM_LENGTH_MIS 0x50170
+/* [RW 21] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - length of the message; 15:6] - message
+ * pointer; 20:16] - next pointer.
+ */
+#define TCM_REG_XX_DESCR_TABLE 0x50280
+#define TCM_REG_XX_DESCR_TABLE_SIZE 29
+/* [R 6] Use to read the value of XX protection Free counter. */
+#define TCM_REG_XX_FREE 0x50178
+#define TM_REG_EN_LINEAR0_TIMER 0x164014
+/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
+#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
+/* [ST 16] Linear0 Number of scans counter. */
+#define TM_REG_LIN0_NUM_SCANS 0x1640a0
+#define TM_REG_LIN0_SCAN_ON 0x1640d0
+/* [RW 24] Linear0 array scan timeout. */
+#define TM_REG_LIN0_SCAN_TIME 0x16403c
+#define TM_REG_LIN0_VNIC_UC 0x164128
+/* [RW 1] Interrupt mask register #0 read/write */
+#define TM_REG_TM_INT_MASK 0x1640fc
+/* [R 1] Interrupt register #0 read */
+#define TM_REG_TM_INT_STS 0x1640f0
+/* [RC 1] Interrupt register #0 read clear */
+#define TM_REG_TM_INT_STS_CLR 0x1640f4
+/* [RW 7] Parity mask register #0 read/write */
+#define TM_REG_TM_PRTY_MASK 0x16410c
+/* [R 7] Parity register #0 read */
+#define TM_REG_TM_PRTY_STS 0x164100
+/* [RC 7] Parity register #0 read clear */
+#define TM_REG_TM_PRTY_STS_CLR 0x164104
+#define TSDM_REG_ENABLE_IN1 0x42238
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
+#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
+/* [R 32] Interrupt register #0 read */
+#define TSDM_REG_TSDM_INT_STS_0 0x42290
+#define TSDM_REG_TSDM_INT_STS_1 0x422a0
+/* [RC 32] Interrupt register #0 read clear */
+#define TSDM_REG_TSDM_INT_STS_CLR_0 0x42294
+#define TSDM_REG_TSDM_INT_STS_CLR_1 0x422a4
+/* [RW 11] Parity mask register #0 read/write */
+#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
+/* [R 11] Parity register #0 read */
+#define TSDM_REG_TSDM_PRTY_STS 0x422b0
+/* [RC 11] Parity register #0 read clear */
+#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each
+ * SEM_FAST register offset.
+ */
+#define TSEM_REG_FAST_MEMORY 0x1a0000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define TSEM_REG_INT_TABLE 0x180400
+/* [WB 128] Debug only. Passive buffer memory */
+#define TSEM_REG_PASSIVE_BUFFER 0x181000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define TSEM_REG_PRAM 0x1c0000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define TSEM_REG_TSEM_INT_MASK_0 0x180100
+#define TSEM_REG_TSEM_INT_MASK_1 0x180110
+/* [R 32] Interrupt register #0 read */
+#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
+#define TSEM_REG_TSEM_INT_STS_1 0x180104
+/* [RC 32] Interrupt register #0 read clear */
+#define TSEM_REG_TSEM_INT_STS_CLR_0 0x1800f8
+#define TSEM_REG_TSEM_INT_STS_CLR_1 0x180108
+/* [RW 32] Parity mask register #0 read/write */
+#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
+#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
+/* [R 32] Parity register #0 read */
+#define TSEM_REG_TSEM_PRTY_STS_0 0x180114
+#define TSEM_REG_TSEM_PRTY_STS_1 0x180124
+/* [RC 32] Parity register #0 read clear */
+#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
+#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
+ */
+#define TSEM_REG_VFPF_ERR_NUM 0x180380
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define UCM_REG_CAM_OCCUP 0xe0170
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define UCM_REG_CFC_INIT_CRD 0xe0204
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the csem interface is detected.
+ */
+#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the dorq interface is detected.
+ */
+#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define UCM_REG_FIC0_INIT_CRD 0xe020c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define UCM_REG_FIC1_INIT_CRD 0xe0210
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the STORM interface is detected.
+ */
+#define UCM_REG_STORM_LENGTH_MIS 0xe0154
+/* [RW 4] Timers output initial credit. Max credit available - 15.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 4 at start-up.
+ */
+#define UCM_REG_TM_INIT_CRD 0xe021c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the tsem interface is detected.
+ */
+#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
+/* [RW 11] Interrupt mask register #0 read/write */
+#define UCM_REG_UCM_INT_MASK 0xe01d4
+/* [R 11] Interrupt register #0 read */
+#define UCM_REG_UCM_INT_STS 0xe01c8
+/* [RC 11] Interrupt register #0 read clear */
+#define UCM_REG_UCM_INT_STS_CLR 0xe01cc
+/* [RW 27] Parity mask register #0 read/write */
+#define UCM_REG_UCM_PRTY_MASK 0xe01e4
+/* [R 27] Parity register #0 read */
+#define UCM_REG_UCM_PRTY_STS 0xe01d8
+/* [RC 27] Parity register #0 read clear */
+#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define UCM_REG_UQM_INIT_CRD 0xe0220
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the SDM interface is detected.
+ */
+#define UCM_REG_USDM_LENGTH_MIS 0xe0158
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the xsem interface isdetected.
+ */
+#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
+/* [RW 20] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are:[5:0] - message length; 14:6] - message
+ * pointer; 19:15] - next pointer.
+ */
+#define UCM_REG_XX_DESCR_TABLE 0xe0280
+#define UCM_REG_XX_DESCR_TABLE_SIZE 27
+/* [R 6] Use to read the XX protection Free counter. */
+#define UCM_REG_XX_FREE 0xe016c
+#define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1 << 10)
+#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1 << 28)
+#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1 << 15)
+#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1 << 24)
+#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1 << 5)
+#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1 << 8)
+#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1 << 4)
+#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1 << 1)
+#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1 << 13)
+#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1 << 0)
+#define UMAC_REG_COMMAND_CONFIG 0x8
+/* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE
+ * state from LPI state when it receives packet for transmission. The
+ * decrement unit is 1 micro-second.
+ */
+#define UMAC_REG_EEE_WAKE_TIMER 0x6c
+/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
+ * to bit 17 of the MAC address etc.
+ */
+#define UMAC_REG_MAC_ADDR0 0xc
+/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
+ * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved.
+ */
+#define UMAC_REG_MAC_ADDR1 0x10
+/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
+ * logic to check frames.
+ */
+#define UMAC_REG_MAXFR 0x14
+#define UMAC_REG_UMAC_EEE_CTRL 0x64
+#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1 << 3)
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
+/* [R 1] parser fifo empty in sdm_sync block */
+#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
+/* [RW 32] Interrupt mask register #0 read/write */
+#define USDM_REG_USDM_INT_MASK_0 0xc42a0
+#define USDM_REG_USDM_INT_MASK_1 0xc42b0
+/* [R 32] Interrupt register #0 read */
+#define USDM_REG_USDM_INT_STS_0 0xc4294
+#define USDM_REG_USDM_INT_STS_1 0xc42a4
+/* [RC 32] Interrupt register #0 read clear */
+#define USDM_REG_USDM_INT_STS_CLR_0 0xc4298
+#define USDM_REG_USDM_INT_STS_CLR_1 0xc42a8
+/* [RW 11] Parity mask register #0 read/write */
+#define USDM_REG_USDM_PRTY_MASK 0xc42c0
+/* [R 11] Parity register #0 read */
+#define USDM_REG_USDM_PRTY_STS 0xc42b4
+/* [RC 11] Parity register #0 read clear */
+#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each
+ * SEM_FAST register offset.
+ */
+#define USEM_REG_FAST_MEMORY 0x320000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define USEM_REG_INT_TABLE 0x300400
+/* [WB 128] Debug only. Passive buffer memory */
+#define USEM_REG_PASSIVE_BUFFER 0x302000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define USEM_REG_PRAM 0x340000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define USEM_REG_USEM_INT_MASK_0 0x300110
+#define USEM_REG_USEM_INT_MASK_1 0x300120
+/* [R 32] Interrupt register #0 read */
+#define USEM_REG_USEM_INT_STS_0 0x300104
+#define USEM_REG_USEM_INT_STS_1 0x300114
+/* [RC 32] Interrupt register #0 read clear */
+#define USEM_REG_USEM_INT_STS_CLR_0 0x300108
+#define USEM_REG_USEM_INT_STS_CLR_1 0x300118
+/* [RW 32] Parity mask register #0 read/write */
+#define USEM_REG_USEM_PRTY_MASK_0 0x300130
+#define USEM_REG_USEM_PRTY_MASK_1 0x300140
+/* [R 32] Parity register #0 read */
+#define USEM_REG_USEM_PRTY_STS_0 0x300124
+#define USEM_REG_USEM_PRTY_STS_1 0x300134
+/* [RC 32] Parity register #0 read clear */
+#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
+#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
+ */
+#define USEM_REG_VFPF_ERR_NUM 0x300380
+#define VFC_MEMORIES_RST_REG_CAM_RST (0x1 << 0)
+#define VFC_MEMORIES_RST_REG_RAM_RST (0x1 << 1)
+#define VFC_REG_MEMORIES_RST 0x1943c
+/* [RW 1] Interrupt mask register #0 read/write */
+#define VFC_REG_VFC_INT_MASK 0x194f0
+/* [R 1] Interrupt register #0 read */
+#define VFC_REG_VFC_INT_STS 0x194fc
+/* [RC 1] Interrupt register #0 read clear */
+#define VFC_REG_VFC_INT_STS_CLR 0x194f8
+/* [RW 1] Parity mask register #0 read/write */
+#define VFC_REG_VFC_PRTY_MASK 0x194e0
+/* [R 1] Parity register #0 read */
+#define VFC_REG_VFC_PRTY_STS 0x194ec
+/* [RC 1] Parity register #0 read clear */
+#define VFC_REG_VFC_PRTY_STS_CLR 0x194e8
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define XCM_REG_CAM_OCCUP 0x20244
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define XCM_REG_CFC_INIT_CRD 0x20404
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the csem interface.
+ */
+#define XCM_REG_CSEM_LENGTH_MIS 0x20228
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the dorq interface.
+ */
+#define XCM_REG_DORQ_LENGTH_MIS 0x20230
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define XCM_REG_FIC0_INIT_CRD 0x2040c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define XCM_REG_FIC1_INIT_CRD 0x20410
+#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the nig0 interface.
+ */
+#define XCM_REG_NIG0_LENGTH_MIS 0x20238
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the nig1 interface.
+ */
+#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the pbf interface.
+ */
+#define XCM_REG_PBF_LENGTH_MIS 0x20234
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the STORM interface.
+ */
+#define XCM_REG_STORM_LENGTH_MIS 0x2021c
+/* [RW 4] Timers output initial credit. Max credit available - 15.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 4 at start-up.
+ */
+#define XCM_REG_TM_INIT_CRD 0x2041c
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the tsem interface.
+ */
+#define XCM_REG_TSEM_LENGTH_MIS 0x20224
+/* [RC 1] Message length mismatch (relative to last indication) at the usem
+ * interface.
+ */
+#define XCM_REG_USEM_LENGTH_MIS 0x2022c
+#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
+#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
+/* [RW 14] Interrupt mask register #0 read/write */
+#define XCM_REG_XCM_INT_MASK 0x202b4
+/* [R 14] Interrupt register #0 read */
+#define XCM_REG_XCM_INT_STS 0x202a8
+/* [RC 14] Interrupt register #0 read clear */
+#define XCM_REG_XCM_INT_STS_CLR 0x202ac
+/* [RW 30] Parity mask register #0 read/write */
+#define XCM_REG_XCM_PRTY_MASK 0x202c4
+/* [R 30] Parity register #0 read */
+#define XCM_REG_XCM_PRTY_STS 0x202b8
+/* [RC 30] Parity register #0 read clear */
+#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define XCM_REG_XQM_INIT_CRD 0x20420
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+ * the SDM interface.
+ */
+#define XCM_REG_XSDM_LENGTH_MIS 0x20220
+/* [RW 17] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - message length; 11:6] - message
+ * pointer; 16:12] - next pointer.
+ */
+#define XCM_REG_XX_DESCR_TABLE 0x20480
+#define XCM_REG_XX_DESCR_TABLE_SIZE 32
+/* [R 6] Used to read the XX protection Free counter. */
+#define XCM_REG_XX_FREE 0x20240
+#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1 << 0)
+#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1 << 1)
+#define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1 << 2)
+#define XMAC_CTRL_REG_RX_EN (0x1 << 1)
+#define XMAC_CTRL_REG_SOFT_RESET (0x1 << 6)
+#define XMAC_CTRL_REG_TX_EN (0x1 << 0)
+#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1 << 7)
+#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1 << 18)
+#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1 << 17)
+#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1 << 1)
+#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1 << 0)
+#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1 << 3)
+#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1 << 4)
+#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1 << 5)
+#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
+#define XMAC_REG_CTRL 0
+/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
+ * packets transmitted by the MAC
+ */
+#define XMAC_REG_CTRL_SA_HI 0x2c
+/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
+ * packets transmitted by the MAC
+ */
+#define XMAC_REG_CTRL_SA_LO 0x28
+#define XMAC_REG_EEE_CTRL 0xd8
+#define XMAC_REG_EEE_TIMERS_HI 0xe4
+#define XMAC_REG_PAUSE_CTRL 0x68
+#define XMAC_REG_PFC_CTRL 0x70
+#define XMAC_REG_PFC_CTRL_HI 0x74
+#define XMAC_REG_RX_LSS_CTRL 0x50
+#define XMAC_REG_RX_LSS_STATUS 0x58
+/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
+ * CRC in strip mode
+ */
+#define XMAC_REG_RX_MAX_SIZE 0x40
+#define XMAC_REG_TX_CTRL 0x20
+#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1 << 0)
+#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1 << 1)
+/* [W 17] Generate an operation after completion; bit-16 is
+ * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
+ * bits 4:0 are the T124Param[4:0]
+ */
+#define XSDM_REG_OPERATION_GEN 0x1664c4
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
+/* [RW 32] Interrupt mask register #0 read/write */
+#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
+#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
+/* [R 32] Interrupt register #0 read */
+#define XSDM_REG_XSDM_INT_STS_0 0x166290
+#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
+/* [RC 32] Interrupt register #0 read clear */
+#define XSDM_REG_XSDM_INT_STS_CLR_0 0x166294
+#define XSDM_REG_XSDM_INT_STS_CLR_1 0x1662a4
+/* [RW 11] Parity mask register #0 read/write */
+#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
+/* [R 11] Parity register #0 read */
+#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
+/* [RC 11] Parity register #0 read clear */
+#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
+/* [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the SEM_FAST registers the base address
+ * XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each
+ * SEM_FAST register offset.
+ */
+#define XSEM_REG_FAST_MEMORY 0x2a0000
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define XSEM_REG_INT_TABLE 0x280400
+/* [WB 128] Debug only. Passive buffer memory */
+#define XSEM_REG_PASSIVE_BUFFER 0x282000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define XSEM_REG_PRAM 0x2c0000
+/* [R 20] Valid sleeping threads indication have bit per thread */
+#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
+/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
+ * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
+ */
+#define XSEM_REG_VFPF_ERR_NUM 0x280380
+/* [RW 32] Interrupt mask register #0 read/write */
+#define XSEM_REG_XSEM_INT_MASK_0 0x280110
+#define XSEM_REG_XSEM_INT_MASK_1 0x280120
+/* [R 32] Interrupt register #0 read */
+#define XSEM_REG_XSEM_INT_STS_0 0x280104
+#define XSEM_REG_XSEM_INT_STS_1 0x280114
+/* [RC 32] Interrupt register #0 read clear */
+#define XSEM_REG_XSEM_INT_STS_CLR_0 0x280108
+#define XSEM_REG_XSEM_INT_STS_CLR_1 0x280118
+/* [RW 32] Parity mask register #0 read/write */
+#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
+#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
+/* [R 32] Parity register #0 read */
+#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
+#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
+/* [RC 32] Parity register #0 read clear */
+#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
+#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
+#define MCPR_ACCESS_LOCK_LOCK (1L << 31)
+#define MCPR_IMC_COMMAND_ENABLE (1L << 31)
+#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
+#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
+#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
+#define MCPR_NVM_ACCESS_ENABLE_EN (1L << 0)
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L << 1)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL << 0)
+#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L << 0)
+#define MCPR_NVM_COMMAND_DOIT (1L << 4)
+#define MCPR_NVM_COMMAND_DONE (1L << 3)
+#define MCPR_NVM_COMMAND_FIRST (1L << 7)
+#define MCPR_NVM_COMMAND_LAST (1L << 8)
+#define MCPR_NVM_COMMAND_WR (1L << 5)
+#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L << 9)
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L << 5)
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L << 1)
+#define BIGMAC_REGISTER_BMAC_CONTROL (0x00 << 3)
+#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01 << 3)
+#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05 << 3)
+#define BIGMAC_REGISTER_RX_CONTROL (0x21 << 3)
+#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46 << 3)
+#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43 << 3)
+#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23 << 3)
+#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26 << 3)
+#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42 << 3)
+#define BIGMAC_REGISTER_TX_CONTROL (0x07 << 3)
+#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09 << 3)
+#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A << 3)
+#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08 << 3)
+#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20 << 3)
+#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C << 3)
+#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00 << 3)
+#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01 << 3)
+#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05 << 3)
+#define BIGMAC2_REGISTER_PFC_CONTROL (0x06 << 3)
+#define BIGMAC2_REGISTER_RX_CONTROL (0x3A << 3)
+#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62 << 3)
+#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E << 3)
+#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C << 3)
+#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40 << 3)
+#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f << 3)
+#define BIGMAC2_REGISTER_TX_CONTROL (0x1C << 3)
+#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E << 3)
+#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20 << 3)
+#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D << 3)
+#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39 << 3)
+#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22 << 3)
+#define EMAC_LED_1000MB_OVERRIDE (1L << 1)
+#define EMAC_LED_100MB_OVERRIDE (1L << 2)
+#define EMAC_LED_10MB_OVERRIDE (1L << 3)
+#define EMAC_LED_OVERRIDE (1L << 0)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L << 26)
+#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L << 26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L << 26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L << 26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L << 26)
+#define EMAC_MDIO_COMM_DATA (0xffffL << 0)
+#define EMAC_MDIO_COMM_START_BUSY (1L << 29)
+#define EMAC_MDIO_MODE_AUTO_POLL (1L << 4)
+#define EMAC_MDIO_MODE_CLAUSE_45 (1L << 31)
+#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL << 16)
+#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
+#define EMAC_MDIO_STATUS_10MB (1L << 1)
+#define EMAC_MODE_25G_MODE (1L << 5)
+#define EMAC_MODE_HALF_DUPLEX (1L << 1)
+#define EMAC_MODE_PORT_GMII (2L << 2)
+#define EMAC_MODE_PORT_MII (1L << 2)
+#define EMAC_MODE_PORT_MII_10M (3L << 2)
+#define EMAC_MODE_RESET (1L << 0)
+#define EMAC_REG_EMAC_LED 0xc
+#define EMAC_REG_EMAC_MAC_MATCH 0x10
+#define EMAC_REG_EMAC_MDIO_COMM 0xac
+#define EMAC_REG_EMAC_MDIO_MODE 0xb4
+#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
+#define EMAC_REG_EMAC_MODE 0x0
+#define EMAC_REG_EMAC_RX_MODE 0xc8
+#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
+#define EMAC_REG_EMAC_RX_STAT_AC 0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_TX_MODE 0xbc
+#define EMAC_REG_EMAC_TX_STAT_AC 0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_REG_RX_PFC_MODE 0x320
+#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L << 2)
+#define EMAC_REG_RX_PFC_MODE_RX_EN (1L << 1)
+#define EMAC_REG_RX_PFC_MODE_TX_EN (1L << 0)
+#define EMAC_REG_RX_PFC_PARAM 0x324
+#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
+#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff << 0)
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff << 0)
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff << 0)
+#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
+#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff << 0)
+#define EMAC_RX_MODE_FLOW_EN (1L << 2)
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L << 3)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L << 10)
+#define EMAC_RX_MODE_PROMISCUOUS (1L << 8)
+#define EMAC_RX_MODE_RESET (1L << 0)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L << 31)
+#define EMAC_TX_MODE_EXT_PAUSE_EN (1L << 3)
+#define EMAC_TX_MODE_FLOW_EN (1L << 4)
+#define EMAC_TX_MODE_RESET (1L << 0)
+#define MISC_REGISTERS_GPIO_0 0
+#define MISC_REGISTERS_GPIO_1 1
+#define MISC_REGISTERS_GPIO_2 2
+#define MISC_REGISTERS_GPIO_3 3
+#define MISC_REGISTERS_GPIO_CLR_POS 16
+#define MISC_REGISTERS_GPIO_FLOAT (0xffL << 24)
+#define MISC_REGISTERS_GPIO_FLOAT_POS 24
+#define MISC_REGISTERS_GPIO_HIGH 1
+#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
+#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
+#define MISC_REGISTERS_GPIO_INT_SET_POS 16
+#define MISC_REGISTERS_GPIO_LOW 0
+#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
+#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
+#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
+#define MISC_REGISTERS_GPIO_SET_POS 8
+#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
+#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1 << 0)
+#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1 << 19)
+#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1 << 29)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1 << 26)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1 << 27)
+#define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1 << 17)
+#define MISC_REGISTERS_RESET_REG_1_SET 0x584
+#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
+#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1 << 24)
+#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1 << 25)
+#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1 << 19)
+#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1 << 17)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1 << 0)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1 << 1)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1 << 2)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1 << 14)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1 << 3)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1 << 15)
+#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1 << 4)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1 << 6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1 << 8)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1 << 7)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1 << 5)
+#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1 << 11)
+#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1 << 13)
+#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR (0x1 << 16)
+#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1 << 9)
+#define MISC_REGISTERS_RESET_REG_2_SET 0x594
+#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1 << 20)
+#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1 << 21)
+#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1 << 22)
+#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1 << 23)
+#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1 << 1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1 << 2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1 << 3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1 << 0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1 << 5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1 << 6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1 << 7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1 << 4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1 << 8)
+#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
+#define MISC_SPIO_CLR_POS 16
+#define MISC_SPIO_FLOAT (0xffL << 24)
+#define MISC_SPIO_FLOAT_POS 24
+#define MISC_SPIO_INPUT_HI_Z 2
+#define MISC_SPIO_INT_OLD_SET_POS 16
+#define MISC_SPIO_OUTPUT_HIGH 1
+#define MISC_SPIO_OUTPUT_LOW 0
+#define MISC_SPIO_SET_POS 8
+#define MISC_SPIO_SPIO4 0x10
+#define MISC_SPIO_SPIO5 0x20
+#define HW_LOCK_MAX_RESOURCE_VALUE 31
+#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13
+#define HW_LOCK_RESOURCE_DRV_FLAGS 10
+#define HW_LOCK_RESOURCE_GPIO 1
+#define HW_LOCK_RESOURCE_MDIO 0
+#define HW_LOCK_RESOURCE_NVRAM 12
+#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
+#define HW_LOCK_RESOURCE_RECOVERY_REG 11
+#define HW_LOCK_RESOURCE_RESET 5
+#define HW_LOCK_RESOURCE_SPIO 2
+#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1 << 4)
+#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1 << 5)
+#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1 << 19)
+#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1 << 18)
+#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1 << 31)
+#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1 << 30)
+#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1 << 9)
+#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1 << 8)
+#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1 << 7)
+#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1 << 6)
+#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1 << 29)
+#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1 << 28)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1 << 1)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1 << 0)
+#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1 << 18)
+#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1 << 11)
+#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1 << 10)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1 << 13)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1 << 12)
+#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1 << 2)
+#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1 << 12)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1 << 28)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1 << 31)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1 << 29)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1 << 30)
+#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1 << 15)
+#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1 << 14)
+#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1 << 14)
+#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1 << 20)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1 << 31)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1 << 30)
+#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1 << 0)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1 << 2)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1 << 3)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1 << 5)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1 << 4)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1 << 3)
+#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1 << 2)
+#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1 << 3)
+#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1 << 2)
+#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1 << 22)
+#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1 << 15)
+#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1 << 27)
+#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1 << 26)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1 << 5)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1 << 4)
+#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1 << 25)
+#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1 << 24)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1 << 29)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1 << 28)
+#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1 << 23)
+#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1 << 22)
+#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1 << 27)
+#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1 << 26)
+#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1 << 21)
+#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1 << 20)
+#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1 << 25)
+#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1 << 24)
+#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1 << 16)
+#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1 << 9)
+#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1 << 8)
+#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1 << 7)
+#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1 << 6)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1 << 11)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1 << 10)
#define RESERVED_GENERAL_ATTENTION_BIT_0 0
#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
@@ -2155,7 +4467,8 @@
/* Used For Error Recovery: changing this will require more \
changes in code that assume
- * error recovery uses general attn bit20 ! */
+ * error recovery uses general attn bit20 !
+ */
#define ERROR_RECOVERY_ATTENTION_BIT \
RESERVED_GENERAL_ATTENTION_BIT_20
#define RESERVED_ATTENTION_BIT \
@@ -2175,8 +4488,6 @@
#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
#define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32))
-
-
/*
* This file defines GRC base address for every block.
* This file is included by chipsim, asm microcode and cpp microcode.
@@ -2706,7 +5017,7 @@
#define ME_REG_VF_VALID (1<<8)
#define ME_REG_VF_NUM_SHIFT 9
#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
-#define VF_ID(x) ((x & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT)
+#define VF_ID(x) 0 /* TODO: remove def */
#define ME_REG_VF_ERR (0x1<<3)
#define ME_REG_ABS_PF_NUM_SHIFT 16
#define ME_REG_ABS_PF_NUM \
@@ -2819,6 +5130,20 @@
#define PCI_MSIX_TABLE_ENABLE_MASK 0x8000
+#if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID))
+#define PCI_CAP_LIST_ID_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT))
+#define PCI_CAP_LIST_NEXT_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_STATUS))
+#define PCI_STATUS_DEF
+#endif
+#if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST))
+#define PCI_STATUS_CAP_LIST_DEF
+#endif
+
+
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
@@ -3263,6 +5588,9 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
+#define MDIO_AN_REG_848xx_ID_MSB 0xffe2
+#define BNX2X84858_PHY_ID 0x600d
+#define MDIO_AN_REG_848xx_ID_LSB 0xffe3
#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
@@ -3271,6 +5599,7 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
+#define MDIO_AN_REG_8481_INTERRUPT_MASK 0xfffb
#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
/* BNX2X84823 only */
@@ -3299,6 +5628,8 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
+/* BNX2X84858 only */
+#define MDIO_PMA_REG_84858_ALLOW_GPHY_ACT 0x8000
/* BNX2X84833 only */
#define MDIO_84833_TOP_CFG_FW_REV 0x400f
@@ -3306,32 +5637,32 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
#define MDIO_84833_SUPER_ISOLATE 0x8000
-/* These are mailbox register set used by 84833. */
-#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
-#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
-#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
-#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
-#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
-#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
-#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
-#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
-#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
-#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
-#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
-#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
-#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
-#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
-#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
-#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
-#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
-#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
-
-/* Mailbox command set used by 84833. */
-#define PHY84833_CMD_SET_PAIR_SWAP 0x8001
-#define PHY84833_CMD_GET_EEE_MODE 0x8008
-#define PHY84833_CMD_SET_EEE_MODE 0x8009
-#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
-/* Mailbox status set used by 84833. */
+/* These are mailbox register set used by 84833/84858. */
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
+#define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
+#define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
+#define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
+#define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
+#define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
+#define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
+#define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
+
+/* Mailbox command set used by 84833/84858 */
+#define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
+#define PHY848xx_CMD_GET_EEE_MODE 0x8008
+#define PHY848xx_CMD_SET_EEE_MODE 0x8009
+#define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031
+/* Mailbox status set used by 84833 only */
#define PHY84833_STATUS_CMD_RECEIVED 0x0001
#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
@@ -3341,6 +5672,17 @@ Theotherbitsarereservedandshouldbezero*/
#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
+/* Mailbox Process */
+#define PHY84833_MB_PROCESS1 1
+#define PHY84833_MB_PROCESS2 2
+#define PHY84833_MB_PROCESS3 3
+
+/* Mailbox status set used by 84858 only */
+#define PHY84858_STATUS_CMD_RECEIVED 0x0001
+#define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
+#define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
+#define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
+#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
/* Warpcore clause 45 addressing */
@@ -3367,6 +5709,8 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
@@ -3382,7 +5726,9 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
+#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
+#define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
#define MDIO_WC_REG_XGXS_STATUS3 0x8129
#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
@@ -3432,7 +5778,10 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
+#define AUTODET_EN (1 << 4)
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
+#define EN_PARALLEL_DET 1
+#define FILTER_FORCE_LINK (1 << 2)
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
@@ -3501,10 +5850,15 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_REG_GPHY_CL45_REG_READ 0xc000
#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
+#define MDIO_REG_GPHY_BASET_EXT_CTRL 0x10
+#define MDIO_REG_GPHY_TX_HIGH_LATENCY 0x1
#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
#define MDIO_REG_GPHY_EXP_ACCESS 0x17
#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
+#define MDIO_REG_GPHY_SHADOW_ACCESS 0x18
+#define MDIO_REG_GPHY_SHADOW_AUX_CTRL (0x0)
+#define MDIO_REG_GPHY_SHADOW_MISC_CTRL (0x7)
#define MDIO_REG_GPHY_AUX_STATUS 0x19
#define MDIO_REG_INTR_STATUS 0x1a
#define MDIO_REG_INTR_MASK 0x1b
@@ -3516,7 +5870,6 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
-
#define IGU_FUNC_BASE 0x0400
#define IGU_ADDR_MSIX 0x0000
@@ -3585,7 +5938,7 @@ Theotherbitsarereservedandshouldbezero*/
#define IGU_SEG_IDX_ATTN 2
#define IGU_SEG_IDX_DEFAULT 1
-/* Fields of IGU PF CONFIGRATION REGISTER */
+/* Fields of IGU PF CONFIGURATION REGISTER */
#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
@@ -3593,7 +5946,7 @@ Theotherbitsarereservedandshouldbezero*/
#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
-/* Fields of IGU VF CONFIGRATION REGISTER */
+/* Fields of IGU VF CONFIGURATION REGISTER */
#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 2/3] net/bnx2x: update HSI code
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (12 preceding siblings ...)
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 1/3] net/bnx2x: update and reorganize HW registers Rasesh Mody
@ 2019-10-02 19:14 ` Rasesh Mody
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 3/3] net/bnx2x: update to latest FW 7.13.11 Rasesh Mody
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-10-02 19:14 UTC (permalink / raw)
To: dev, jerinj, ferruh.yigit; +Cc: Rasesh Mody, GR-Everest-DPDK-Dev
Update hardware software common base driver code in preparation to
update the firmware to version 7.13.11.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/bnx2x/bnx2x.c | 20 +-
drivers/net/bnx2x/bnx2x.h | 23 +-
drivers/net/bnx2x/bnx2x_osal.h | 29 +
drivers/net/bnx2x/bnx2x_rxtx.c | 10 +-
drivers/net/bnx2x/ecore_hsi.h | 3508 ++++++++++++++++++--------------
drivers/net/bnx2x/ecore_sp.c | 11 +-
6 files changed, 1994 insertions(+), 1607 deletions(-)
create mode 100644 drivers/net/bnx2x/bnx2x_osal.h
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index d552f50e2..010e16088 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -2182,8 +2182,10 @@ int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
- tx_start_bd->addr =
- rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
+ tx_start_bd->addr_lo =
+ rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
+ tx_start_bd->addr_hi =
+ rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
tx_start_bd->general_data =
@@ -5015,13 +5017,14 @@ static void
bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
- union ustorm_eth_rx_producers rx_prods;
+ struct ustorm_eth_rx_producers rx_prods;
uint32_t i;
+ memset(&rx_prods, 0, sizeof(rx_prods));
+
/* update producers */
- rx_prods.prod.bd_prod = rx_bd_prod;
- rx_prods.prod.cqe_prod = rx_cq_prod;
- rx_prods.prod.reserved = 0;
+ rx_prods.bd_prod = rx_bd_prod;
+ rx_prods.cqe_prod = rx_cq_prod;
/*
* Make sure that the BD and SGE data is updated before updating the
@@ -5034,9 +5037,8 @@ bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
wmb();
for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
- REG_WR(sc,
- (fp->ustorm_rx_prods_offset + (i * 4)),
- rx_prods.raw_data[i]);
+ REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
+ ((uint32_t *)&rx_prods)[i]);
}
wmb(); /* keep prod updates ordered */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 1ea8b55c9..054d95424 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -19,18 +19,7 @@
#include <rte_bus_pci.h>
#include <rte_io.h>
-#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
-#ifndef __LITTLE_ENDIAN
-#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
-#endif
-#undef __BIG_ENDIAN
-#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
-#ifndef __BIG_ENDIAN
-#define __BIG_ENDIAN RTE_BIG_ENDIAN
-#endif
-#undef __LITTLE_ENDIAN
-#endif
-
+#include "bnx2x_osal.h"
#include "bnx2x_ethdev.h"
#include "ecore_mfw_req.h"
#include "ecore_fw_defs.h"
@@ -1911,16 +1900,18 @@ bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
{
uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
COMMAND_REG_INT_ACK);
- union igu_ack_register igu_ack;
+ struct igu_ack_register igu_ack;
+ uint32_t *val = NULL;
- igu_ack.sb.status_block_index = index;
- igu_ack.sb.sb_id_and_flags =
+ igu_ack.status_block_index = index;
+ igu_ack.sb_id_and_flags =
((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
(storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
- REG_WR(sc, hc_addr, igu_ack.raw_data);
+ val = (uint32_t *)&igu_ack;
+ REG_WR(sc, hc_addr, *val);
/* Make sure that ACK is written */
mb();
diff --git a/drivers/net/bnx2x/bnx2x_osal.h b/drivers/net/bnx2x/bnx2x_osal.h
new file mode 100644
index 000000000..7cd293259
--- /dev/null
+++ b/drivers/net/bnx2x/bnx2x_osal.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2019 Cavium Inc.
+ *
+ * All rights reserved.
+ * www.cavium.com
+ */
+
+#ifndef BNX2X_OSAL_H
+#define BNX2X_OSAL_H
+
+#include <sys/stat.h>
+
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
+#endif
+#undef __BIG_ENDIAN
+#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN RTE_BIG_ENDIAN
+#endif
+#undef __LITTLE_ENDIAN
+#endif
+
+#define __le16 uint16_t
+#define __le32 uint32_t
+#define __le64 uint64_t
+
+#endif /* BNX2X_OSAL_H */
diff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c
index e5a2b25b5..ae97dfee3 100644
--- a/drivers/net/bnx2x/bnx2x_rxtx.c
+++ b/drivers/net/bnx2x/bnx2x_rxtx.c
@@ -321,12 +321,14 @@ static inline void
bnx2x_upd_rx_prod_fast(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
- union ustorm_eth_rx_producers rx_prods;
+ struct ustorm_eth_rx_producers rx_prods = { 0 };
+ uint32_t *val = NULL;
- rx_prods.prod.bd_prod = rx_bd_prod;
- rx_prods.prod.cqe_prod = rx_cq_prod;
+ rx_prods.bd_prod = rx_bd_prod;
+ rx_prods.cqe_prod = rx_cq_prod;
- REG_WR(sc, fp->ustorm_rx_prods_offset, rx_prods.raw_data[0]);
+ val = (uint32_t *)&rx_prods;
+ REG_WR(sc, fp->ustorm_rx_prods_offset, val[0]);
}
static uint16_t
diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index 74189eed6..2728deb1d 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -13,29 +13,32 @@
#ifndef ECORE_HSI_H
#define ECORE_HSI_H
-#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
+#include "ecore_fw_defs.h"
+#include "ecore_mfw_req.h"
+#include "bnx2x_osal.h"
+
+#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
struct license_key {
- uint32_t reserved[6];
+ uint32_t reserved[6];
- uint32_t max_iscsi_conn;
-#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
-#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
-#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
-#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
+ uint32_t max_iscsi_conn;
+#define ECORE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
+#define ECORE_MAX_ISCSI_TRGT_CONN_SHIFT 0
+#define ECORE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
+#define ECORE_MAX_ISCSI_INIT_CONN_SHIFT 16
- uint32_t reserved_a;
+ uint32_t reserved_a;
- uint32_t max_fcoe_conn;
-#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
-#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
-#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
-#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
+ uint32_t max_fcoe_conn;
+#define ECORE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
+#define ECORE_MAX_FCOE_TRGT_CONN_SHIFT 0
+#define ECORE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
+#define ECORE_MAX_FCOE_INIT_CONN_SHIFT 16
- uint32_t reserved_b[4];
+ uint32_t reserved_b[4];
};
-typedef struct license_key license_key_t;
/****************************************************************************
@@ -270,6 +273,14 @@ struct shared_hw_cfg { /* NVRAM Offset */
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
+ /* This field extends the mf mode chosen in nvm cfg #73 (as we ran
+ * out of bits)
+ */
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
+ #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
+
uint32_t ump_nc_si_config; /* 0x120 */
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
@@ -332,6 +343,7 @@ struct shared_hw_cfg { /* NVRAM Offset */
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
+ #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000
};
@@ -499,7 +511,6 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
*/
#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
-
/* Set non-default values for TXFIR in SFP mode. */
#define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
@@ -672,7 +683,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002
- #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
+ #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020
@@ -738,6 +749,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8722 0x00000f00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54616 0x00001000
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84834 0x00001100
+ #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84858 0x00001200
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
@@ -874,6 +886,9 @@ struct shared_feat_cfg { /* NVRAM Offset */
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
+ #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
/* Act as if the FCoE license is invalid */
#define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000
@@ -958,6 +973,12 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00
+ #define PORT_FEAT_CFG_DCBX_SEL_MASK 0x00003000
+ #define PORT_FEAT_CFG_DCBX_SEL_SHIFT 12
+ #define PORT_FEAT_CFG_DCBX_SEL_CEE 0x00000000
+ #define PORT_FEAT_CFG_DCBX_SEL_IEEE 0x00001000
+ #define PORT_FEAT_CFG_DCBX_SEL_AUTO 0x00002000
+
#define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
#define PORT_FEATURE_EN_SIZE_SHIFT 24
#define PORT_FEATURE_WOL_ENABLED 0x01000000
@@ -1040,14 +1061,24 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000
#define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000
- uint32_t Reserved0; /* 0x460 */
+ /* Secondary MBA configuration,
+ * see mba_config for the fileds defination.
+ */
+ uint32_t mba_config2;
uint32_t mba_vlan_cfg;
#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF
#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
+ #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000
+ #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000
+ #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000
+
+ /* Secondary MBA configuration,
+ * see mba_vlan_cfg for the fileds defination.
+ */
+ uint32_t mba_vlan_cfg2;
- uint32_t Reserved1;
uint32_t smbus_config;
#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
@@ -1088,8 +1119,8 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000
#define PORT_FEATURE_LINK_SPEED_SHIFT 16
#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
- #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
- #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
+ #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000
+ #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000
#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
@@ -1130,7 +1161,7 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
- uint32_t Reserved2[16]; /* 0x488 */
+ uint32_t Reserved2[16]; /* 0x48C */
};
/****************************************************************************
@@ -1241,6 +1272,16 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0
+ /* Sensor interface - Disabled / BSC / In the future - SMBUS */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED \
+ 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000
+
+ /* On Board Sensor Address */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18
/* MFW flavor to be used */
uint32_t mfw_cfg; /* 0x4008 */
@@ -1255,6 +1296,32 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100
+ /* Prevent OCBB feature */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200
+
+ /* Enable DCi support */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400
+
+ /* Reserved bits: 75 */
+
+ /* PLDM support over MCTP */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_MASK 0x00001000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_SHIFT 12
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_ENABLED 0x00001000
+
+ /* Option to Disable embedded LLDP, 0 - Off, 1 - On */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_MASK 0x00002000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_SHIFT 13
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_OFF 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_ON 0x00002000
+
/* Hide DCBX feature in CCM/BACS menus */
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16
@@ -1291,6 +1358,26 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200
+ /* Override PCIE revision ID when enabled the,
+ * revision ID will set to B1=='0x11'
+ */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400
+
+ /* Bypass slicer offset tuning */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800
+ /* Control Revision ID */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000
/* Threshold in celcius for max continuous operation */
uint32_t temperature_report; /* 0x4014 */
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F
@@ -1341,6 +1428,14 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000
+ /* Override Rx signal detect threshold when enabled the threshold
+ * will be set staticaly
+ */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000
+
/* Debug signet rx threshold */
uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007
@@ -1434,6 +1529,31 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16
#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000
#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24
+
+ /* Manufacture kit version */
+ uint32_t manufacture_ver; /* 0x403C */
+
+ /* Manufacture timestamp */
+ uint32_t manufacture_data; /* 0x4040 */
+
+ /* Number of ISCSI/FCOE cfg images */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000
+
+ /* MCP crash dump trigger */
+ uint32_t mcp_crash_dump; /* 0x4044 */
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000
+ #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001
+
+ /* MBI version */
+ uint32_t mbi_version; /* 0x4048 */
+
+ /* MBI date */
+ uint32_t mbi_date; /* 0x404C */
};
@@ -1449,6 +1569,7 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
+#define E1_FUNC_MAX 2
#define E1H_FUNC_MAX 8
#define E2_FUNC_MAX 4 /* per path */
@@ -1575,6 +1696,10 @@ struct drv_func_mb {
#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
+ #define DRV_MSG_CODE_OEM_OK 0x00010000
+ #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
/*
* The optic module verification command requires bootcode
@@ -1629,8 +1754,15 @@ struct drv_func_mb {
#define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000
#define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000
+ #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000
+
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
+ #define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000
+
+ #define DRV_MSG_CODE_UPDATE_DRIVER_STATE 0xC2000000
+ #define REQ_BC_VER_4_UPDATE_DRIVER_STATE 0x00070f35
+
uint32_t drv_mb_param;
#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
@@ -1642,6 +1774,22 @@ struct drv_func_mb {
#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
#define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001
+ #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002
+ #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003
+ #define DRV_MSG_CODE_VLAN_TABLE_IMAGE_REQ 0x00000004
+
+ #define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001
+ #define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002
+ #define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003
+ #define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004
+ #define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005
+ #define DRV_MSG_CODE_CONFIG_CHANGE_RST2DFT 0x00000006
+
+ #define DRV_MSG_CODE_DRIVER_STATE_UNKNOWN 0x00000001
+ #define DRV_MSG_CODE_DRIVER_STATE_NOT_LOADED 0x00000002
+ #define DRV_MSG_CODE_DRIVER_STATE_LOADING 0x00000003
+ #define DRV_MSG_CODE_DRIVER_STATE_DISABLED 0x00000004
+ #define DRV_MSG_CODE_DRIVER_STATE_ACTIVE 0x00000005
uint32_t fw_mb_header;
#define FW_MSG_CODE_MASK 0xffff0000
@@ -1708,6 +1856,13 @@ struct drv_func_mb {
#define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000
#define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000
+ #define FW_MSG_CODE_OEM_ACK 0x00010000
+ #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000
+
+ #define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000
+
+ #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0xC3000000
+
#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
uint32_t fw_mb_param;
@@ -1745,6 +1900,13 @@ struct drv_func_mb {
#define DRV_STATUS_SET_MF_BW 0x00000004
#define DRV_STATUS_LINK_EVENT 0x00000008
+ #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
+ #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
+ #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
+ #define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040
+
+ #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
+
#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
@@ -1958,7 +2120,7 @@ struct shmem_region { /* SharedMem Offset (size) */
struct shm_dev_info dev_info; /* 0x8 (0x438) */
- license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
+ struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52 * 2 = 0x68) */
/* FW information (for internal FW use) */
uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */
@@ -1976,7 +2138,7 @@ struct shmem_region { /* SharedMem Offset (size) */
struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
#endif /* BMAPI */
-}; /* 57711 = 0x7E4 | 57712 = 0x734 */
+}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
/****************************************************************************
* Shared Memory 2 Region *
@@ -1995,7 +2157,7 @@ struct shmem_region { /* SharedMem Offset (size) */
/****************************************************************************/
struct fw_flr_ack {
uint32_t pf_ack;
- uint32_t vf_ack[1];
+ uint32_t vf_ack;
uint32_t iov_dis_ack;
};
@@ -2134,17 +2296,30 @@ struct dcbx_app_priority_entry {
uint8_t pri_bitmap;
uint8_t appBitfield;
#define DCBX_APP_ENTRY_VALID 0x01
- #define DCBX_APP_ENTRY_SF_MASK 0x30
+ #define DCBX_APP_ENTRY_SF_MASK 0xF0
#define DCBX_APP_ENTRY_SF_SHIFT 4
#define DCBX_APP_SF_ETH_TYPE 0x10
- #define DCBX_APP_SF_PORT 0x20
+ #define DCBX_APP_SF_PORT 0x20 /* TCP */
+ #define DCBX_APP_SF_UDP 0x40 /* UDP */
+ #define DCBX_APP_SF_DEFAULT 0x80
+ #define DCBX_APP_PRI_0 0x01
+ #define DCBX_APP_PRI_1 0x02
+ #define DCBX_APP_PRI_2 0x04
+ #define DCBX_APP_PRI_3 0x08
+ #define DCBX_APP_PRI_4 0x10
+ #define DCBX_APP_PRI_5 0x20
+ #define DCBX_APP_PRI_6 0x40
+ #define DCBX_APP_PRI_7 0x80
#elif defined(__LITTLE_ENDIAN)
uint8_t appBitfield;
#define DCBX_APP_ENTRY_VALID 0x01
- #define DCBX_APP_ENTRY_SF_MASK 0x30
+ #define DCBX_APP_ENTRY_SF_MASK 0xF0
#define DCBX_APP_ENTRY_SF_SHIFT 4
+ #define DCBX_APP_ENTRY_VALID 0x01
#define DCBX_APP_SF_ETH_TYPE 0x10
- #define DCBX_APP_SF_PORT 0x20
+ #define DCBX_APP_SF_PORT 0x20 /* TCP */
+ #define DCBX_APP_SF_UDP 0x40 /* UDP */
+ #define DCBX_APP_SF_DEFAULT 0x80
uint8_t pri_bitmap;
uint16_t app_id;
#endif
@@ -2343,6 +2518,85 @@ struct shmem_lfa {
};
+/*
+ * Used to suppoert NSCI get OS driver version
+ * On driver load the version value will be set
+ * On driver unload driver value of 0x0 will be set
+ */
+struct os_drv_ver {
+ #define DRV_VER_NOT_LOADED 0
+ /*personalites orrder is importent */
+ #define DRV_PERS_ETHERNET 0
+ #define DRV_PERS_ISCSI 1
+ #define DRV_PERS_FCOE 2
+ /*shmem2 struct is constatnt can't add more personalites here*/
+ #define MAX_DRV_PERS 3
+ uint32_t versions[MAX_DRV_PERS];
+};
+
+#define OEM_I2C_UUID_STR_ADDR 0x9f
+#define OEM_I2C_CARD_SKU_STR_ADDR 0x3c
+#define OEM_I2C_CARD_FN_STR_ADDR 0x48
+#define OEM_I2C_CARD_NAME_STR_ADDR 0x10e
+
+#define OEM_I2C_UUID_STR_LEN 16
+#define OEM_I2C_CARD_SKU_STR_LEN 12
+#define OEM_I2C_CARD_FN_STR_LEN 12
+#define OEM_I2C_CARD_NAME_STR_LEN 128
+#define OEM_I2C_CARD_VERSION_STR_LEN 36
+
+struct oem_i2c_data_t {
+ uint32_t size;
+ uint8_t uuid[OEM_I2C_UUID_STR_LEN];
+ uint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN];
+ uint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN];
+ uint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN];
+ uint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN];
+};
+
+enum curr_cfg_method_e {
+ CURR_CFG_MET_NONE = 0, /* default config */
+ CURR_CFG_MET_OS = 1,
+ CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */
+ CURR_CFG_MET_HP_OTHER = 3,
+ CURR_CFG_MET_VC_CLP = 4, /* C-Class SM-CLP */
+ CURR_CFG_MET_HP_CNU = 5, /* Converged Network Utility */
+ CURR_CFG_MET_HP_DCI = 6, /* DCi (BD) changes */
+};
+
+#define FC_NPIV_WWPN_SIZE 8
+#define FC_NPIV_WWNN_SIZE 8
+struct bdn_npiv_settings {
+ uint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE];
+ uint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE];
+};
+
+struct bdn_fc_npiv_cfg {
+ /* hdr used internally by the MFW */
+ uint32_t hdr;
+ uint32_t num_of_npiv;
+};
+
+#define MAX_NUMBER_NPIV 64
+struct bdn_fc_npiv_tbl {
+ struct bdn_fc_npiv_cfg fc_npiv_cfg;
+ struct bdn_npiv_settings settings[MAX_NUMBER_NPIV];
+};
+
+struct mdump_driver_info {
+ uint32_t epoc;
+ uint32_t drv_ver;
+ uint32_t fw_ver;
+
+ uint32_t valid_dump;
+ #define FIRST_DUMP_VALID (1 << 0)
+ #define SECOND_DUMP_VALID (1 << 1)
+
+ uint32_t flags;
+ #define ENABLE_ALL_TRIGGERS (0x7fffffff)
+ #define TRIGGER_MDUMP_ONCE (1 << 31)
+};
+
struct shmem2_region {
uint32_t size; /* 0x0000 */
@@ -2426,18 +2680,18 @@ struct shmem2_region {
uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
- uint32_t swim_base_addr; /* 0x0108 */
- uint32_t swim_funcs;
- uint32_t swim_main_cb;
+ uint32_t swim_base_addr; /* 0x00a8 */
+ uint32_t swim_funcs; /* 0x00ac */
+ uint32_t swim_main_cb; /* 0x00b0 */
/*
* bitmap notifying which VIF profiles stored in nvram are enabled by
* switch
*/
- uint32_t afex_profiles_enabled[2];
+ uint32_t afex_profiles_enabled[2]; /* 0x00b4 */
/* generic flags controlled by the driver */
- uint32_t drv_flags;
+ uint32_t drv_flags; /* 0x00bc */
#define DRV_FLAGS_DCB_CONFIGURED 0x0
#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
#define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
@@ -2459,45 +2713,47 @@ struct shmem2_region {
(_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
/* pointer to extended dev_info shared data copied from nvm image */
- uint32_t extended_dev_info_shared_addr;
- uint32_t ncsi_oem_data_addr;
+ uint32_t extended_dev_info_shared_addr; /* 0x00c0 */
+ uint32_t ncsi_oem_data_addr; /* 0x00c4 */
- uint32_t sensor_data_addr;
- uint32_t buffer_block_addr;
- uint32_t sensor_data_req_update_interval;
- uint32_t temperature_in_half_celsius;
- uint32_t glob_struct_in_host;
+ uint32_t sensor_data_addr; /* 0x00c8 */
+ uint32_t buffer_block_addr; /* 0x00cc */
+ uint32_t sensor_data_req_update_interval; /* 0x00d0 */
+ uint32_t temperature_in_half_celsius; /* 0x00d4 */
+ uint32_t glob_struct_in_host; /* 0x00d8 */
- uint32_t dcbx_neg_res_ext_offset;
+ uint32_t dcbx_neg_res_ext_offset; /* 0x00dc */
#define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
- uint32_t drv_capabilities_flag[E2_FUNC_MAX];
+ uint32_t drv_capabilities_flag[E2_FUNC_MAX]; /* 0x00e0 */
#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
+ #define DRV_FLAGS_MTU_MASK 0xffff0000
+ #define DRV_FLAGS_MTU_SHIFT 16
- uint32_t extended_dev_info_shared_cfg_size;
+ uint32_t extended_dev_info_shared_cfg_size; /* 0x00f0 */
- uint32_t dcbx_en[PORT_MAX];
+ uint32_t dcbx_en[PORT_MAX]; /* 0x00f4 */
/* The offset points to the multi threaded meta structure */
- uint32_t multi_thread_data_offset;
+ uint32_t multi_thread_data_offset; /* 0x00fc */
/* address of DMAable host address holding values from the drivers */
- uint32_t drv_info_host_addr_lo;
- uint32_t drv_info_host_addr_hi;
+ uint32_t drv_info_host_addr_lo; /* 0x0100 */
+ uint32_t drv_info_host_addr_hi; /* 0x0104 */
/* general values written by the MFW (such as current version) */
- uint32_t drv_info_control;
+ uint32_t drv_info_control; /* 0x0108 */
#define DRV_INFO_CONTROL_VER_MASK 0x000000ff
#define DRV_INFO_CONTROL_VER_SHIFT 0
#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
- uint32_t ibft_host_addr; /* initialized by option ROM */
+ uint32_t ibft_host_addr; /* initialized by option ROM */ /* 0x010c */
- struct eee_remote_vals eee_remote_vals[PORT_MAX];
- uint32_t pf_allocation[E2_FUNC_MAX];
+ struct eee_remote_vals eee_remote_vals[PORT_MAX]; /* 0x0110 */
+ uint32_t pf_allocation[E2_FUNC_MAX]; /* 0x0120 */
#define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
#define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0
@@ -2515,13 +2771,13 @@ struct shmem2_region {
* bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
* value. When 1'b1 those bits contains a value times 16 microseconds.
*/
- uint32_t eee_status[PORT_MAX];
+ uint32_t eee_status[PORT_MAX]; /* 0x0130 */
#define SHMEM_EEE_TIMER_MASK 0x0000ffff
#define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
#define SHMEM_EEE_SUPPORTED_SHIFT 16
#define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
#define SHMEM_EEE_100M_ADV (1<<0)
- #define SHMEM_EEE_1G_ADV (1U<<1)
+ #define SHMEM_EEE_1G_ADV (1 << 1)
#define SHMEM_EEE_10G_ADV (1<<2)
#define SHMEM_EEE_ADV_STATUS_SHIFT 20
#define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
@@ -2531,26 +2787,143 @@ struct shmem2_region {
#define SHMEM_EEE_ACTIVE_BIT 0x40000000
#define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
- uint32_t sizeof_port_stats;
+ uint32_t sizeof_port_stats; /* 0x0138 */
/* Link Flap Avoidance */
- uint32_t lfa_host_addr[PORT_MAX];
+ uint32_t lfa_host_addr[PORT_MAX]; /* 0x013c */
/* External PHY temperature in deg C. */
- uint32_t extphy_temps_in_celsius;
+ uint32_t extphy_temps_in_celsius; /* 0x0144 */
#define EXTPHY1_TEMP_MASK 0x0000ffff
#define EXTPHY1_TEMP_SHIFT 0
+ #define ON_BOARD_TEMP_MASK 0xffff0000
+ #define ON_BOARD_TEMP_SHIFT 16
uint32_t ocdata_info_addr; /* Offset 0x148 */
uint32_t drv_func_info_addr; /* Offset 0x14C */
uint32_t drv_func_info_size; /* Offset 0x150 */
uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */
- #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
- #define LINK_ATTR_84858 0x00000002
- #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
- #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
+ #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
+ #define LINK_ATTR_84858 0x00000002
+ #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
+ #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
+ #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
+ #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
+ #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
+
+ uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */
+ uint32_t fcode_ver; /* Offset 0x15c */
+ uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
+ #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */
+ /* driver version for each personality*/
+ struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
+
+ /* Flag to the driver that PF's drv_info_host_addr buffer was read */
+ uint32_t mfw_drv_indication; /* Offset 0x19c */
+
+ /* We use inidcation for each PF (0..3) */
+ #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
+
+ union { /* For various OEMs */ /* Offset 0x1a0 */
+ uint8_t storage_boot_prog[E2_FUNC_MAX];
+ #define STORAGE_BOOT_PROG_MASK 0x000000FF
+ #define STORAGE_BOOT_PROG_NONE 0x00000000
+ #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
+ #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
+ #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
+ #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
+ #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
+ #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
+ #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
+ #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
+ #define STORAGE_BOOT_PROG_COMPLETED 0x00000080
+
+ uint32_t oem_i2c_data_addr;
+ };
+
+ /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
+ /* For PCP values 0-3 use the map lower */
+ /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
+ * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
+ */
+ uint32_t c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */
+
+ /* For PCP values 4-7 use the map upper */
+ /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
+ * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
+ */
+ uint32_t c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */
+
+ /* For PCP default value get the MSB byte of the map default */
+ uint32_t c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */
+
+ /* FC_NPIV table offset in NVRAM */
+ uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */
+
+ /* Shows last method that changed configuration of this device */
+ enum curr_cfg_method_e curr_cfg; /* 0x1dc */
+
+ /* Storm FW version, shold be kept in the format 0xMMmmbbdd:
+ * MM - Major, mm - Minor, bb - Build ,dd - Drop
+ */
+ uint32_t netproc_fw_ver; /* 0x1e0 */
+
+ /* Option ROM SMASH CLP version */
+ uint32_t clp_ver; /* 0x1e4 */
+
+ uint32_t pcie_bus_num; /* 0x1e8 */
- uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
+ uint32_t sriov_switch_mode; /* 0x1ec */
+ #define SRIOV_SWITCH_MODE_NONE 0x0
+ #define SRIOV_SWITCH_MODE_VEB 0x1
+ #define SRIOV_SWITCH_MODE_VEPA 0x2
+
+ uint8_t rsrv2[E2_FUNC_MAX]; /* 0x1f0 */
+
+ uint32_t img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */
+
+ uint32_t mtu_size[E2_FUNC_MAX]; /* 0x1f8 */
+
+ uint32_t os_driver_state[E2_FUNC_MAX]; /* 0x208 */
+ #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */
+ #define OS_DRIVER_STATE_LOADING 1 /* transition state */
+ #define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */
+ #define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */
+
+ /* mini dump driver info */
+ struct mdump_driver_info drv_info; /* 0x218 */
+
+ /* written by mfw, read by driver, eg. feature capability support */
+ uint32_t mfw_flags; /* 0x22c */
+ #define DISABLE_EMBEDDED_LLDP_SUPPORT 0x00000001
+};
+
+#define VLAN_BITMAP_SIZE 512
+#define VLAN_PF_NUM_MAX 8
+
+struct pf_vlan_table {
+ uint16_t pvid;
+ uint8_t pcp;
+ uint8_t rsvd;
+ uint8_t trunk_vlan_bitmap[VLAN_BITMAP_SIZE];
+ uint32_t rsvd1[4];
+};
+
+struct vlan_table_s {
+ uint32_t version;
+ #define VLAN_TABLE_IMAGE_VERSION_1 1
+ uint8_t vlan_mode[NVM_PATH_MAX][PORT_MAX];
+ #define VLAN_MODE_NORMAL 0
+ #define VLAN_MODE_FILTER 1
+ #define VLAN_MODE_QINQ 2
+ struct pf_vlan_table pf_vlans[VLAN_PF_NUM_MAX];
+ uint32_t rsvd2[8];
+};
+
+/* The VLAN table Image is stored in Big Endian format */
+struct nvm_vlan_table_image {
+ struct vlan_table_s vlan_table;
+ uint32_t crc;
};
@@ -3228,31 +3601,29 @@ struct port_info {
#define BNX2X_5710_FW_MAJOR_VERSION 7
-#define BNX2X_5710_FW_MINOR_VERSION 2
-#define BNX2X_5710_FW_REVISION_VERSION 51
+#define BNX2X_5710_FW_MINOR_VERSION 13
+#define BNX2X_5710_FW_REVISION_VERSION 11
#define BNX2X_5710_FW_ENGINEERING_VERSION 0
#define BNX2X_5710_FW_COMPILE_FLAGS 1
/*
- * attention bits $$KEEP_ENDIANNESS$$
+ * attention bits
*/
-struct atten_sp_status_block
-{
- uint32_t attn_bits /* 16 bit of attention signal lines */;
- uint32_t attn_bits_ack /* 16 bit of attention signal ack */;
- uint8_t status_block_id /* status block id */;
- uint8_t reserved0 /* resreved for padding */;
- uint16_t attn_bits_index /* attention bits running index */;
- uint32_t reserved1 /* resreved for padding */;
+struct atten_sp_status_block {
+ __le32 attn_bits;
+ __le32 attn_bits_ack;
+ uint8_t status_block_id;
+ uint8_t reserved0;
+ __le16 attn_bits_index;
+ __le32 reserved1;
};
/*
* The eth aggregative context of Cstorm
*/
-struct cstorm_eth_ag_context
-{
+struct cstorm_eth_ag_context {
uint32_t __reserved0[10];
};
@@ -3260,101 +3631,100 @@ struct cstorm_eth_ag_context
/*
* dmae command structure
*/
-struct dmae_command
-{
+struct dmae_command {
uint32_t opcode;
-#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */
+#define DMAE_COMMAND_SRC (0x1 << 0)
#define DMAE_COMMAND_SRC_SHIFT 0
-#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
+#define DMAE_COMMAND_DST (0x3 << 1)
#define DMAE_COMMAND_DST_SHIFT 1
-#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */
+#define DMAE_COMMAND_C_DST (0x1 << 3)
#define DMAE_COMMAND_C_DST_SHIFT 3
-#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */
+#define DMAE_COMMAND_C_TYPE_ENABLE (0x1 << 4)
#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
-#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1 << 5)
#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
-#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7 << 6)
#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
-#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */
+#define DMAE_COMMAND_ENDIANITY (0x3 << 9)
#define DMAE_COMMAND_ENDIANITY_SHIFT 9
-#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */
+#define DMAE_COMMAND_PORT (0x1 << 11)
#define DMAE_COMMAND_PORT_SHIFT 11
-#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */
+#define DMAE_COMMAND_CRC_RESET (0x1 << 12)
#define DMAE_COMMAND_CRC_RESET_SHIFT 12
-#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */
+#define DMAE_COMMAND_SRC_RESET (0x1 << 13)
#define DMAE_COMMAND_SRC_RESET_SHIFT 13
-#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */
+#define DMAE_COMMAND_DST_RESET (0x1 << 14)
#define DMAE_COMMAND_DST_RESET_SHIFT 14
-#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */
+#define DMAE_COMMAND_E1HVN (0x3 << 15)
#define DMAE_COMMAND_E1HVN_SHIFT 15
-#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */
+#define DMAE_COMMAND_DST_VN (0x3 << 17)
#define DMAE_COMMAND_DST_VN_SHIFT 17
-#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */
+#define DMAE_COMMAND_C_FUNC (0x1 << 19)
#define DMAE_COMMAND_C_FUNC_SHIFT 19
-#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */
+#define DMAE_COMMAND_ERR_POLICY (0x3 << 20)
#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
-#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */
+#define DMAE_COMMAND_RESERVED0 (0x3FF << 22)
#define DMAE_COMMAND_RESERVED0_SHIFT 22
- uint32_t src_addr_lo /* source address low/grc address */;
- uint32_t src_addr_hi /* source address hi */;
- uint32_t dst_addr_lo /* dest address low/grc address */;
- uint32_t dst_addr_hi /* dest address hi */;
+ uint32_t src_addr_lo;
+ uint32_t src_addr_hi;
+ uint32_t dst_addr_lo;
+ uint32_t dst_addr_hi;
#if defined(__BIG_ENDIAN)
uint16_t opcode_iov;
-#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
+#define DMAE_COMMAND_SRC_VFID (0x3F << 0)
#define DMAE_COMMAND_SRC_VFID_SHIFT 0
-#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
+#define DMAE_COMMAND_SRC_VFPF (0x1 << 6)
#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
-#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED1 (0x1 << 7)
#define DMAE_COMMAND_RESERVED1_SHIFT 7
-#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
+#define DMAE_COMMAND_DST_VFID (0x3F << 8)
#define DMAE_COMMAND_DST_VFID_SHIFT 8
-#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
+#define DMAE_COMMAND_DST_VFPF (0x1 << 14)
#define DMAE_COMMAND_DST_VFPF_SHIFT 14
-#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED2 (0x1 << 15)
#define DMAE_COMMAND_RESERVED2_SHIFT 15
- uint16_t len /* copy length */;
+ uint16_t len;
#elif defined(__LITTLE_ENDIAN)
- uint16_t len /* copy length */;
+ uint16_t len;
uint16_t opcode_iov;
-#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
+#define DMAE_COMMAND_SRC_VFID (0x3F << 0)
#define DMAE_COMMAND_SRC_VFID_SHIFT 0
-#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
+#define DMAE_COMMAND_SRC_VFPF (0x1 << 6)
#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
-#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED1 (0x1 << 7)
#define DMAE_COMMAND_RESERVED1_SHIFT 7
-#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
+#define DMAE_COMMAND_DST_VFID (0x3F << 8)
#define DMAE_COMMAND_DST_VFID_SHIFT 8
-#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
+#define DMAE_COMMAND_DST_VFPF (0x1 << 14)
#define DMAE_COMMAND_DST_VFPF_SHIFT 14
-#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
+#define DMAE_COMMAND_RESERVED2 (0x1 << 15)
#define DMAE_COMMAND_RESERVED2_SHIFT 15
#endif
- uint32_t comp_addr_lo /* completion address low/grc address */;
- uint32_t comp_addr_hi /* completion address hi */;
- uint32_t comp_val /* value to write to completion address */;
- uint32_t crc32 /* crc32 result */;
- uint32_t crc32_c /* crc32_c result */;
+ uint32_t comp_addr_lo;
+ uint32_t comp_addr_hi;
+ uint32_t comp_val;
+ uint32_t crc32;
+ uint32_t crc32_c;
#if defined(__BIG_ENDIAN)
- uint16_t crc16_c /* crc16_c result */;
- uint16_t crc16 /* crc16 result */;
+ uint16_t crc16_c;
+ uint16_t crc16;
#elif defined(__LITTLE_ENDIAN)
- uint16_t crc16 /* crc16 result */;
- uint16_t crc16_c /* crc16_c result */;
+ uint16_t crc16;
+ uint16_t crc16_c;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3;
- uint16_t crc_t10 /* crc_t10 result */;
+ uint16_t crc_t10;
#elif defined(__LITTLE_ENDIAN)
- uint16_t crc_t10 /* crc_t10 result */;
+ uint16_t crc_t10;
uint16_t reserved3;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t xsum8 /* checksum8 result */;
- uint16_t xsum16 /* checksum16 result */;
+ uint16_t xsum8;
+ uint16_t xsum16;
#elif defined(__LITTLE_ENDIAN)
- uint16_t xsum16 /* checksum16 result */;
- uint16_t xsum8 /* checksum8 result */;
+ uint16_t xsum16;
+ uint16_t xsum8;
#endif
};
@@ -3362,162 +3732,149 @@ struct dmae_command
/*
* common data for all protocols
*/
-struct doorbell_hdr
-{
+struct doorbell_hdr {
uint8_t header;
-#define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */
+#define DOORBELL_HDR_RX (0x1 << 0)
#define DOORBELL_HDR_RX_SHIFT 0
-#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */
+#define DOORBELL_HDR_DB_TYPE (0x1 << 1)
#define DOORBELL_HDR_DB_TYPE_SHIFT 1
-#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */
+#define DOORBELL_HDR_DPM_SIZE (0x3 << 2)
#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
-#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */
+#define DOORBELL_HDR_CONN_TYPE (0xF << 4)
#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
};
/*
* Ethernet doorbell
*/
-struct eth_tx_doorbell
-{
+struct eth_tx_doorbell {
#if defined(__BIG_ENDIAN)
- uint16_t npackets /* number of data bytes that were added in the doorbell */;
+ uint16_t npackets;
uint8_t params;
-#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0)
#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
-#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6)
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
-#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
+#define ETH_TX_DOORBELL_SPARE (0x1 << 7)
#define ETH_TX_DOORBELL_SPARE_SHIFT 7
struct doorbell_hdr hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr hdr;
uint8_t params;
-#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0)
#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
-#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6)
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
-#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
+#define ETH_TX_DOORBELL_SPARE (0x1 << 7)
#define ETH_TX_DOORBELL_SPARE_SHIFT 7
- uint16_t npackets /* number of data bytes that were added in the doorbell */;
+ uint16_t npackets;
#endif
};
/*
- * 3 lines. status block $$KEEP_ENDIANNESS$$
+ * 3 lines. status block
*/
-struct hc_status_block_e1x
-{
- uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */;
- uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
- uint32_t rsrv[11];
+struct hc_status_block_e1x {
+ __le16 index_values[HC_SB_MAX_INDICES_E1X];
+ __le16 running_index[HC_SB_MAX_SM];
+ __le32 rsrv[11];
};
/*
* host status block
*/
-struct host_hc_status_block_e1x
-{
- struct hc_status_block_e1x sb /* fast path indices */;
+struct host_hc_status_block_e1x {
+ struct hc_status_block_e1x sb;
};
/*
- * 3 lines. status block $$KEEP_ENDIANNESS$$
+ * 3 lines. status block
*/
-struct hc_status_block_e2
-{
- uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */;
- uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
- uint32_t reserved[11];
+struct hc_status_block_e2 {
+ __le16 index_values[HC_SB_MAX_INDICES_E2];
+ __le16 running_index[HC_SB_MAX_SM];
+ __le32 reserved[11];
};
/*
* host status block
*/
-struct host_hc_status_block_e2
-{
- struct hc_status_block_e2 sb /* fast path indices */;
+struct host_hc_status_block_e2 {
+ struct hc_status_block_e2 sb;
};
/*
- * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$
+ * 5 lines. slow-path status block
*/
-struct hc_sp_status_block
-{
- uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */;
- uint16_t running_index /* Status Block running index */;
- uint16_t rsrv;
+struct hc_sp_status_block {
+ __le16 index_values[HC_SP_SB_MAX_INDICES];
+ __le16 running_index;
+ __le16 rsrv;
uint32_t rsrv1;
};
/*
* host status block
*/
-struct host_sp_status_block
-{
- struct atten_sp_status_block atten_status_block /* attention bits section */;
- struct hc_sp_status_block sp_sb /* slow path indices */;
+struct host_sp_status_block {
+ struct atten_sp_status_block atten_status_block;
+ struct hc_sp_status_block sp_sb;
};
/*
* IGU driver acknowledgment register
*/
-union igu_ack_register
-{
- struct {
+struct igu_ack_register {
#if defined(__BIG_ENDIAN)
- uint16_t sb_id_and_flags;
-#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
+ uint16_t sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0)
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
-#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_ACK_REGISTER_STORM_ID (0x7 << 5)
#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
-#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8)
#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
-#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9)
#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
-#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
+#define IGU_ACK_REGISTER_RESERVED (0x1F << 11)
#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
- uint16_t status_block_index /* status block index acknowledgement */;
+ uint16_t status_block_index;
#elif defined(__LITTLE_ENDIAN)
- uint16_t status_block_index /* status block index acknowledgement */;
- uint16_t sb_id_and_flags;
-#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
+ uint16_t status_block_index;
+ uint16_t sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0)
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
-#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_ACK_REGISTER_STORM_ID (0x7 << 5)
#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
-#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8)
#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
-#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9)
#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
-#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
+#define IGU_ACK_REGISTER_RESERVED (0x1F << 11)
#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
#endif
- } sb;
- uint32_t raw_data;
};
/*
* IGU driver acknowledgement register
*/
-struct igu_backward_compatible
-{
+struct igu_backward_compatible {
uint32_t sb_id_and_flags;
-#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF << 0)
#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
-#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F << 16)
#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
-#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7 << 21)
#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
-#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1 << 24)
#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
-#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3 << 25)
#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
-#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F << 27)
#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
uint32_t reserved_2;
};
@@ -3526,26 +3883,25 @@ struct igu_backward_compatible
/*
* IGU driver acknowledgement register
*/
-struct igu_regular
-{
+struct igu_regular {
uint32_t sb_id_and_flags;
-#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_SB_INDEX (0xFFFFF << 0)
#define IGU_REGULAR_SB_INDEX_SHIFT 0
-#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_RESERVED0 (0x1 << 20)
#define IGU_REGULAR_RESERVED0_SHIFT 20
-#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */
+#define IGU_REGULAR_SEGMENT_ACCESS (0x7 << 21)
#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
-#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_BUPDATE (0x1 << 24)
#define IGU_REGULAR_BUPDATE_SHIFT 24
-#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */
+#define IGU_REGULAR_ENABLE_INT (0x3 << 25)
#define IGU_REGULAR_ENABLE_INT_SHIFT 25
-#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_RESERVED_1 (0x1 << 27)
#define IGU_REGULAR_RESERVED_1_SHIFT 27
-#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_CLEANUP_TYPE (0x3 << 28)
#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
-#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_CLEANUP_SET (0x1 << 30)
#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
-#define IGU_REGULAR_BCLEANUP (0x1U<<31) /* BitField sb_id_and_flags */
+#define IGU_REGULAR_BCLEANUP (0x1 << 31)
#define IGU_REGULAR_BCLEANUP_SHIFT 31
uint32_t reserved_2;
};
@@ -3553,8 +3909,7 @@ struct igu_regular
/*
* IGU driver acknowledgement register
*/
-union igu_consprod_reg
-{
+union igu_consprod_reg {
struct igu_regular regular;
struct igu_backward_compatible backward_compatible;
};
@@ -3563,8 +3918,7 @@ union igu_consprod_reg
/*
* Igu control commands
*/
-enum igu_ctrl_cmd
-{
+enum igu_ctrl_cmd {
IGU_CTRL_CMD_TYPE_RD,
IGU_CTRL_CMD_TYPE_WR,
MAX_IGU_CTRL_CMD};
@@ -3573,18 +3927,17 @@ enum igu_ctrl_cmd
/*
* Control register for the IGU command register
*/
-struct igu_ctrl_reg
-{
+struct igu_ctrl_reg {
uint32_t ctrl_data;
-#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */
+#define IGU_CTRL_REG_ADDRESS (0xFFF << 0)
#define IGU_CTRL_REG_ADDRESS_SHIFT 0
-#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */
+#define IGU_CTRL_REG_FID (0x7F << 12)
#define IGU_CTRL_REG_FID_SHIFT 12
-#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */
+#define IGU_CTRL_REG_RESERVED (0x1 << 19)
#define IGU_CTRL_REG_RESERVED_SHIFT 19
-#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */
+#define IGU_CTRL_REG_TYPE (0x1 << 20)
#define IGU_CTRL_REG_TYPE_SHIFT 20
-#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */
+#define IGU_CTRL_REG_UNUSED (0x7FF << 21)
#define IGU_CTRL_REG_UNUSED_SHIFT 21
};
@@ -3592,8 +3945,7 @@ struct igu_ctrl_reg
/*
* Igu interrupt command
*/
-enum igu_int_cmd
-{
+enum igu_int_cmd {
IGU_INT_ENABLE,
IGU_INT_DISABLE,
IGU_INT_NOP,
@@ -3604,8 +3956,7 @@ enum igu_int_cmd
/*
* Igu segments
*/
-enum igu_seg_access
-{
+enum igu_seg_access {
IGU_SEG_ACCESS_NORM,
IGU_SEG_ACCESS_DEF,
IGU_SEG_ACCESS_ATTN,
@@ -3615,34 +3966,33 @@ enum igu_seg_access
/*
* Parser parsing flags field
*/
-struct parsing_flags
-{
- uint16_t flags;
-#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */
+struct parsing_flags {
+ __le16 flags;
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1 << 0)
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
-#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */
+#define PARSING_FLAGS_VLAN (0x1 << 1)
#define PARSING_FLAGS_VLAN_SHIFT 1
-#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */
+#define PARSING_FLAGS_EXTRA_VLAN (0x1 << 2)
#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
-#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3 << 3)
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
-#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */
+#define PARSING_FLAGS_IP_OPTIONS (0x1 << 5)
#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
-#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */
+#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1 << 6)
#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
-#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */
+#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3 << 7)
#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
-#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */
+#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1 << 9)
#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
-#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1 << 10)
#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
-#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1 << 11)
#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
-#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */
+#define PARSING_FLAGS_CONNECTION_MATCH (0x1 << 12)
#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
-#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */
+#define PARSING_FLAGS_LLC_SNAP (0x1 << 13)
#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
-#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */
+#define PARSING_FLAGS_RESERVED0 (0x3 << 14)
#define PARSING_FLAGS_RESERVED0_SHIFT 14
};
@@ -3650,8 +4000,7 @@ struct parsing_flags
/*
* Parsing flags for TCP ACK type
*/
-enum prs_flags_ack_type
-{
+enum prs_flags_ack_type {
PRS_FLAG_PUREACK_PIGGY,
PRS_FLAG_PUREACK_PURE,
MAX_PRS_FLAGS_ACK_TYPE};
@@ -3660,8 +4009,7 @@ enum prs_flags_ack_type
/*
* Parsing flags for Ethernet address type
*/
-enum prs_flags_eth_addr_type
-{
+enum prs_flags_eth_addr_type {
PRS_FLAG_ETHTYPE_NON_UNICAST,
PRS_FLAG_ETHTYPE_UNICAST,
MAX_PRS_FLAGS_ETH_ADDR_TYPE};
@@ -3670,8 +4018,7 @@ enum prs_flags_eth_addr_type
/*
* Parsing flags for over-ethernet protocol
*/
-enum prs_flags_over_eth
-{
+enum prs_flags_over_eth {
PRS_FLAG_OVERETH_UNKNOWN,
PRS_FLAG_OVERETH_IPV4,
PRS_FLAG_OVERETH_IPV6,
@@ -3682,8 +4029,7 @@ enum prs_flags_over_eth
/*
* Parsing flags for over-IP protocol
*/
-enum prs_flags_over_ip
-{
+enum prs_flags_over_ip {
PRS_FLAG_OVERIP_UNKNOWN,
PRS_FLAG_OVERIP_TCP,
PRS_FLAG_OVERIP_UDP,
@@ -3693,18 +4039,17 @@ enum prs_flags_over_ip
/*
* SDM operation gen command (generate aggregative interrupt)
*/
-struct sdm_op_gen
-{
- uint32_t command;
-#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */
+struct sdm_op_gen {
+ __le32 command;
+#define SDM_OP_GEN_COMP_PARAM (0x1F << 0)
#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
-#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */
+#define SDM_OP_GEN_COMP_TYPE (0x7 << 5)
#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
-#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */
+#define SDM_OP_GEN_AGG_VECT_IDX (0xFF << 8)
#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
-#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */
+#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1 << 16)
#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
-#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */
+#define SDM_OP_GEN_RESERVED (0x7FFF << 17)
#define SDM_OP_GEN_RESERVED_SHIFT 17
};
@@ -3712,17 +4057,16 @@ struct sdm_op_gen
/*
* Timers connection context
*/
-struct timers_block_context
-{
- uint32_t __reserved_0 /* data of client 0 of the timers block*/;
- uint32_t __reserved_1 /* data of client 1 of the timers block*/;
- uint32_t __reserved_2 /* data of client 2 of the timers block*/;
+struct timers_block_context {
+ uint32_t __reserved_0;
+ uint32_t __reserved_1;
+ uint32_t __reserved_2;
uint32_t flags;
-#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */
+#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3 << 0)
#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
-#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */
+#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1 << 2)
#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
-#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */
+#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF << 3)
#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
};
@@ -3730,8 +4074,7 @@ struct timers_block_context
/*
* The eth aggregative context of Tstorm
*/
-struct tstorm_eth_ag_context
-{
+struct tstorm_eth_ag_context {
uint32_t __reserved0[14];
};
@@ -3739,17 +4082,16 @@ struct tstorm_eth_ag_context
/*
* The eth aggregative context of Ustorm
*/
-struct ustorm_eth_ag_context
-{
+struct ustorm_eth_ag_context {
uint32_t __reserved0;
#if defined(__BIG_ENDIAN)
- uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
+ uint8_t cdu_usage;
uint8_t __reserved2;
uint16_t __reserved1;
#elif defined(__LITTLE_ENDIAN)
uint16_t __reserved1;
uint8_t __reserved2;
- uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
+ uint8_t cdu_usage;
#endif
uint32_t __reserved3[6];
};
@@ -3758,17 +4100,16 @@ struct ustorm_eth_ag_context
/*
* The eth aggregative context of Xstorm
*/
-struct xstorm_eth_ag_context
-{
+struct xstorm_eth_ag_context {
uint32_t reserved0;
#if defined(__BIG_ENDIAN)
- uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
+ uint8_t cdu_reserved;
uint8_t reserved2;
uint16_t reserved1;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved1;
uint8_t reserved2;
- uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
+ uint8_t cdu_reserved;
#endif
uint32_t reserved3[30];
};
@@ -3777,16 +4118,15 @@ struct xstorm_eth_ag_context
/*
* doorbell message sent to the chip
*/
-struct doorbell
-{
+struct doorbell {
#if defined(__BIG_ENDIAN)
- uint16_t zero_fill2 /* driver must zero this field! */;
- uint8_t zero_fill1 /* driver must zero this field! */;
+ uint16_t zero_fill2;
+ uint8_t zero_fill1;
struct doorbell_hdr header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr header;
- uint8_t zero_fill1 /* driver must zero this field! */;
- uint16_t zero_fill2 /* driver must zero this field! */;
+ uint8_t zero_fill1;
+ uint16_t zero_fill2;
#endif
};
@@ -3794,527 +4134,563 @@ struct doorbell
/*
* doorbell message sent to the chip
*/
-struct doorbell_set_prod
-{
+struct doorbell_set_prod {
#if defined(__BIG_ENDIAN)
- uint16_t prod /* Producer index to be set */;
- uint8_t zero_fill1 /* driver must zero this field! */;
+ uint16_t prod;
+ uint8_t zero_fill1;
struct doorbell_hdr header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr header;
- uint8_t zero_fill1 /* driver must zero this field! */;
- uint16_t prod /* Producer index to be set */;
+ uint8_t zero_fill1;
+ uint16_t prod;
#endif
};
-struct regpair
-{
- uint32_t lo /* low word for reg-pair */;
- uint32_t hi /* high word for reg-pair */;
+struct regpair {
+ __le32 lo;
+ __le32 hi;
};
-struct regpair_native
-{
- uint32_t lo /* low word for reg-pair */;
- uint32_t hi /* high word for reg-pair */;
+struct regpair_native {
+ uint32_t lo;
+ uint32_t hi;
};
/*
* Classify rule opcodes in E2/E3
*/
-enum classify_rule
-{
- CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */,
- CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */,
- CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */,
+enum classify_rule {
+ CLASSIFY_RULE_OPCODE_MAC,
+ CLASSIFY_RULE_OPCODE_VLAN,
+ CLASSIFY_RULE_OPCODE_PAIR,
+ CLASSIFY_RULE_OPCODE_IMAC_VNI,
MAX_CLASSIFY_RULE};
/*
* Classify rule types in E2/E3
*/
-enum classify_rule_action_type
-{
+enum classify_rule_action_type {
CLASSIFY_RULE_REMOVE,
CLASSIFY_RULE_ADD,
MAX_CLASSIFY_RULE_ACTION_TYPE};
/*
- * client init ramrod data $$KEEP_ENDIANNESS$$
+ * client init ramrod data
*/
-struct client_init_general_data
-{
- uint8_t client_id /* client_id */;
- uint8_t statistics_counter_id /* statistics counter id */;
- uint8_t statistics_en_flg /* statistics en flg */;
- uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */;
- uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
- uint8_t sp_client_id /* the slow path rings client Id. */;
- uint16_t mtu /* Host MTU from client config */;
- uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */;
- uint8_t func_id /* PCI function ID (0-71) */;
- uint8_t cos /* The connection cos, if applicable */;
+struct client_init_general_data {
+ uint8_t client_id;
+ uint8_t statistics_counter_id;
+ uint8_t statistics_en_flg;
+ uint8_t is_fcoe_flg;
+ uint8_t activate_flg;
+ uint8_t sp_client_id;
+ __le16 mtu;
+ uint8_t statistics_zero_flg;
+ uint8_t func_id;
+ uint8_t cos;
uint8_t traffic_type;
- uint32_t reserved0;
+ uint8_t fp_hsi_ver;
+ uint8_t reserved0[3];
};
/*
- * client init rx data $$KEEP_ENDIANNESS$$
+ * client init rx data
*/
-struct client_init_rx_data
-{
+struct client_init_rx_data {
uint8_t tpa_en;
-#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1 << 0)
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
-#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1 << 1)
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
-#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */
+#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1 << 2)
#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
-#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */
-#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
- uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */;
- uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */;
- uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */;
- uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */;
- uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
- uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */;
- uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */;
- uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */;
- uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;
- uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */;
- uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */;
- uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */;
- uint8_t status_block_id /* rx status block id */;
- uint8_t rx_sb_index_number /* status block indices */;
- uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
- uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
- uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
- uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */;
- uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
- uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */;
- uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */;
- struct regpair bd_page_base /* BD page base address at the host */;
- struct regpair sge_page_base /* SGE page base address at the host */;
- struct regpair cqe_page_base /* Completion queue base address */;
+#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE (0x1 << 3)
+#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE_SHIFT 3
+#define CLIENT_INIT_RX_DATA_RESERVED5 (0xF << 4)
+#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 4
+ uint8_t vmqueue_mode_en_flg;
+ uint8_t extra_data_over_sgl_en_flg;
+ uint8_t cache_line_alignment_log_size;
+ uint8_t enable_dynamic_hc;
+ uint8_t max_sges_for_packet;
+ uint8_t client_qzone_id;
+ uint8_t drop_ip_cs_err_flg;
+ uint8_t drop_tcp_cs_err_flg;
+ uint8_t drop_ttl0_flg;
+ uint8_t drop_udp_cs_err_flg;
+ uint8_t inner_vlan_removal_enable_flg;
+ uint8_t outer_vlan_removal_enable_flg;
+ uint8_t status_block_id;
+ uint8_t rx_sb_index_number;
+ uint8_t dont_verify_rings_pause_thr_flg;
+ uint8_t max_tpa_queues;
+ uint8_t silent_vlan_removal_flg;
+ __le16 max_bytes_on_bd;
+ __le16 sge_buff_size;
+ uint8_t approx_mcast_engine_id;
+ uint8_t rss_engine_id;
+ struct regpair bd_page_base;
+ struct regpair sge_page_base;
+ struct regpair cqe_page_base;
uint8_t is_leading_rss;
uint8_t is_approx_mcast;
- uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
- uint16_t state;
-#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */
+ __le16 max_agg_size;
+ __le16 state;
+#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1 << 0)
#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
-#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1 << 1)
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
-#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1 << 2)
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
-#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */
+#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1 << 3)
#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
-#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1 << 4)
#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
-#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1 << 5)
#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
-#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */
+#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1 << 6)
#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
-#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */
+#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF << 7)
#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
- uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */;
- uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */;
- uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */;
- uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */;
- uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
- uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
- uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket with will be genratet when this ring is full. for regular flow control set this to 1 */;
- uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
- uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
- uint32_t reserved6[2];
-};
-
-/*
- * client init tx data $$KEEP_ENDIANNESS$$
- */
-struct client_init_tx_data
-{
- uint8_t enforce_security_flg /* if set, security checks will be made for this connection */;
- uint8_t tx_status_block_id /* the number of status block to update */;
- uint8_t tx_sb_index_number /* the index to use inside the status block */;
- uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */;
- uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */;
- uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */;
- uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
- struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */;
- uint16_t state;
-#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */
+ __le16 cqe_pause_thr_low;
+ __le16 cqe_pause_thr_high;
+ __le16 bd_pause_thr_low;
+ __le16 bd_pause_thr_high;
+ __le16 sge_pause_thr_low;
+ __le16 sge_pause_thr_high;
+ __le16 rx_cos_mask;
+ __le16 silent_vlan_value;
+ __le16 silent_vlan_mask;
+ uint8_t handle_ptp_pkts_flg;
+ uint8_t reserved6[3];
+ __le32 reserved7;
+};
+
+/*
+ * client init tx data
+ */
+struct client_init_tx_data {
+ uint8_t enforce_security_flg;
+ uint8_t tx_status_block_id;
+ uint8_t tx_sb_index_number;
+ uint8_t tss_leading_client_id;
+ uint8_t tx_switching_flg;
+ uint8_t anti_spoofing_flg;
+ __le16 default_vlan;
+ struct regpair tx_bd_page_base;
+ __le16 state;
+#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1 << 0)
#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
-#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1 << 1)
#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
-#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1 << 2)
#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
-#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */
+#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1 << 3)
#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
-#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */
+#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF << 4)
#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
- uint8_t default_vlan_flg /* is default vlan valid for this client. */;
- uint8_t force_default_pri_flg /* if set, force default priority */;
- uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */;
- uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */;
- uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */;
- uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */;
+ uint8_t default_vlan_flg;
+ uint8_t force_default_pri_flg;
+ uint8_t tunnel_lso_inc_ip_id;
+ uint8_t refuse_outband_vlan_flg;
+ uint8_t tunnel_non_lso_pcsum_location;
+ uint8_t tunnel_non_lso_outer_ip_csum_location;
};
/*
- * client init ramrod data $$KEEP_ENDIANNESS$$
+ * client init ramrod data
*/
-struct client_init_ramrod_data
-{
- struct client_init_general_data general /* client init general data */;
- struct client_init_rx_data rx /* client init rx data */;
- struct client_init_tx_data tx /* client init tx data */;
+struct client_init_ramrod_data {
+ struct client_init_general_data general;
+ struct client_init_rx_data rx;
+ struct client_init_tx_data tx;
};
/*
- * client update ramrod data $$KEEP_ENDIANNESS$$
+ * client update ramrod data
*/
-struct client_update_ramrod_data
-{
- uint8_t client_id /* the client to update */;
- uint8_t func_id /* PCI function ID this client belongs to (0-71) */;
- uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */;
- uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */;
- uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */;
- uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */;
- uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */;
- uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */;
- uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
- uint8_t activate_change_flg /* If set, activate_flg will be checked */;
- uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
+struct client_update_ramrod_data {
+ uint8_t client_id;
+ uint8_t func_id;
+ uint8_t inner_vlan_removal_enable_flg;
+ uint8_t inner_vlan_removal_change_flg;
+ uint8_t outer_vlan_removal_enable_flg;
+ uint8_t outer_vlan_removal_change_flg;
+ uint8_t anti_spoofing_enable_flg;
+ uint8_t anti_spoofing_change_flg;
+ uint8_t activate_flg;
+ uint8_t activate_change_flg;
+ __le16 default_vlan;
uint8_t default_vlan_enable_flg;
uint8_t default_vlan_change_flg;
- uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
- uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
- uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
+ __le16 silent_vlan_value;
+ __le16 silent_vlan_mask;
+ uint8_t silent_vlan_removal_flg;
uint8_t silent_vlan_change_flg;
- uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */;
- uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */;
- uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */;
- uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */;
- uint32_t reserved1;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+ uint8_t refuse_outband_vlan_flg;
+ uint8_t refuse_outband_vlan_change_flg;
+ uint8_t tx_switching_flg;
+ uint8_t tx_switching_change_flg;
+ uint8_t handle_ptp_pkts_flg;
+ uint8_t handle_ptp_pkts_change_flg;
+ __le16 reserved1;
+ __le32 echo;
};
/*
* The eth storm context of Cstorm
*/
-struct cstorm_eth_st_context
-{
+struct cstorm_eth_st_context {
uint32_t __reserved0[4];
};
-struct double_regpair
-{
- uint32_t regpair0_lo /* low word for reg-pair0 */;
- uint32_t regpair0_hi /* high word for reg-pair0 */;
- uint32_t regpair1_lo /* low word for reg-pair1 */;
- uint32_t regpair1_hi /* high word for reg-pair1 */;
+struct double_regpair {
+ uint32_t regpair0_lo;
+ uint32_t regpair0_hi;
+ uint32_t regpair1_lo;
+ uint32_t regpair1_hi;
};
/*
- * Ethernet address types used in ethernet tx BDs
+ * 2nd parse bd type used in ethernet tx BDs
+ */
+enum eth_2nd_parse_bd_type {
+ ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
+ MAX_ETH_2ND_PARSE_BD_TYPE};
+
+
+/*
+ * Ethernet address typesm used in ethernet tx BDs
*/
-enum eth_addr_type
-{
+enum eth_addr_type {
UNKNOWN_ADDRESS,
UNICAST_ADDRESS,
MULTICAST_ADDRESS,
BROADCAST_ADDRESS,
- MAX_ETH_ADDR_TYPE
-};
+ MAX_ETH_ADDR_TYPE};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct eth_classify_cmd_header
-{
+struct eth_classify_cmd_header {
uint8_t cmd_general_data;
-#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1 << 0)
#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
-#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1 << 1)
#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
-#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */
+#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3 << 2)
#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
-#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */
+#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1 << 4)
#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
-#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */
+#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7 << 5)
#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
- uint8_t func_id /* the function id */;
+ uint8_t func_id;
uint8_t client_id;
uint8_t reserved1;
};
/*
- * header for eth classification config ramrod $$KEEP_ENDIANNESS$$
+ * header for eth classification config ramrod
*/
-struct eth_classify_header
-{
- uint8_t rule_cnt /* number of rules in classification config ramrod */;
- uint8_t reserved0;
- uint16_t reserved1;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+struct eth_classify_header {
+ uint8_t rule_cnt;
+ uint8_t warning_on_error;
+ __le16 reserved1;
+ __le32 echo;
};
/*
- * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a Inner-MAC/VNI classification rule
*/
-struct eth_classify_mac_cmd
-{
+struct eth_classify_imac_vni_cmd {
struct eth_classify_cmd_header header;
- uint16_t reserved0;
- uint16_t inner_mac;
- uint16_t mac_lsb;
- uint16_t mac_mid;
- uint16_t mac_msb;
- uint16_t reserved1;
+ __le32 vni;
+ __le16 imac_lsb;
+ __le16 imac_mid;
+ __le16 imac_msb;
+ __le16 reserved1;
};
/*
- * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a MAC classification rule
*/
-struct eth_classify_pair_cmd
-{
+struct eth_classify_mac_cmd {
struct eth_classify_cmd_header header;
- uint16_t reserved0;
- uint16_t inner_mac;
- uint16_t mac_lsb;
- uint16_t mac_mid;
- uint16_t mac_msb;
- uint16_t vlan;
+ __le16 reserved0;
+ __le16 inner_mac;
+ __le16 mac_lsb;
+ __le16 mac_mid;
+ __le16 mac_msb;
+ __le16 reserved1;
};
/*
- * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$
+ * Command for adding/removing a MAC-VLAN pair classification rule
*/
-struct eth_classify_vlan_cmd
-{
+struct eth_classify_pair_cmd {
struct eth_classify_cmd_header header;
- uint32_t reserved0;
- uint32_t reserved1;
- uint16_t reserved2;
- uint16_t vlan;
+ __le16 reserved0;
+ __le16 inner_mac;
+ __le16 mac_lsb;
+ __le16 mac_mid;
+ __le16 mac_msb;
+ __le16 vlan;
+};
+
+
+/*
+ * Command for adding/removing a VLAN classification rule
+ */
+struct eth_classify_vlan_cmd {
+ struct eth_classify_cmd_header header;
+ __le32 reserved0;
+ __le32 reserved1;
+ __le16 reserved2;
+ __le16 vlan;
};
/*
- * union for eth classification rule $$KEEP_ENDIANNESS$$
+ * union for eth classification rule
*/
-union eth_classify_rule_cmd
-{
+union eth_classify_rule_cmd {
struct eth_classify_mac_cmd mac;
struct eth_classify_vlan_cmd vlan;
struct eth_classify_pair_cmd pair;
+ struct eth_classify_imac_vni_cmd imac_vni;
};
/*
- * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
+ * parameters for eth classification configuration ramrod
*/
-struct eth_classify_rules_ramrod_data
-{
+struct eth_classify_rules_ramrod_data {
struct eth_classify_header header;
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
};
/*
- * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$
+ * The data contain client ID need to the ramrod
*/
-struct eth_common_ramrod_data
-{
- uint32_t client_id /* id of this client. (5 bits are used) */;
- uint32_t reserved1;
+struct eth_common_ramrod_data {
+ __le32 client_id;
+ __le32 reserved1;
};
/*
* The eth storm context of Ustorm
*/
-struct ustorm_eth_st_context
-{
+struct ustorm_eth_st_context {
uint32_t reserved0[52];
};
/*
* The eth storm context of Tstorm
*/
-struct tstorm_eth_st_context
-{
+struct tstorm_eth_st_context {
uint32_t __reserved0[28];
};
/*
* The eth storm context of Xstorm
*/
-struct xstorm_eth_st_context
-{
+struct xstorm_eth_st_context {
uint32_t reserved0[60];
};
/*
* Ethernet connection context
*/
-struct eth_context
-{
- struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */;
- struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */;
- struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */;
- struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */;
- struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */;
- struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */;
- struct timers_block_context timers_context /* Timers block context */;
- struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */;
- struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */;
+struct eth_context {
+ struct ustorm_eth_st_context ustorm_st_context;
+ struct tstorm_eth_st_context tstorm_st_context;
+ struct xstorm_eth_ag_context xstorm_ag_context;
+ struct tstorm_eth_ag_context tstorm_ag_context;
+ struct cstorm_eth_ag_context cstorm_ag_context;
+ struct ustorm_eth_ag_context ustorm_ag_context;
+ struct timers_block_context timers_context;
+ struct xstorm_eth_st_context xstorm_st_context;
+ struct cstorm_eth_st_context cstorm_st_context;
};
/*
* union for sgl and raw data.
*/
-union eth_sgl_or_raw_data
-{
- uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */;
- uint32_t raw_data[4] /* raw data from Tstorm to the driver. */;
+union eth_sgl_or_raw_data {
+ __le16 sgl[8];
+ uint32_t raw_data[4];
};
/*
- * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$
+ * eth FP end aggregation CQE parameters struct
*/
-struct eth_end_agg_rx_cqe
-{
+struct eth_end_agg_rx_cqe {
uint8_t type_error_flags;
-#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
+#define ETH_END_AGG_RX_CQE_TYPE (0x3 << 0)
#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
-#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
+#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1 << 2)
#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
-#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */
+#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F << 3)
#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
uint8_t reserved1;
- uint8_t queue_index /* The aggregation queue index of this packet */;
+ uint8_t queue_index;
uint8_t reserved2;
- uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */;
- uint16_t num_of_coalesced_segs /* Num of coalesced segments. */;
- uint16_t pkt_len /* Packet length */;
- uint8_t pure_ack_count /* Number of pure acks coalesced. */;
+ __le32 timestamp_delta;
+ __le16 num_of_coalesced_segs;
+ __le16 pkt_len;
+ uint8_t pure_ack_count;
uint8_t reserved3;
- uint16_t reserved4;
- union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
- uint32_t reserved5[8];
+ __le16 reserved4;
+ union eth_sgl_or_raw_data sgl_or_raw_data;
+ __le32 padding[8];
};
+/*
+ * Ethernet error code
+ */
+enum eth_error_code {
+ ETH_OK = 0x00,
+ ETH_RAMROD_DATA_READ_ERROR = 0x01,
+ ETH_FILTERS_FUNC_NOT_ENABLED,
+ ETH_FILTERS_MAC_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_MAC_DEL_FAIL_NOF,
+ ETH_FILTERS_PAIR_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_PAIR_DEL_FAIL_NOF,
+ ETH_FILTERS_VLAN_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_VLAN_ADD_FAIL_DUP_TT,
+ ETH_FILTERS_VLAN_DEL_FAIL_NOF,
+ ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT,
+ ETH_FILTERS_VLAN_DEL_FAIL_NO_VLAN,
+ ETH_FILTERS_IMAC_VNI_ADD_UNALLOWED_IN_TX,
+ ETH_FILTERS_IMAC_VNI_DEL_UNALLOWED_IN_TX,
+ ETH_FILTERS_IMAC_VNI_ADD_FAIL_CAM_FULL,
+ ETH_FILTERS_IMAC_VNI_DEL_FAIL_NOF,
+ MAX_ETH_ERROR_CODE};
/*
- * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$
+ * regular eth FP CQE parameters struct
*/
-struct eth_fast_path_rx_cqe
-{
+struct eth_fast_path_rx_cqe {
uint8_t type_error_flags;
-#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
+#define ETH_FAST_PATH_RX_CQE_TYPE (0x3 << 0)
#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
+#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1 << 2)
#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
-#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1 << 3)
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
-#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1 << 4)
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
-#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1 << 5)
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
-#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */
-#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1 << 6)
+#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1 << 7)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
uint8_t status_flags;
-#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7 << 0)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1 << 3)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
-#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1 << 4)
#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
-#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1 << 5)
#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
-#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1 << 6)
#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
-#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1 << 7)
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
- uint8_t queue_index /* The aggregation queue index of this packet */;
- uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */;
- uint32_t rss_hash_result /* RSS toeplitz hash result */;
- uint16_t vlan_tag /* Ethernet VLAN tag field */;
- uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;
- uint16_t len_on_bd /* Number of bytes placed on the BD */;
+ uint8_t queue_index;
+ uint8_t placement_offset;
+ __le32 rss_hash_result;
+ __le16 vlan_tag;
+ __le16 pkt_len_or_gro_seg_len;
+ __le16 len_on_bd;
struct parsing_flags pars_flags;
- union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
- uint32_t reserved1[8];
+ union eth_sgl_or_raw_data sgl_or_raw_data;
+ uint8_t tunn_type;
+ uint8_t tunn_inner_hdrs_offset;
+ __le16 reserved1;
+ __le32 tunn_tenant_id;
+ __le32 padding[5];
+ __le32 marker;
};
/*
- * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$
+ * Command for setting classification flags for a client
*/
-struct eth_filter_rules_cmd
-{
+struct eth_filter_rules_cmd {
uint8_t cmd_general_data;
-#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_FILTER_RULES_CMD_RX_CMD (0x1 << 0)
#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
-#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_FILTER_RULES_CMD_TX_CMD (0x1 << 1)
#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
-#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */
+#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F << 2)
#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
- uint8_t func_id /* the function id */;
- uint8_t client_id /* the client id */;
+ uint8_t func_id;
+ uint8_t client_id;
uint8_t reserved1;
- uint16_t state;
-#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */
+ __le16 state;
+#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1 << 0)
#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
-#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1 << 1)
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
-#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1 << 2)
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
-#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */
+#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1 << 3)
#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
-#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1 << 4)
#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
-#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1 << 5)
#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
-#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */
+#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1 << 6)
#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
-#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */
+#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF << 7)
#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
- uint16_t reserved3;
+ __le16 reserved3;
struct regpair reserved4;
};
/*
- * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$
+ * parameters for eth classification filters ramrod
*/
-struct eth_filter_rules_ramrod_data
-{
+struct eth_filter_rules_ramrod_data {
struct eth_classify_header header;
struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
};
/*
- * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
+ * Hsi version
+ */
+enum eth_fp_hsi_ver {
+ ETH_FP_HSI_VER_0,
+ ETH_FP_HSI_VER_1,
+ ETH_FP_HSI_VER_2,
+ MAX_ETH_FP_HSI_VER};
+
+
+/*
+ * parameters for eth classification configuration ramrod
*/
-struct eth_general_rules_ramrod_data
-{
+struct eth_general_rules_ramrod_data {
struct eth_classify_header header;
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
};
@@ -4323,38 +4699,36 @@ struct eth_general_rules_ramrod_data
/*
* The data for Halt ramrod
*/
-struct eth_halt_ramrod_data
-{
- uint32_t client_id /* id of this client. (5 bits are used) */;
- uint32_t reserved0;
+struct eth_halt_ramrod_data {
+ __le32 client_id;
+ __le32 reserved0;
};
/*
* destination and source mac address.
*/
-struct eth_mac_addresses
-{
+struct eth_mac_addresses {
#if defined(__BIG_ENDIAN)
- uint16_t dst_mid /* destination mac address 16 middle bits */;
- uint16_t dst_lo /* destination mac address 16 low bits */;
+ __le16 dst_mid;
+ __le16 dst_lo;
#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_lo /* destination mac address 16 low bits */;
- uint16_t dst_mid /* destination mac address 16 middle bits */;
+ __le16 dst_lo;
+ __le16 dst_mid;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t src_lo /* source mac address 16 low bits */;
- uint16_t dst_hi /* destination mac address 16 high bits */;
+ __le16 src_lo;
+ __le16 dst_hi;
#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_hi /* destination mac address 16 high bits */;
- uint16_t src_lo /* source mac address 16 low bits */;
+ __le16 dst_hi;
+ __le16 src_lo;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t src_hi /* source mac address 16 high bits */;
- uint16_t src_mid /* source mac address 16 middle bits */;
+ __le16 src_hi;
+ __le16 src_mid;
#elif defined(__LITTLE_ENDIAN)
- uint16_t src_mid /* source mac address 16 middle bits */;
- uint16_t src_hi /* source mac address 16 high bits */;
+ __le16 src_mid;
+ __le16 src_hi;
#endif
};
@@ -4362,78 +4736,54 @@ struct eth_mac_addresses
/*
* tunneling related data.
*/
-struct eth_tunnel_data
-{
-#if defined(__BIG_ENDIAN)
- uint16_t dst_mid /* destination mac address 16 middle bits */;
- uint16_t dst_lo /* destination mac address 16 low bits */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_lo /* destination mac address 16 low bits */;
- uint16_t dst_mid /* destination mac address 16 middle bits */;
-#endif
-#if defined(__BIG_ENDIAN)
- uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
- uint16_t dst_hi /* destination mac address 16 high bits */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t dst_hi /* destination mac address 16 high bits */;
- uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
-#endif
-#if defined(__BIG_ENDIAN)
+struct eth_tunnel_data {
+ __le16 dst_lo;
+ __le16 dst_mid;
+ __le16 dst_hi;
+ __le16 fw_ip_hdr_csum;
+ __le16 pseudo_csum;
+ uint8_t ip_hdr_start_inner_w;
uint8_t flags;
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
-#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
+#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1 << 0)
+#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
+#define ETH_TUNNEL_DATA_RESERVED (0x7F << 1)
#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
- uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
- uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
-#elif defined(__LITTLE_ENDIAN)
- uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
- uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
- uint8_t flags;
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
-#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
-#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
-#endif
};
/*
* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1).
*/
-union eth_mac_addr_or_tunnel_data
-{
- struct eth_mac_addresses mac_addr /* destination and source mac addresses. */;
- struct eth_tunnel_data tunnel_data /* tunneling related data. */;
+union eth_mac_addr_or_tunnel_data {
+ struct eth_mac_addresses mac_addr;
+ struct eth_tunnel_data tunnel_data;
};
/*
- * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$
+ * Command for setting multicast classification for a client
*/
-struct eth_multicast_rules_cmd
-{
+struct eth_multicast_rules_cmd {
uint8_t cmd_general_data;
-#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
+#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1 << 0)
#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
-#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
+#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1 << 1)
#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
-#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */
+#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1 << 2)
#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
-#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */
+#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F << 3)
#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
- uint8_t func_id /* the function id */;
- uint8_t bin_id /* the bin to add this function to (0-255) */;
- uint8_t engine_id /* the approximate multicast engine id */;
- uint32_t reserved2;
+ uint8_t func_id;
+ uint8_t bin_id;
+ uint8_t engine_id;
+ __le32 reserved2;
struct regpair reserved3;
};
/*
- * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$
+ * parameters for multicast classification ramrod
*/
-struct eth_multicast_rules_ramrod_data
-{
+struct eth_multicast_rules_ramrod_data {
struct eth_classify_header header;
struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
};
@@ -4442,17 +4792,15 @@ struct eth_multicast_rules_ramrod_data
/*
* Place holder for ramrods protocol specific data
*/
-struct ramrod_data
-{
- uint32_t data_lo;
- uint32_t data_hi;
+struct ramrod_data {
+ __le32 data_lo;
+ __le32 data_hi;
};
/*
* union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
*/
-union eth_ramrod_data
-{
+union eth_ramrod_data {
struct ramrod_data general;
};
@@ -4460,8 +4808,7 @@ union eth_ramrod_data
/*
* RSS toeplitz hash type, as reported in CQE
*/
-enum eth_rss_hash_type
-{
+enum eth_rss_hash_type {
DEFAULT_HASH_TYPE,
IPV4_HASH_TYPE,
TCP_IPV4_HASH_TYPE,
@@ -4476,100 +4823,100 @@ enum eth_rss_hash_type
/*
* Ethernet RSS mode
*/
-enum eth_rss_mode
-{
+enum eth_rss_mode {
ETH_RSS_MODE_DISABLED,
- ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */,
- ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
- ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */,
- ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */,
- ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */,
+ ETH_RSS_MODE_REGULAR,
+ ETH_RSS_MODE_ESX51,
+ ETH_RSS_MODE_VLAN_PRI,
+ ETH_RSS_MODE_E1HOV_PRI,
+ ETH_RSS_MODE_IP_DSCP,
MAX_ETH_RSS_MODE};
/*
- * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$
+ * parameters for RSS update ramrod (E2)
*/
-struct eth_rss_update_ramrod_data
-{
+struct eth_rss_update_ramrod_data {
uint8_t rss_engine_id;
- uint8_t capabilities;
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */
+ uint8_t rss_mode;
+ __le16 capabilities;
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1 << 0)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1 << 1)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1 << 2)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */
-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
- uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
- uint8_t rss_mode /* The RSS mode for this function */;
- uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
- uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
- uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */;
- uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */;
- uint32_t echo;
- uint32_t reserved3;
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1 << 3)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1 << 4)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1 << 5)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1 << 6)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1 << 7)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
+#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1 << 8)
+#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1 << 9)
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F << 10)
+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
+ uint8_t rss_result_mask;
+ uint8_t reserved3;
+ __le16 reserved4;
+ uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
+ __le32 rss_key[T_ETH_RSS_KEY];
+ __le32 echo;
+ __le32 reserved5;
};
/*
* The eth Rx Buffer Descriptor
*/
-struct eth_rx_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
+struct eth_rx_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
};
/*
- * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$
+ * Eth Rx Cqe structure- general structure for ramrods
*/
-struct common_ramrod_eth_rx_cqe
-{
+struct common_ramrod_eth_rx_cqe {
uint8_t ramrod_type;
-#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3 << 0)
#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
-#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */
+#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1 << 2)
#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
-#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F << 3)
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
- uint8_t conn_type /* only 3 bits are used */;
- uint16_t reserved1 /* protocol specific data */;
- uint32_t conn_and_cmd_data;
-#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
+ uint8_t conn_type;
+ __le16 reserved1;
+ __le32 conn_and_cmd_data;
+#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF << 0)
#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
-#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF << 24)
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
- struct ramrod_data protocol_data /* protocol specific data */;
- uint32_t echo;
- uint32_t reserved2[11];
+ struct ramrod_data protocol_data;
+ __le32 echo;
+ __le32 reserved2[11];
};
/*
* Rx Last CQE in page (in ETH)
*/
-struct eth_rx_cqe_next_page
-{
- uint32_t addr_lo /* Next page low pointer */;
- uint32_t addr_hi /* Next page high pointer */;
- uint32_t reserved[14];
+struct eth_rx_cqe_next_page {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le32 reserved[14];
};
/*
* union for all eth rx cqe types (fix their sizes)
*/
-union eth_rx_cqe
-{
+union eth_rx_cqe {
struct eth_fast_path_rx_cqe fast_path_cqe;
struct common_ramrod_eth_rx_cqe ramrod_cqe;
struct eth_rx_cqe_next_page next_page_cqe;
@@ -4580,324 +4927,328 @@ union eth_rx_cqe
/*
* Values for RX ETH CQE type field
*/
-enum eth_rx_cqe_type
-{
- RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */,
- RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */,
- RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */,
- RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */,
+enum eth_rx_cqe_type {
+ RX_ETH_CQE_TYPE_ETH_FASTPATH,
+ RX_ETH_CQE_TYPE_ETH_RAMROD,
+ RX_ETH_CQE_TYPE_ETH_START_AGG,
+ RX_ETH_CQE_TYPE_ETH_STOP_AGG,
MAX_ETH_RX_CQE_TYPE};
/*
* Type of SGL/Raw field in ETH RX fast path CQE
*/
-enum eth_rx_fp_sel
-{
- ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */,
- ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */,
+enum eth_rx_fp_sel {
+ ETH_FP_CQE_REGULAR,
+ ETH_FP_CQE_RAW,
MAX_ETH_RX_FP_SEL};
/*
* The eth Rx SGE Descriptor
*/
-struct eth_rx_sge
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
+struct eth_rx_sge {
+ __le32 addr_lo;
+ __le32 addr_hi;
};
/*
- * common data for all protocols $$KEEP_ENDIANNESS$$
+ * common data for all protocols
*/
-struct spe_hdr
-{
- uint32_t conn_and_cmd_data;
-#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
+struct spe_hdr {
+ __le32 conn_and_cmd_data;
+#define SPE_HDR_CID (0xFFFFFF << 0)
#define SPE_HDR_CID_SHIFT 0
-#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */
+#define SPE_HDR_CMD_ID (0xFF << 24)
#define SPE_HDR_CMD_ID_SHIFT 24
- uint16_t type;
-#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */
+ __le16 type;
+#define SPE_HDR_CONN_TYPE (0xFF << 0)
#define SPE_HDR_CONN_TYPE_SHIFT 0
-#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */
+#define SPE_HDR_FUNCTION_ID (0xFF << 8)
#define SPE_HDR_FUNCTION_ID_SHIFT 8
- uint16_t reserved1;
+ __le16 reserved1;
};
/*
* specific data for ethernet slow path element
*/
-union eth_specific_data
-{
- uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
- struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */;
- struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */;
- struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */;
- struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */;
- struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */;
- struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */;
- struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */;
- struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */;
+union eth_specific_data {
+ uint8_t protocol_data[8];
+ struct regpair client_update_ramrod_data;
+ struct regpair client_init_ramrod_init_data;
+ struct eth_halt_ramrod_data halt_ramrod_data;
+ struct regpair update_data_addr;
+ struct eth_common_ramrod_data common_ramrod_data;
+ struct regpair classify_cfg_addr;
+ struct regpair filter_cfg_addr;
+ struct regpair mcast_cfg_addr;
};
/*
* Ethernet slow path element
*/
-struct eth_spe
-{
- struct spe_hdr hdr /* common data for all protocols */;
- union eth_specific_data data /* data specific to ethernet protocol */;
+struct eth_spe {
+ struct spe_hdr hdr;
+ union eth_specific_data data;
};
/*
* Ethernet command ID for slow path elements
*/
-enum eth_spqe_cmd_id
-{
+enum eth_spqe_cmd_id {
RAMROD_CMD_ID_ETH_UNUSED,
- RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */,
- RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */,
- RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */,
- RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */,
- RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */,
- RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */,
- RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */,
- RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */,
- RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
- RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */,
- RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */,
+ RAMROD_CMD_ID_ETH_CLIENT_SETUP,
+ RAMROD_CMD_ID_ETH_HALT,
+ RAMROD_CMD_ID_ETH_FORWARD_SETUP,
+ RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
+ RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
+ RAMROD_CMD_ID_ETH_EMPTY,
+ RAMROD_CMD_ID_ETH_TERMINATE,
+ RAMROD_CMD_ID_ETH_TPA_UPDATE,
+ RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
+ RAMROD_CMD_ID_ETH_FILTER_RULES,
+ RAMROD_CMD_ID_ETH_MULTICAST_RULES,
+ RAMROD_CMD_ID_ETH_RSS_UPDATE,
+ RAMROD_CMD_ID_ETH_SET_MAC,
MAX_ETH_SPQE_CMD_ID};
/*
* eth tpa update command
*/
-enum eth_tpa_update_command
-{
- TPA_UPDATE_NONE_COMMAND /* nop command */,
- TPA_UPDATE_ENABLE_COMMAND /* enable command */,
- TPA_UPDATE_DISABLE_COMMAND /* disable command */,
+enum eth_tpa_update_command {
+ TPA_UPDATE_NONE_COMMAND,
+ TPA_UPDATE_ENABLE_COMMAND,
+ TPA_UPDATE_DISABLE_COMMAND,
MAX_ETH_TPA_UPDATE_COMMAND};
/*
* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header
*/
-enum eth_tunnel_lso_inc_ip_id
-{
- EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */,
- INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */,
+enum eth_tunnel_lso_inc_ip_id {
+ EXT_HEADER,
+ INT_HEADER,
MAX_ETH_TUNNEL_LSO_INC_IP_ID};
/*
* In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD.
*/
-enum eth_tunnel_non_lso_csum_location
-{
- CSUM_ON_PKT /* checksum is on the packet. */,
- CSUM_ON_BD /* checksum is on the BD. */,
+enum eth_tunnel_non_lso_csum_location {
+ CSUM_ON_PKT,
+ CSUM_ON_BD,
MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};
/*
- * Tx regular BD structure $$KEEP_ENDIANNESS$$
+ * Packet Tunneling Type
+ */
+enum eth_tunn_type {
+ TUNN_TYPE_NONE,
+ TUNN_TYPE_VXLAN,
+ TUNN_TYPE_L2_GRE,
+ TUNN_TYPE_IPV4_GRE,
+ TUNN_TYPE_IPV6_GRE,
+ TUNN_TYPE_L2_GENEVE,
+ TUNN_TYPE_IPV4_GENEVE,
+ TUNN_TYPE_IPV6_GENEVE,
+ MAX_ETH_TUNN_TYPE};
+
+
+/*
+ * Tx regular BD structure
*/
-struct eth_tx_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
- uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */;
- uint16_t nbytes /* Size of the data represented by the BD */;
- uint8_t reserved[4] /* keeps same size as other eth tx bd types */;
+struct eth_tx_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le16 total_pkt_bytes;
+ __le16 nbytes;
+ uint8_t reserved[4];
};
/*
* structure for easy accessibility to assembler
*/
-struct eth_tx_bd_flags
-{
+struct eth_tx_bd_flags {
uint8_t as_bitfield;
-#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */
+#define ETH_TX_BD_FLAGS_IP_CSUM (0x1 << 0)
#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
-#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */
+#define ETH_TX_BD_FLAGS_L4_CSUM (0x1 << 1)
#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
-#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */
+#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3 << 2)
#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
-#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */
+#define ETH_TX_BD_FLAGS_START_BD (0x1 << 4)
#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
-#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */
+#define ETH_TX_BD_FLAGS_IS_UDP (0x1 << 5)
#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
-#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */
+#define ETH_TX_BD_FLAGS_SW_LSO (0x1 << 6)
#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
-#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */
+#define ETH_TX_BD_FLAGS_IPV6 (0x1 << 7)
#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
};
/*
- * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$
+ * The eth Tx Buffer Descriptor
*/
-struct eth_tx_start_bd
-{
- uint64_t addr;
- uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */;
- uint16_t nbytes /* Size of the data represented by the BD */;
- uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */;
+struct eth_tx_start_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ __le16 nbd;
+ __le16 nbytes;
+ __le16 vlan_or_ethertype;
struct eth_tx_bd_flags bd_flags;
uint8_t general_data;
-#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */
+#define ETH_TX_START_BD_HDR_NBDS (0x7 << 0)
#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
-#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */
+#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1 << 3)
+#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
+#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1 << 4)
#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
-#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */
+#define ETH_TX_START_BD_PARSE_NBDS (0x3 << 5)
#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
-#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */
+#define ETH_TX_START_BD_TUNNEL_EXIST (0x1 << 7)
#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
};
/*
- * Tx parsing BD structure for ETH E1h $$KEEP_ENDIANNESS$$
+ * Tx parsing BD structure for ETH E1/E1h
*/
-struct eth_tx_parse_bd_e1x
-{
- uint16_t global_data;
-#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */
+struct eth_tx_parse_bd_e1x {
+ __le16 global_data;
+#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF << 0)
#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */
+#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3 << 4)
#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
-#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */
+#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1 << 6)
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
-#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */
+#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1 << 7)
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
-#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
+#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1 << 8)
#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
-#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */
+#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F << 9)
#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
uint8_t tcp_flags;
-#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
+#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1 << 0)
#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
-#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
+#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1 << 1)
#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
-#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
+#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1 << 2)
#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
-#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
+#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1 << 3)
#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
-#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
+#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1 << 4)
#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
-#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
+#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1 << 5)
#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
-#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
+#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1 << 6)
#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
-#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
+#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1 << 7)
#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
- uint8_t ip_hlen_w /* IP header length in WORDs */;
- uint16_t total_hlen_w /* IP+TCP+ETH */;
- uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */;
- uint16_t lso_mss /* for LSO mode */;
- uint16_t ip_id /* for LSO mode */;
- uint32_t tcp_send_seq /* for LSO mode */;
+ uint8_t ip_hlen_w;
+ __le16 total_hlen_w;
+ __le16 tcp_pseudo_csum;
+ __le16 lso_mss;
+ __le16 ip_id;
+ __le32 tcp_send_seq;
};
/*
- * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$
+ * Tx parsing BD structure for ETH E2
*/
-struct eth_tx_parse_bd_e2
-{
- union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */;
- uint32_t parsing_data;
-#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */
+struct eth_tx_parse_bd_e2 {
+ union eth_mac_addr_or_tunnel_data data;
+ __le32 parsing_data;
+#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF << 0)
#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */
+#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF << 11)
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
-#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */
+#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1 << 15)
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
-#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */
+#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF << 16)
#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
-#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */
+#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3 << 30)
#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
};
/*
- * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$
+ * Tx 2nd parsing BD structure for ETH packet
*/
-struct eth_tx_parse_2nd_bd
-{
- uint16_t global_data;
-#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */
+struct eth_tx_parse_2nd_bd {
+ __le16 global_data;
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF << 0)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
-#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */
+#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1 << 4)
#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
-#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */
+#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1 << 5)
#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
-#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
+#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1 << 6)
#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
-#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */
+#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1 << 7)
#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
-#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F << 8)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
-#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */
+#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7 << 13)
#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
- uint16_t reserved2;
+ uint8_t bd_type;
+#define ETH_TX_PARSE_2ND_BD_TYPE (0xF << 0)
+#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
+#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF << 4)
+#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
+ uint8_t reserved3;
uint8_t tcp_flags;
-#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
+#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1 << 0)
#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
-#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
+#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1 << 1)
#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
-#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
+#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1 << 2)
#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
-#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
+#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1 << 3)
#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
-#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
+#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1 << 4)
#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
-#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
+#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1 << 5)
#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
-#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
+#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1 << 6)
#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
-#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
+#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1 << 7)
#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
- uint8_t reserved3;
- uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */;
- uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */;
- uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */;
- uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */;
- uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */;
+ uint8_t reserved4;
+ uint8_t tunnel_udp_hdr_start_w;
+ uint8_t fw_ip_hdr_to_payload_w;
+ __le16 fw_ip_csum_wo_len_flags_frag;
+ __le16 hw_ip_id;
+ __le32 tcp_send_seq;
};
/*
* The last BD in the BD memory will hold a pointer to the next BD memory
*/
-struct eth_tx_next_bd
-{
- uint32_t addr_lo /* Single continuous buffer low pointer */;
- uint32_t addr_hi /* Single continuous buffer high pointer */;
- uint8_t reserved[8] /* keeps same size as other eth tx bd types */;
+struct eth_tx_next_bd {
+ __le32 addr_lo;
+ __le32 addr_hi;
+ uint8_t reserved[8];
};
/*
* union for 4 Bd types
*/
-union eth_tx_bd_types
-{
- struct eth_tx_start_bd start_bd /* the first bd in a packets */;
- struct eth_tx_bd reg_bd /* the common bd */;
- struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */;
- struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */;
- struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */;
- struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */;
+union eth_tx_bd_types {
+ struct eth_tx_start_bd start_bd;
+ struct eth_tx_bd reg_bd;
+ struct eth_tx_parse_bd_e1x parse_bd_e1x;
+ struct eth_tx_parse_bd_e2 parse_bd_e2;
+ struct eth_tx_parse_2nd_bd parse_2nd_bd;
+ struct eth_tx_next_bd next_bd;
};
/*
* array of 13 bds as appears in the eth xstorm context
*/
-struct eth_tx_bds_array
-{
+struct eth_tx_bds_array {
union eth_tx_bd_types bds[13];
};
@@ -4905,79 +5256,73 @@ struct eth_tx_bds_array
/*
* VLAN mode on TX BDs
*/
-enum eth_tx_vlan_type
-{
+enum eth_tx_vlan_type {
X_ETH_NO_VLAN,
X_ETH_OUTBAND_VLAN,
X_ETH_INBAND_VLAN,
- X_ETH_FW_ADDED_VLAN /* Driver should not use this! */,
+ X_ETH_FW_ADDED_VLAN,
MAX_ETH_TX_VLAN_TYPE};
/*
* Ethernet VLAN filtering mode in E1x
*/
-enum eth_vlan_filter_mode
-{
- ETH_VLAN_FILTER_ANY_VLAN /* Don't filter by vlan */,
- ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */,
- ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */,
+enum eth_vlan_filter_mode {
+ ETH_VLAN_FILTER_ANY_VLAN,
+ ETH_VLAN_FILTER_SPECIFIC_VLAN,
+ ETH_VLAN_FILTER_CLASSIFY,
MAX_ETH_VLAN_FILTER_MODE};
/*
- * MAC filtering configuration command header $$KEEP_ENDIANNESS$$
+ * MAC filtering configuration command header
*/
-struct mac_configuration_hdr
-{
- uint8_t length /* number of entries valid in this command (6 bits) */;
- uint8_t offset /* offset of the first entry in the list */;
- uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */;
- uint32_t echo /* echo value to be sent to driver on event ring */;
+struct mac_configuration_hdr {
+ uint8_t length;
+ uint8_t offset;
+ __le16 client_id;
+ __le32 echo;
};
/*
- * MAC address in list for ramrod $$KEEP_ENDIANNESS$$
+ * MAC address in list for ramrod
*/
-struct mac_configuration_entry
-{
- uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
- uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */;
- uint8_t pf_id /* The pf id, for multi function mode */;
+struct mac_configuration_entry {
+ __le16 lsb_mac_addr;
+ __le16 middle_mac_addr;
+ __le16 msb_mac_addr;
+ __le16 vlan_id;
+ uint8_t pf_id;
uint8_t flags;
-#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */
+#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1 << 0)
#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
-#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */
+#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1 << 1)
#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
-#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */
+#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3 << 2)
#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
-#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - can't remove vlan 1 - can remove vlan. relevant only to everest1 */
+#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1 << 4)
#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
-#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */
+#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1 << 5)
#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
-#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */
+#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3 << 6)
#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
- uint16_t reserved0;
- uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */;
+ __le16 reserved0;
+ __le32 clients_bit_vector;
};
/*
* MAC filtering configuration command
*/
-struct mac_configuration_cmd
-{
- struct mac_configuration_hdr hdr /* header */;
- struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */;
+struct mac_configuration_cmd {
+ struct mac_configuration_hdr hdr;
+ struct mac_configuration_entry config_table[64];
};
/*
* Set-MAC command type (in E1x)
*/
-enum set_mac_action_type
-{
+enum set_mac_action_type {
T_ETH_MAC_COMMAND_INVALIDATE,
T_ETH_MAC_COMMAND_SET,
MAX_SET_MAC_ACTION_TYPE};
@@ -4986,160 +5331,211 @@ enum set_mac_action_type
/*
* Ethernet TPA Modes
*/
-enum tpa_mode
-{
- TPA_LRO /* LRO mode TPA */,
- TPA_GRO /* GRO mode TPA */,
+enum tpa_mode {
+ TPA_LRO,
+ TPA_GRO,
MAX_TPA_MODE};
/*
- * tpa update ramrod data $$KEEP_ENDIANNESS$$
+ * tpa update ramrod data
*/
-struct tpa_update_ramrod_data
-{
- uint8_t update_ipv4 /* none, enable or disable */;
- uint8_t update_ipv6 /* none, enable or disable */;
- uint8_t client_id /* client init flow control data */;
- uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
- uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
- uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */;
- uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
- uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */;
- uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
- uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
- uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */;
- uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */;
- uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
- uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
+struct tpa_update_ramrod_data {
+ uint8_t update_ipv4;
+ uint8_t update_ipv6;
+ uint8_t client_id;
+ uint8_t max_tpa_queues;
+ uint8_t max_sges_for_packet;
+ uint8_t complete_on_both_clients;
+ uint8_t dont_verify_rings_pause_thr_flg;
+ uint8_t tpa_mode;
+ __le16 sge_buff_size;
+ __le16 max_agg_size;
+ __le32 sge_page_base_lo;
+ __le32 sge_page_base_hi;
+ __le16 sge_pause_thr_low;
+ __le16 sge_pause_thr_high;
+ uint8_t tpa_over_vlan_disable;
+ uint8_t reserved[7];
};
/*
* approximate-match multicast filtering for E1H per function in Tstorm
*/
-struct tstorm_eth_approximate_match_multicast_filtering
-{
- uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */;
+struct tstorm_eth_approximate_match_multicast_filtering {
+ uint32_t mcast_add_hash_bit_array[8];
};
/*
- * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$
+ * Common configuration parameters per function in Tstorm
*/
-struct tstorm_eth_function_common_config
-{
- uint16_t config_flags;
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
+struct tstorm_eth_function_common_config {
+ __le16 config_flags;
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1 << 0)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1 << 1)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1 << 2)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1 << 3)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7 << 4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Don't filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1 << 7)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF << 8)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
- uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
+ uint8_t rss_result_mask;
uint8_t reserved1;
- uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */;
+ __le16 vlan_id[2];
};
/*
- * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$
+ * MAC filtering configuration parameters per port in Tstorm
*/
-struct tstorm_eth_mac_filter_config
-{
- uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */;
- uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */;
- uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */;
- uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */;
- uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */;
- uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. The primary vlan is taken from the CAM target table. */;
- uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */;
+struct tstorm_eth_mac_filter_config {
+ uint32_t ucast_drop_all;
+ uint32_t ucast_accept_all;
+ uint32_t mcast_drop_all;
+ uint32_t mcast_accept_all;
+ uint32_t bcast_accept_all;
+ uint32_t vlan_filter[2];
+ uint32_t unmatched_unicast;
};
/*
- * tx only queue init ramrod data $$KEEP_ENDIANNESS$$
+ * tx only queue init ramrod data
*/
-struct tx_queue_init_ramrod_data
-{
- struct client_init_general_data general /* client init general data */;
- struct client_init_tx_data tx /* client init tx data */;
+struct tx_queue_init_ramrod_data {
+ struct client_init_general_data general;
+ struct client_init_tx_data tx;
};
/*
* Three RX producers for ETH
*/
-union ustorm_eth_rx_producers
-{
- struct {
+struct ustorm_eth_rx_producers {
#if defined(__BIG_ENDIAN)
- uint16_t bd_prod /* Producer of the RX BD ring */;
- uint16_t cqe_prod /* Producer of the RX CQE ring */;
+ uint16_t bd_prod;
+ uint16_t cqe_prod;
#elif defined(__LITTLE_ENDIAN)
- uint16_t cqe_prod /* Producer of the RX CQE ring */;
- uint16_t bd_prod /* Producer of the RX BD ring */;
+ uint16_t cqe_prod;
+ uint16_t bd_prod;
#endif
#if defined(__BIG_ENDIAN)
- uint16_t reserved;
- uint16_t sge_prod /* Producer of the RX SGE ring */;
+ uint16_t reserved;
+ uint16_t sge_prod;
#elif defined(__LITTLE_ENDIAN)
- uint16_t sge_prod /* Producer of the RX SGE ring */;
- uint16_t reserved;
+ uint16_t sge_prod;
+ uint16_t reserved;
#endif
- } prod;
- uint32_t raw_data[2];
};
/*
- * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$
+ * FCoE RX statistics parameters section#0
+ */
+struct fcoe_rx_stat_params_section0 {
+ __le32 fcoe_rx_pkt_cnt;
+ __le32 fcoe_rx_byte_cnt;
+};
+
+
+/*
+ * FCoE RX statistics parameters section#1
+ */
+struct fcoe_rx_stat_params_section1 {
+ __le32 fcoe_ver_cnt;
+ __le32 fcoe_rx_drop_pkt_cnt;
+};
+
+
+/*
+ * FCoE RX statistics parameters section#2
+ */
+struct fcoe_rx_stat_params_section2 {
+ __le32 fc_crc_cnt;
+ __le32 eofa_del_cnt;
+ __le32 miss_frame_cnt;
+ __le32 seq_timeout_cnt;
+ __le32 drop_seq_cnt;
+ __le32 fcoe_rx_drop_pkt_cnt;
+ __le32 fcp_rx_pkt_cnt;
+ __le32 reserved0;
+};
+
+
+/*
+ * FCoE TX statistics parameters
+ */
+struct fcoe_tx_stat_params {
+ __le32 fcoe_tx_pkt_cnt;
+ __le32 fcoe_tx_byte_cnt;
+ __le32 fcp_tx_pkt_cnt;
+ __le32 reserved0;
+};
+
+/*
+ * FCoE statistics parameters
*/
-struct afex_vif_list_ramrod_data
-{
- uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */;
- uint8_t func_bit_map /* the function bit map to set */;
- uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */;
- uint8_t func_to_clear /* the func id to clear in case of clear func mode */;
+struct fcoe_statistics_params {
+ struct fcoe_tx_stat_params tx_stat;
+ struct fcoe_rx_stat_params_section0 rx_stat0;
+ struct fcoe_rx_stat_params_section1 rx_stat1;
+ struct fcoe_rx_stat_params_section2 rx_stat2;
+};
+
+
+/*
+ * The data afex vif list ramrod need
+ */
+struct afex_vif_list_ramrod_data {
+ uint8_t afex_vif_list_command;
+ uint8_t func_bit_map;
+ __le16 vif_list_index;
+ uint8_t func_to_clear;
uint8_t echo;
- uint16_t reserved1;
+ __le16 reserved1;
};
/*
- * cfc delete event data $$KEEP_ENDIANNESS$$
+ *
*/
-struct cfc_del_event_data
-{
- uint32_t cid /* cid of deleted connection */;
- uint32_t reserved0;
- uint32_t reserved1;
+struct c2s_pri_trans_table_entry {
+ uint8_t val[8];
+};
+
+
+/*
+ * cfc delete event data
+ */
+struct cfc_del_event_data {
+ __le32 cid;
+ __le32 reserved0;
+ __le32 reserved1;
};
/*
* per-port SAFC demo variables
*/
-struct cmng_flags_per_port
-{
+struct cmng_flags_per_port {
uint32_t cmng_enables;
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1 << 0)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
-#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1 << 1)
#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1 << 2)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
-#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1 << 3)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
-#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */
+#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF << 4)
#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
uint32_t __reserved1;
};
@@ -5148,46 +5544,42 @@ struct cmng_flags_per_port
/*
* per-port rate shaping variables
*/
-struct rate_shaping_vars_per_port
-{
- uint32_t rs_periodic_timeout /* timeout of periodic timer */;
- uint32_t rs_threshold /* threshold, below which we start to stop queues */;
+struct rate_shaping_vars_per_port {
+ uint32_t rs_periodic_timeout;
+ uint32_t rs_threshold;
};
/*
* per-port fairness variables
*/
-struct fairness_vars_per_port
-{
- uint32_t upper_bound /* Quota for a protocol/vnic */;
- uint32_t fair_threshold /* almost-empty threshold */;
- uint32_t fairness_timeout /* timeout of fairness timer */;
- uint32_t reserved0;
+struct fairness_vars_per_port {
+ uint32_t upper_bound;
+ uint32_t fair_threshold;
+ uint32_t fairness_timeout;
+ uint32_t size_thr;
};
/*
* per-port SAFC variables
*/
-struct safc_struct_per_port
-{
+struct safc_struct_per_port {
#if defined(__BIG_ENDIAN)
uint16_t __reserved1;
uint8_t __reserved0;
- uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
+ uint8_t safc_timeout_usec;
#elif defined(__LITTLE_ENDIAN)
- uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
+ uint8_t safc_timeout_usec;
uint8_t __reserved0;
uint16_t __reserved1;
#endif
- uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */;
- uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */;
+ uint8_t cos_to_traffic_types[MAX_COS_NUMBER];
+ uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS];
};
/*
* Per-port congestion management variables
*/
-struct cmng_struct_per_port
-{
+struct cmng_struct_per_port {
struct rate_shaping_vars_per_port rs_vars;
struct fairness_vars_per_port fair_vars;
struct safc_struct_per_port safc_vars;
@@ -5197,14 +5589,13 @@ struct cmng_struct_per_port
/*
* a single rate shaping counter. can be used as protocol or vnic counter
*/
-struct rate_shaping_counter
-{
- uint32_t quota /* Quota for a protocol/vnic */;
+struct rate_shaping_counter {
+ uint32_t quota;
#if defined(__BIG_ENDIAN)
uint16_t __reserved0;
- uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
+ uint16_t rate;
#elif defined(__LITTLE_ENDIAN)
- uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
+ uint16_t rate;
uint16_t __reserved0;
#endif
};
@@ -5212,26 +5603,23 @@ struct rate_shaping_counter
/*
* per-vnic rate shaping variables
*/
-struct rate_shaping_vars_per_vn
-{
- struct rate_shaping_counter vn_counter /* per-vnic counter */;
+struct rate_shaping_vars_per_vn {
+ struct rate_shaping_counter vn_counter;
};
/*
* per-vnic fairness variables
*/
-struct fairness_vars_per_vn
-{
- uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */;
- uint32_t vn_credit_delta /* used for incrementing the credit */;
+struct fairness_vars_per_vn {
+ uint32_t cos_credit_delta[MAX_COS_NUMBER];
+ uint32_t vn_credit_delta;
uint32_t __reserved0;
};
/*
* cmng port init state
*/
-struct cmng_vnic
-{
+struct cmng_vnic {
struct rate_shaping_vars_per_vn vnic_max_rate[4];
struct fairness_vars_per_vn vnic_min_rate[4];
};
@@ -5239,8 +5627,7 @@ struct cmng_vnic
/*
* cmng port init state
*/
-struct cmng_init
-{
+struct cmng_init {
struct cmng_struct_per_port port;
struct cmng_vnic vnic;
};
@@ -5249,12 +5636,13 @@ struct cmng_init
/*
* driver parameters for congestion management init, all rates are in Mbps
*/
-struct cmng_init_input
-{
+struct cmng_init_input {
uint32_t port_rate;
- uint16_t vnic_min_rate[4] /* rates are in Mbps */;
- uint16_t vnic_max_rate[4] /* rates are in Mbps */;
- uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */;
+ uint32_t size_thr;
+ uint32_t fairness_thr;
+ uint16_t vnic_min_rate[4];
+ uint16_t vnic_max_rate[4];
+ uint16_t cos_min_rate[MAX_COS_NUMBER];
uint16_t cos_to_pause_mask[MAX_COS_NUMBER];
struct cmng_flags_per_port flags;
};
@@ -5263,64 +5651,59 @@ struct cmng_init_input
/*
* Protocol-common command ID for slow path elements
*/
-enum common_spqe_cmd_id
-{
+enum common_spqe_cmd_id {
RAMROD_CMD_ID_COMMON_UNUSED,
- RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */,
- RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */,
- RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */,
- RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */,
- RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
- RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */,
- RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
- RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
- RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */,
- RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
+ RAMROD_CMD_ID_COMMON_FUNCTION_START,
+ RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
+ RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
+ RAMROD_CMD_ID_COMMON_CFC_DEL,
+ RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
+ RAMROD_CMD_ID_COMMON_STAT_QUERY,
+ RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
+ RAMROD_CMD_ID_COMMON_START_TRAFFIC,
+ RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
+ RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
MAX_COMMON_SPQE_CMD_ID};
/*
* Per-protocol connection types
*/
-enum connection_type
-{
- ETH_CONNECTION_TYPE /* Ethernet */,
- TOE_CONNECTION_TYPE /* TOE */,
- RDMA_CONNECTION_TYPE /* RDMA */,
- ISCSI_CONNECTION_TYPE /* iSCSI */,
- FCOE_CONNECTION_TYPE /* FCoE */,
+enum connection_type {
+ ETH_CONNECTION_TYPE,
+ TOE_CONNECTION_TYPE,
+ RDMA_CONNECTION_TYPE,
+ ISCSI_CONNECTION_TYPE,
+ FCOE_CONNECTION_TYPE,
RESERVED_CONNECTION_TYPE_0,
RESERVED_CONNECTION_TYPE_1,
RESERVED_CONNECTION_TYPE_2,
- NONE_CONNECTION_TYPE /* General- used for common slow path */,
+ NONE_CONNECTION_TYPE,
MAX_CONNECTION_TYPE};
/*
* Cos modes
*/
-enum cos_mode
-{
- OVERRIDE_COS /* Firmware deduce cos according to DCB */,
- STATIC_COS /* Firmware has constant queues per CoS */,
- FW_WRR /* Firmware keep fairness between different CoSes */,
+enum cos_mode {
+ OVERRIDE_COS,
+ STATIC_COS,
+ FW_WRR,
MAX_COS_MODE};
/*
* Dynamic HC counters set by the driver
*/
-struct hc_dynamic_drv_counter
-{
- uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */;
+struct hc_dynamic_drv_counter {
+ uint32_t val[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* zone A per-queue data
*/
-struct cstorm_queue_zone_data
-{
- struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */;
+struct cstorm_queue_zone_data {
+ struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
struct regpair reserved[2];
};
@@ -5328,120 +5711,106 @@ struct cstorm_queue_zone_data
/*
* Vf-PF channel data in cstorm ram (non-triggered zone)
*/
-struct vf_pf_channel_zone_data
-{
- uint32_t msg_addr_lo /* the message address on VF memory */;
- uint32_t msg_addr_hi /* the message address on VF memory */;
+struct vf_pf_channel_zone_data {
+ uint32_t msg_addr_lo;
+ uint32_t msg_addr_hi;
};
/*
* zone for VF non-triggered data
*/
-struct non_trigger_vf_zone
-{
- struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */;
+struct non_trigger_vf_zone {
+ struct vf_pf_channel_zone_data vf_pf_channel;
};
/*
* Vf-PF channel trigger zone in cstorm ram
*/
-struct vf_pf_channel_zone_trigger
-{
- uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */;
+struct vf_pf_channel_zone_trigger {
+ uint8_t addr_valid;
};
/*
* zone that triggers the in-bound interrupt
*/
-struct trigger_vf_zone
-{
-#if defined(__BIG_ENDIAN)
- uint16_t reserved1;
- uint8_t reserved0;
- struct vf_pf_channel_zone_trigger vf_pf_channel;
-#elif defined(__LITTLE_ENDIAN)
+struct trigger_vf_zone {
struct vf_pf_channel_zone_trigger vf_pf_channel;
uint8_t reserved0;
uint16_t reserved1;
-#endif
uint32_t reserved2;
};
/*
* zone B per-VF data
*/
-struct cstorm_vf_zone_data
-{
- struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */;
- struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */;
+struct cstorm_vf_zone_data {
+ struct non_trigger_vf_zone non_trigger;
+ struct trigger_vf_zone trigger;
};
/*
* Dynamic host coalescing init parameters, per state machine
*/
-struct dynamic_hc_sm_config
-{
- uint32_t threshold[3] /* thresholds of number of outstanding bytes */;
- uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */;
- uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */;
- uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */;
- uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */;
- uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */;
+struct dynamic_hc_sm_config {
+ uint32_t threshold[3];
+ uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
+ uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* Dynamic host coalescing init parameters
*/
-struct dynamic_hc_config
-{
- struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */;
+struct dynamic_hc_config {
+ struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
};
-struct e2_integ_data
-{
+struct e2_integ_data {
#if defined(__BIG_ENDIAN)
uint8_t flags;
-#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
+#define E2_INTEG_DATA_TESTING_EN (0x1 << 0)
#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
-#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
+#define E2_INTEG_DATA_LB_TX (0x1 << 1)
#define E2_INTEG_DATA_LB_TX_SHIFT 1
-#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
+#define E2_INTEG_DATA_COS_TX (0x1 << 2)
#define E2_INTEG_DATA_COS_TX_SHIFT 2
-#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1 << 3)
#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
-#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1 << 4)
#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
-#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
+#define E2_INTEG_DATA_RESERVED (0x7 << 5)
#define E2_INTEG_DATA_RESERVED_SHIFT 5
- uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
- uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
+ uint8_t cos;
+ uint8_t voq;
+ uint8_t pbf_queue;
#elif defined(__LITTLE_ENDIAN)
- uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
- uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
+ uint8_t pbf_queue;
+ uint8_t voq;
+ uint8_t cos;
uint8_t flags;
-#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
+#define E2_INTEG_DATA_TESTING_EN (0x1 << 0)
#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
-#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
+#define E2_INTEG_DATA_LB_TX (0x1 << 1)
#define E2_INTEG_DATA_LB_TX_SHIFT 1
-#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
+#define E2_INTEG_DATA_COS_TX (0x1 << 2)
#define E2_INTEG_DATA_COS_TX_SHIFT 2
-#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1 << 3)
#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
-#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1 << 4)
#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
-#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
+#define E2_INTEG_DATA_RESERVED (0x7 << 5)
#define E2_INTEG_DATA_RESERVED_SHIFT 5
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3;
uint8_t reserved2;
- uint8_t ramEn /* context area reserved for reading enable bit from ram */;
+ uint8_t ramEn;
#elif defined(__LITTLE_ENDIAN)
- uint8_t ramEn /* context area reserved for reading enable bit from ram */;
+ uint8_t ramEn;
uint8_t reserved2;
uint16_t reserved3;
#endif
@@ -5449,333 +5818,320 @@ struct e2_integ_data
/*
- * set mac event data $$KEEP_ENDIANNESS$$
+ * set mac event data
*/
-struct eth_event_data
-{
- uint32_t echo /* set mac echo data to return to driver */;
- uint32_t reserved0;
- uint32_t reserved1;
+struct eth_event_data {
+ __le32 echo;
+ __le32 reserved0;
+ __le32 reserved1;
};
/*
- * pf-vf event data $$KEEP_ENDIANNESS$$
+ * pf-vf event data
*/
-struct vf_pf_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
+struct vf_pf_event_data {
+ uint8_t vf_id;
uint8_t reserved0;
- uint16_t reserved1;
- uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */;
- uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */;
+ __le16 reserved1;
+ __le32 msg_addr_lo;
+ __le32 msg_addr_hi;
};
/*
- * VF FLR event data $$KEEP_ENDIANNESS$$
+ * VF FLR event data
*/
-struct vf_flr_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
+struct vf_flr_event_data {
+ uint8_t vf_id;
uint8_t reserved0;
- uint16_t reserved1;
- uint32_t reserved2;
- uint32_t reserved3;
+ __le16 reserved1;
+ __le32 reserved2;
+ __le32 reserved3;
};
/*
- * malicious VF event data $$KEEP_ENDIANNESS$$
+ * malicious VF event data
*/
-struct malicious_vf_event_data
-{
- uint8_t vf_id /* VF ID (0-63) */;
- uint8_t err_id /* reason for malicious notification */;
- uint16_t reserved1;
- uint32_t reserved2;
- uint32_t reserved3;
+struct malicious_vf_event_data {
+ uint8_t vf_id;
+ uint8_t err_id;
+ __le16 reserved1;
+ __le32 reserved2;
+ __le32 reserved3;
};
/*
- * vif list event data $$KEEP_ENDIANNESS$$
+ * vif list event data
*/
-struct vif_list_event_data
-{
- uint8_t func_bit_map /* bit map of pf indice */;
+struct vif_list_event_data {
+ uint8_t func_bit_map;
uint8_t echo;
- uint16_t reserved0;
- uint32_t reserved1;
- uint32_t reserved2;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le32 reserved2;
};
/*
- * function update event data $$KEEP_ENDIANNESS$$
+ * function update event data
*/
-struct function_update_event_data
-{
+struct function_update_event_data {
uint8_t echo;
uint8_t reserved;
- uint16_t reserved0;
- uint32_t reserved1;
- uint32_t reserved2;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le32 reserved2;
};
/*
* union for all event ring message types
*/
-union event_data
-{
- struct vf_pf_event_data vf_pf_event /* vf-pf event data */;
- struct eth_event_data eth_event /* set mac event data */;
- struct cfc_del_event_data cfc_del_event /* cfc delete event data */;
- struct vf_flr_event_data vf_flr_event /* vf flr event data */;
- struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */;
- struct vif_list_event_data vif_list_event /* vif list event data */;
- struct function_update_event_data function_update_event /* function update event data */;
+union event_data {
+ struct vf_pf_event_data vf_pf_event;
+ struct eth_event_data eth_event;
+ struct cfc_del_event_data cfc_del_event;
+ struct vf_flr_event_data vf_flr_event;
+ struct malicious_vf_event_data malicious_vf_event;
+ struct vif_list_event_data vif_list_event;
+ struct function_update_event_data function_update_event;
};
/*
* per PF event ring data
*/
-struct event_ring_data
-{
- struct regpair_native base_addr /* ring base address */;
+struct event_ring_data {
+ struct regpair_native base_addr;
#if defined(__BIG_ENDIAN)
- uint8_t index_id /* index ID within the status block */;
- uint8_t sb_id /* status block ID */;
- uint16_t producer /* event ring producer */;
+ uint8_t index_id;
+ uint8_t sb_id;
+ uint16_t producer;
#elif defined(__LITTLE_ENDIAN)
- uint16_t producer /* event ring producer */;
- uint8_t sb_id /* status block ID */;
- uint8_t index_id /* index ID within the status block */;
+ uint16_t producer;
+ uint8_t sb_id;
+ uint8_t index_id;
#endif
uint32_t reserved0;
};
/*
- * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$
+ * event ring message element (each element is 128 bits)
*/
-struct event_ring_msg
-{
+struct event_ring_msg {
uint8_t opcode;
- uint8_t error /* error on the mesasage */;
+ uint8_t error;
uint16_t reserved1;
- union event_data data /* message data (96 bits data) */;
+ union event_data data;
};
/*
* event ring next page element (128 bits)
*/
-struct event_ring_next
-{
- struct regpair addr /* Address of the next page of the ring */;
+struct event_ring_next {
+ struct regpair addr;
uint32_t reserved[2];
};
/*
* union for event ring element types (each element is 128 bits)
*/
-union event_ring_elem
-{
- struct event_ring_msg message /* event ring message */;
- struct event_ring_next next_page /* event ring next page */;
+union event_ring_elem {
+ struct event_ring_msg message;
+ struct event_ring_next next_page;
};
/*
* Common event ring opcodes
*/
-enum event_ring_opcode
-{
+enum event_ring_opcode {
EVENT_RING_OPCODE_VF_PF_CHANNEL,
- EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */,
- EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */,
- EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */,
- EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
- EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */,
- EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
- EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
- EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */,
- EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */,
- EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */,
- EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */,
- EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */,
- EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */,
- EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */,
- EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */,
- EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
- EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
- EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
+ EVENT_RING_OPCODE_FUNCTION_START,
+ EVENT_RING_OPCODE_FUNCTION_STOP,
+ EVENT_RING_OPCODE_CFC_DEL,
+ EVENT_RING_OPCODE_CFC_DEL_WB,
+ EVENT_RING_OPCODE_STAT_QUERY,
+ EVENT_RING_OPCODE_STOP_TRAFFIC,
+ EVENT_RING_OPCODE_START_TRAFFIC,
+ EVENT_RING_OPCODE_VF_FLR,
+ EVENT_RING_OPCODE_MALICIOUS_VF,
+ EVENT_RING_OPCODE_FORWARD_SETUP,
+ EVENT_RING_OPCODE_RSS_UPDATE_RULES,
+ EVENT_RING_OPCODE_FUNCTION_UPDATE,
+ EVENT_RING_OPCODE_AFEX_VIF_LISTS,
+ EVENT_RING_OPCODE_SET_MAC,
+ EVENT_RING_OPCODE_CLASSIFICATION_RULES,
+ EVENT_RING_OPCODE_FILTERS_RULES,
+ EVENT_RING_OPCODE_MULTICAST_RULES,
+ EVENT_RING_OPCODE_SET_TIMESYNC,
MAX_EVENT_RING_OPCODE};
/*
* Modes for fairness algorithm
*/
-enum fairness_mode
-{
- FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */,
- FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */,
+enum fairness_mode {
+ FAIRNESS_COS_WRR_MODE,
+ FAIRNESS_COS_ETS_MODE,
MAX_FAIRNESS_MODE};
/*
- * Priority and cos $$KEEP_ENDIANNESS$$
+ * Priority and cos
*/
-struct priority_cos
-{
- uint8_t priority /* Priority */;
- uint8_t cos /* Cos */;
- uint16_t reserved1;
+struct priority_cos {
+ uint8_t priority;
+ uint8_t cos;
+ __le16 reserved1;
};
/*
- * The data for flow control configuration $$KEEP_ENDIANNESS$$
+ * The data for flow control configuration
*/
-struct flow_control_configuration
-{
- struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */;
- uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */;
- uint8_t dcb_version /* DCB version Increase by one on each DCB update */;
- uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */;
+struct flow_control_configuration {
+ struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
+ uint8_t dcb_enabled;
+ uint8_t dcb_version;
+ uint8_t dont_add_pri_0_en;
uint8_t reserved1;
- uint32_t reserved2;
+ __le32 reserved2;
+ uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct function_start_data
-{
- uint8_t function_mode /* the function mode */;
- uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode. (E2/E3 Only) */;
- uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */;
- uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
+struct function_start_data {
+ uint8_t function_mode;
+ uint8_t allow_npar_tx_switching;
+ __le16 sd_vlan_tag;
+ __le16 vif_id;
uint8_t path_id;
- uint8_t network_cos_mode /* The cos mode for network traffic. */;
- uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */;
- uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
- uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
- uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
- uint16_t reserved1[2];
-};
-
-
-/*
- * $$KEEP_ENDIANNESS$$
- */
-struct function_update_data
-{
- uint8_t vif_id_change_flg /* If set, vif_id will be checked */;
- uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */;
- uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */;
- uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */;
- uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
- uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */;
- uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */;
- uint8_t network_cos_mode /* The cos mode for network traffic. */;
- uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */;
- uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */;
- uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */;
- uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */;
+ uint8_t network_cos_mode;
+ uint8_t dmae_cmd_id;
+ uint8_t no_added_tags;
+ __le16 reserved0;
+ __le32 reserved1;
+ uint8_t inner_clss_vxlan;
+ uint8_t inner_clss_l2gre;
+ uint8_t inner_clss_l2geneve;
+ uint8_t inner_rss;
+ __le16 vxlan_dst_port;
+ __le16 geneve_dst_port;
+ uint8_t sd_accept_mf_clss_fail;
+ uint8_t sd_accept_mf_clss_fail_match_ethtype;
+ __le16 sd_accept_mf_clss_fail_ethtype;
+ __le16 sd_vlan_eth_type;
+ uint8_t sd_vlan_force_pri_flg;
+ uint8_t sd_vlan_force_pri_val;
+ uint8_t c2s_pri_tt_valid;
+ uint8_t c2s_pri_default;
+ uint8_t tx_vlan_filtering_enable;
+ uint8_t tx_vlan_filtering_use_pvid;
+ uint8_t reserved2[4];
+ struct c2s_pri_trans_table_entry c2s_pri_trans_table;
+};
+
+
+/*
+ *
+ */
+struct function_update_data {
+ uint8_t vif_id_change_flg;
+ uint8_t afex_default_vlan_change_flg;
+ uint8_t allowed_priorities_change_flg;
+ uint8_t network_cos_mode_change_flg;
+ __le16 vif_id;
+ __le16 afex_default_vlan;
+ uint8_t allowed_priorities;
+ uint8_t network_cos_mode;
+ uint8_t lb_mode_en_change_flg;
+ uint8_t lb_mode_en;
+ uint8_t tx_switch_suspend_change_flg;
+ uint8_t tx_switch_suspend;
uint8_t echo;
+ uint8_t update_tunn_cfg_flg;
+ uint8_t inner_clss_vxlan;
+ uint8_t inner_clss_l2gre;
+ uint8_t inner_clss_l2geneve;
+ uint8_t inner_rss;
+ __le16 vxlan_dst_port;
+ __le16 geneve_dst_port;
+ uint8_t sd_vlan_force_pri_change_flg;
+ uint8_t sd_vlan_force_pri_flg;
+ uint8_t sd_vlan_force_pri_val;
+ uint8_t sd_vlan_tag_change_flg;
+ uint8_t sd_vlan_eth_type_change_flg;
uint8_t reserved1;
- uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */;
- uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
- uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
- uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
- uint32_t reserved3;
+ __le16 sd_vlan_tag;
+ __le16 sd_vlan_eth_type;
+ uint8_t tx_vlan_filtering_pvid_change_flg;
+ uint8_t reserved0;
+ __le32 reserved2;
};
/*
* FW version stored in the Xstorm RAM
*/
-struct fw_version
-{
+struct fw_version {
#if defined(__BIG_ENDIAN)
- uint8_t engineering /* firmware current engineering version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t major /* firmware current major version */;
+ uint8_t engineering;
+ uint8_t revision;
+ uint8_t minor;
+ uint8_t major;
#elif defined(__LITTLE_ENDIAN)
- uint8_t major /* firmware current major version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t engineering /* firmware current engineering version */;
+ uint8_t major;
+ uint8_t minor;
+ uint8_t revision;
+ uint8_t engineering;
#endif
uint32_t flags;
-#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
+#define FW_VERSION_OPTIMIZED (0x1 << 0)
#define FW_VERSION_OPTIMIZED_SHIFT 0
-#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */
+#define FW_VERSION_BIG_ENDIEN (0x1 << 1)
#define FW_VERSION_BIG_ENDIEN_SHIFT 1
-#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 1 - E1H */
+#define FW_VERSION_CHIP_VERSION (0x3 << 2)
#define FW_VERSION_CHIP_VERSION_SHIFT 2
-#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */
+#define __FW_VERSION_RESERVED (0xFFFFFFF << 4)
#define __FW_VERSION_RESERVED_SHIFT 4
};
-/*
- * GRE RSS Mode
- */
-enum gre_rss_mode
-{
- GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */,
- GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */,
- NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */,
- MAX_GRE_RSS_MODE};
-
-
-/*
- * GRE Tunnel Mode
- */
-enum gre_tunnel_type
-{
- NO_GRE_TUNNEL,
- NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */,
- L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */,
- IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */,
- MAX_GRE_TUNNEL_TYPE};
-
-
/*
* Dynamic Host-Coalescing - Driver(host) counters
*/
-struct hc_dynamic_sb_drv_counters
-{
- uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */;
+struct hc_dynamic_sb_drv_counters {
+ uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
};
/*
* 2 bytes. configuration/state parameters for a single protocol index
*/
-struct hc_index_data
-{
+struct hc_index_data {
#if defined(__BIG_ENDIAN)
uint8_t flags;
-#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
+#define HC_INDEX_DATA_SM_ID (0x1 << 0)
#define HC_INDEX_DATA_SM_ID_SHIFT 0
-#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
+#define HC_INDEX_DATA_HC_ENABLED (0x1 << 1)
#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
-#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1 << 2)
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
-#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
+#define HC_INDEX_DATA_RESERVE (0x1F << 3)
#define HC_INDEX_DATA_RESERVE_SHIFT 3
- uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
+ uint8_t timeout;
#elif defined(__LITTLE_ENDIAN)
- uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
+ uint8_t timeout;
uint8_t flags;
-#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
+#define HC_INDEX_DATA_SM_ID (0x1 << 0)
#define HC_INDEX_DATA_SM_ID_SHIFT 0
-#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
+#define HC_INDEX_DATA_HC_ENABLED (0x1 << 1)
#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
-#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1 << 2)
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
-#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
+#define HC_INDEX_DATA_RESERVE (0x1F << 3)
#define HC_INDEX_DATA_RESERVE_SHIFT 3
#endif
};
@@ -5784,56 +6140,53 @@ struct hc_index_data
/*
* HC state-machine
*/
-struct hc_status_block_sm
-{
+struct hc_status_block_sm {
#if defined(__BIG_ENDIAN)
uint8_t igu_seg_id;
- uint8_t igu_sb_id /* sb_id within the IGU */;
- uint8_t timer_value /* Determines the time_to_expire */;
+ uint8_t igu_sb_id;
+ uint8_t timer_value;
uint8_t __flags;
#elif defined(__LITTLE_ENDIAN)
uint8_t __flags;
- uint8_t timer_value /* Determines the time_to_expire */;
- uint8_t igu_sb_id /* sb_id within the IGU */;
+ uint8_t timer_value;
+ uint8_t igu_sb_id;
uint8_t igu_seg_id;
#endif
- uint32_t time_to_expire /* The time in which it expects to wake up */;
+ uint32_t time_to_expire;
};
/*
* hold PCI identification variables- used in various places in firmware
*/
-struct pci_entity
-{
+struct pci_entity {
#if defined(__BIG_ENDIAN)
- uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
- uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
- uint8_t vnic_id /* Virtual NIC ID (0-3) */;
- uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
+ uint8_t vf_valid;
+ uint8_t vf_id;
+ uint8_t vnic_id;
+ uint8_t pf_id;
#elif defined(__LITTLE_ENDIAN)
- uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
- uint8_t vnic_id /* Virtual NIC ID (0-3) */;
- uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
- uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
+ uint8_t pf_id;
+ uint8_t vnic_id;
+ uint8_t vf_id;
+ uint8_t vf_valid;
#endif
};
/*
* The fast-path status block meta-data, common to all chips
*/
-struct hc_sb_data
-{
- struct regpair_native host_sb_addr /* Host status block address */;
- struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */;
- struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
+struct hc_sb_data {
+ struct regpair_native host_sb_addr;
+ struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
+ struct pci_entity p_func;
#if defined(__BIG_ENDIAN)
uint8_t rsrv0;
uint8_t state;
- uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
- uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
+ uint8_t dhc_qzone_id;
+ uint8_t same_igu_sb_1b;
#elif defined(__LITTLE_ENDIAN)
- uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
- uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
+ uint8_t same_igu_sb_1b;
+ uint8_t dhc_qzone_id;
uint8_t state;
uint8_t rsrv0;
#endif
@@ -5844,8 +6197,7 @@ struct hc_sb_data
/*
* Segment types for host coaslescing
*/
-enum hc_segment
-{
+enum hc_segment {
HC_REGULAR_SEGMENT,
HC_DEFAULT_SEGMENT,
MAX_HC_SEGMENT};
@@ -5854,59 +6206,64 @@ enum hc_segment
/*
* The fast-path status block meta-data
*/
-struct hc_sp_status_block_data
-{
- struct regpair_native host_sb_addr /* Host status block address */;
+struct hc_sp_status_block_data {
+ struct regpair_native host_sb_addr;
#if defined(__BIG_ENDIAN)
uint8_t rsrv1;
uint8_t state;
- uint8_t igu_seg_id /* segment id of the IGU */;
- uint8_t igu_sb_id /* sb_id within the IGU */;
+ uint8_t igu_seg_id;
+ uint8_t igu_sb_id;
#elif defined(__LITTLE_ENDIAN)
- uint8_t igu_sb_id /* sb_id within the IGU */;
- uint8_t igu_seg_id /* segment id of the IGU */;
+ uint8_t igu_sb_id;
+ uint8_t igu_seg_id;
uint8_t state;
uint8_t rsrv1;
#endif
- struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
+ struct pci_entity p_func;
};
/*
* The fast-path status block meta-data
*/
-struct hc_status_block_data_e1x
-{
- struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */;
- struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
+struct hc_status_block_data_e1x {
+ struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
+ struct hc_sb_data common;
};
/*
* The fast-path status block meta-data
*/
-struct hc_status_block_data_e2
-{
- struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */;
- struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
+struct hc_status_block_data_e2 {
+ struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
+ struct hc_sb_data common;
};
/*
* IGU block operartion modes (in Everest2)
*/
-enum igu_mode
-{
- HC_IGU_BC_MODE /* Backward compatible mode */,
- HC_IGU_NBC_MODE /* Non-backward compatible mode */,
+enum igu_mode {
+ HC_IGU_BC_MODE,
+ HC_IGU_NBC_MODE,
MAX_IGU_MODE};
+/*
+ * Inner Headers Classification Type
+ */
+enum inner_clss_type {
+ INNER_CLSS_DISABLED,
+ INNER_CLSS_USE_VLAN,
+ INNER_CLSS_USE_VNI,
+ MAX_INNER_CLSS_TYPE};
+
+
/*
* IP versions
*/
-enum ip_ver
-{
+enum ip_ver {
IP_V4,
IP_V6,
MAX_IP_VER};
@@ -5915,131 +6272,122 @@ enum ip_ver
/*
* Malicious VF error ID
*/
-enum malicious_vf_error_id
-{
- VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */,
- ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */,
- ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */,
- ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */,
- ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,
- ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */,
- ETH_TOO_MANY_BDS /* Tx packet has too many BDs */,
- ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */,
- ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */,
- ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */,
- ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */,
- ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */,
- ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */,
- ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */,
+enum malicious_vf_error_id {
+ MALICIOUS_VF_NO_ERROR,
+ VF_PF_CHANNEL_NOT_READY,
+ ETH_ILLEGAL_BD_LENGTHS,
+ ETH_PACKET_TOO_SHORT,
+ ETH_PAYLOAD_TOO_BIG,
+ ETH_ILLEGAL_ETH_TYPE,
+ ETH_ILLEGAL_LSO_HDR_LEN,
+ ETH_TOO_MANY_BDS,
+ ETH_ZERO_HDR_NBDS,
+ ETH_START_BD_NOT_SET,
+ ETH_ILLEGAL_PARSE_NBDS,
+ ETH_IPV6_AND_CHECKSUM,
+ ETH_VLAN_FLG_INCORRECT,
+ ETH_ILLEGAL_LSO_MSS,
+ ETH_TUNNEL_NOT_SUPPORTED,
MAX_MALICIOUS_VF_ERROR_ID};
/*
* Multi-function modes
*/
-enum mf_mode
-{
+enum mf_mode {
SINGLE_FUNCTION,
- MULTI_FUNCTION_SD /* Switch dependent (vlan based) */,
- MULTI_FUNCTION_SI /* Switch independent (mac based) */,
- MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */,
+ MULTI_FUNCTION_SD,
+ MULTI_FUNCTION_SI,
+ MULTI_FUNCTION_AFEX,
MAX_MF_MODE};
/*
- * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per pf)
*/
-struct tstorm_per_pf_stats
-{
- struct regpair rcv_error_bytes /* number of bytes received with errors */;
+struct tstorm_per_pf_stats {
+ struct regpair rcv_error_bytes;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_pf_stats
-{
+struct per_pf_stats {
struct tstorm_per_pf_stats tstorm_pf_statistics;
};
/*
- * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per port)
*/
-struct tstorm_per_port_stats
-{
- uint32_t mac_discard /* number of packets with mac errors */;
- uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */;
- uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */;
- uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */;
- uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */;
- uint32_t reserved;
+struct tstorm_per_port_stats {
+ __le32 mac_discard;
+ __le32 mac_filter_discard;
+ __le32 brb_truncate_discard;
+ __le32 mf_tag_discard;
+ __le32 packet_drop;
+ __le32 reserved;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_port_stats
-{
+struct per_port_stats {
struct tstorm_per_port_stats tstorm_port_statistics;
};
/*
- * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Tstorm (per client)
*/
-struct tstorm_per_queue_stats
-{
- struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */;
- uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */;
- uint32_t checksum_discard /* number of total packets received with checksum error */;
- struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */;
- uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */;
- uint32_t pkts_too_big_discard /* number of too long packets received */;
- struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */;
- uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */;
- uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;
- uint16_t no_buff_discard;
- uint16_t reserved0;
- uint32_t reserved1;
+struct tstorm_per_queue_stats {
+ struct regpair rcv_ucast_bytes;
+ __le32 rcv_ucast_pkts;
+ __le32 checksum_discard;
+ struct regpair rcv_bcast_bytes;
+ __le32 rcv_bcast_pkts;
+ __le32 pkts_too_big_discard;
+ struct regpair rcv_mcast_bytes;
+ __le32 rcv_mcast_pkts;
+ __le32 ttl0_discard;
+ __le16 no_buff_discard;
+ __le16 reserved0;
+ __le32 reserved1;
};
/*
- * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Ustorm (per client)
*/
-struct ustorm_per_queue_stats
-{
- struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */;
- struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */;
- struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */;
- uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
- uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */;
- struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */;
- uint32_t coalesced_events /* the number of aggregations */;
- uint32_t coalesced_aborts /* the number of exception which avoid aggregation */;
+struct ustorm_per_queue_stats {
+ struct regpair ucast_no_buff_bytes;
+ struct regpair mcast_no_buff_bytes;
+ struct regpair bcast_no_buff_bytes;
+ __le32 ucast_no_buff_pkts;
+ __le32 mcast_no_buff_pkts;
+ __le32 bcast_no_buff_pkts;
+ __le32 coalesced_pkts;
+ struct regpair coalesced_bytes;
+ __le32 coalesced_events;
+ __le32 coalesced_aborts;
};
/*
- * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics collected by the Xstorm (per client)
*/
-struct xstorm_per_queue_stats
-{
- struct regpair ucast_bytes_sent /* number of total bytes sent without errors */;
- struct regpair mcast_bytes_sent /* number of total bytes sent without errors */;
- struct regpair bcast_bytes_sent /* number of total bytes sent without errors */;
- uint32_t ucast_pkts_sent /* number of total packets sent without errors */;
- uint32_t mcast_pkts_sent /* number of total packets sent without errors */;
- uint32_t bcast_pkts_sent /* number of total packets sent without errors */;
- uint32_t error_drop_pkts /* number of total packets drooped due to errors */;
+struct xstorm_per_queue_stats {
+ struct regpair ucast_bytes_sent;
+ struct regpair mcast_bytes_sent;
+ struct regpair bcast_bytes_sent;
+ __le32 ucast_pkts_sent;
+ __le32 mcast_pkts_sent;
+ __le32 bcast_pkts_sent;
+ __le32 error_drop_pkts;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct per_queue_stats
-{
+struct per_queue_stats {
struct tstorm_per_queue_stats tstorm_queue_statistics;
struct ustorm_per_queue_stats ustorm_queue_statistics;
struct xstorm_per_queue_stats xstorm_queue_statistics;
@@ -6047,24 +6395,23 @@ struct per_queue_stats
/*
- * FW version stored in first line of pram $$KEEP_ENDIANNESS$$
+ * FW version stored in first line of pram
*/
-struct pram_fw_version
-{
- uint8_t major /* firmware current major version */;
- uint8_t minor /* firmware current minor version */;
- uint8_t revision /* firmware current revision version */;
- uint8_t engineering /* firmware current engineering version */;
+struct pram_fw_version {
+ uint8_t major;
+ uint8_t minor;
+ uint8_t revision;
+ uint8_t engineering;
uint8_t flags;
-#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
+#define PRAM_FW_VERSION_OPTIMIZED (0x1 << 0)
#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
-#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */
+#define PRAM_FW_VERSION_STORM_ID (0x3 << 1)
#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
-#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */
+#define PRAM_FW_VERSION_BIG_ENDIEN (0x1 << 3)
#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
-#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 1 - E1H */
+#define PRAM_FW_VERSION_CHIP_VERSION (0x3 << 4)
#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
-#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */
+#define __PRAM_FW_VERSION_RESERVED0 (0x3 << 6)
#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
};
@@ -6072,107 +6419,98 @@ struct pram_fw_version
/*
* Ethernet slow path element
*/
-union protocol_common_specific_data
-{
- uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
- struct regpair phy_address /* SPE physical address */;
- struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */;
- struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */;
+union protocol_common_specific_data {
+ uint8_t protocol_data[8];
+ struct regpair phy_address;
+ struct regpair mac_config_addr;
+ struct afex_vif_list_ramrod_data afex_vif_list_data;
};
/*
* The send queue element
*/
-struct protocol_common_spe
-{
- struct spe_hdr hdr /* SPE header */;
- union protocol_common_specific_data data /* data specific to common protocol */;
+struct protocol_common_spe {
+ struct spe_hdr hdr;
+ union protocol_common_specific_data data;
};
/*
- * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$
+ * The data for the Set Timesync Ramrod
*/
-struct set_timesync_ramrod_data
-{
- uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */;
- uint8_t offset_cmd /* Timesync Offset Command */;
- uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */;
- uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */;
- uint32_t drift_adjust_period /* Drift Adjust Period (in us) */;
- struct regpair offset_delta /* Timesync Offset Delta (in ns) */;
+struct set_timesync_ramrod_data {
+ uint8_t drift_adjust_cmd;
+ uint8_t offset_cmd;
+ uint8_t add_sub_drift_adjust_value;
+ uint8_t drift_adjust_value;
+ uint32_t drift_adjust_period;
+ struct regpair offset_delta;
};
/*
* The send queue element
*/
-struct slow_path_element
-{
- struct spe_hdr hdr /* common data for all protocols */;
- struct regpair protocol_data /* additional data specific to the protocol */;
+struct slow_path_element {
+ struct spe_hdr hdr;
+ struct regpair protocol_data;
};
/*
- * Protocol-common statistics counter $$KEEP_ENDIANNESS$$
+ * Protocol-common statistics counter
*/
-struct stats_counter
-{
- uint16_t xstats_counter /* xstorm statistics counter */;
- uint16_t reserved0;
- uint32_t reserved1;
- uint16_t tstats_counter /* tstorm statistics counter */;
- uint16_t reserved2;
- uint32_t reserved3;
- uint16_t ustats_counter /* ustorm statistics counter */;
- uint16_t reserved4;
- uint32_t reserved5;
- uint16_t cstats_counter /* ustorm statistics counter */;
- uint16_t reserved6;
- uint32_t reserved7;
+struct stats_counter {
+ __le16 xstats_counter;
+ __le16 reserved0;
+ __le32 reserved1;
+ __le16 tstats_counter;
+ __le16 reserved2;
+ __le32 reserved3;
+ __le16 ustats_counter;
+ __le16 reserved4;
+ __le32 reserved5;
+ __le16 cstats_counter;
+ __le16 reserved6;
+ __le32 reserved7;
};
/*
- * $$KEEP_ENDIANNESS$$
+ *
*/
-struct stats_query_entry
-{
+struct stats_query_entry {
uint8_t kind;
- uint8_t index /* queue index */;
- uint16_t funcID /* the func the statistic will send to */;
- uint32_t reserved;
- struct regpair address /* pxp address */;
+ uint8_t index;
+ __le16 funcID;
+ __le32 reserved;
+ struct regpair address;
};
/*
- * statistic command $$KEEP_ENDIANNESS$$
+ * statistic command
*/
-struct stats_query_cmd_group
-{
+struct stats_query_cmd_group {
struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
};
/*
- * statistic command header $$KEEP_ENDIANNESS$$
+ * statistic command header
*/
-struct stats_query_header
-{
- uint8_t cmd_num /* command number */;
+struct stats_query_header {
+ uint8_t cmd_num;
uint8_t reserved0;
- uint16_t drv_stats_counter;
- uint32_t reserved1;
- struct regpair stats_counters_addrs /* stats counter */;
+ __le16 drv_stats_counter;
+ __le32 reserved1;
+ struct regpair stats_counters_addrs;
};
/*
* Types of statistcis query entry
*/
-enum stats_query_type
-{
+enum stats_query_type {
STATS_TYPE_QUEUE,
STATS_TYPE_PORT,
STATS_TYPE_PF,
@@ -6184,8 +6522,7 @@ enum stats_query_type
/*
* Indicate of the function status block state
*/
-enum status_block_state
-{
+enum status_block_state {
SB_DISABLED,
SB_ENABLED,
SB_CLEANED,
@@ -6195,8 +6532,7 @@ enum status_block_state
/*
* Storm IDs (including attentions for IGU related enums)
*/
-enum storm_id
-{
+enum storm_id {
USTORM_ID,
CSTORM_ID,
XSTORM_ID,
@@ -6208,19 +6544,17 @@ enum storm_id
/*
* Taffic types used in ETS and flow control algorithms
*/
-enum traffic_type
-{
- LLFC_TRAFFIC_TYPE_NW /* Networking */,
- LLFC_TRAFFIC_TYPE_FCOE /* FCoE */,
- LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */,
+enum traffic_type {
+ LLFC_TRAFFIC_TYPE_NW,
+ LLFC_TRAFFIC_TYPE_FCOE,
+ LLFC_TRAFFIC_TYPE_ISCSI,
MAX_TRAFFIC_TYPE};
/*
* zone A per-queue data
*/
-struct tstorm_queue_zone_data
-{
+struct tstorm_queue_zone_data {
struct regpair reserved[4];
};
@@ -6228,8 +6562,7 @@ struct tstorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct tstorm_vf_zone_data
-{
+struct tstorm_vf_zone_data {
struct regpair reserved;
};
@@ -6237,41 +6570,87 @@ struct tstorm_vf_zone_data
/*
* Add or Subtract Value for Set Timesync Ramrod
*/
-enum ts_add_sub_value
-{
- TS_SUB_VALUE /* Subtract Value */,
- TS_ADD_VALUE /* Add Value */,
+enum ts_add_sub_value {
+ TS_SUB_VALUE,
+ TS_ADD_VALUE,
MAX_TS_ADD_SUB_VALUE};
/*
* Drift-Adjust Commands for Set Timesync Ramrod
*/
-enum ts_drift_adjust_cmd
-{
- TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */,
- TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */,
- TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */,
+enum ts_drift_adjust_cmd {
+ TS_DRIFT_ADJUST_KEEP,
+ TS_DRIFT_ADJUST_SET,
+ TS_DRIFT_ADJUST_RESET,
MAX_TS_DRIFT_ADJUST_CMD};
/*
* Offset Commands for Set Timesync Ramrod
*/
-enum ts_offset_cmd
-{
- TS_OFFSET_KEEP /* Keep Offset at current values */,
- TS_OFFSET_INC /* Increase Offset by Offset Delta */,
- TS_OFFSET_DEC /* Decrease Offset by Offset Delta */,
+enum ts_offset_cmd {
+ TS_OFFSET_KEEP,
+ TS_OFFSET_INC,
+ TS_OFFSET_DEC,
MAX_TS_OFFSET_CMD};
+/*
+ * Input for measuring Pci Latency
+ */
+struct t_measure_pci_latency_ctrl {
+ struct regpair read_addr;
+#if defined(__BIG_ENDIAN)
+ uint8_t sleep;
+ uint8_t enable;
+ uint8_t func_id;
+ uint8_t read_size;
+#elif defined(__LITTLE_ENDIAN)
+ uint8_t read_size;
+ uint8_t func_id;
+ uint8_t enable;
+ uint8_t sleep;
+#endif
+#if defined(__BIG_ENDIAN)
+ uint16_t num_meas;
+ uint8_t reserved;
+ uint8_t period_10us;
+#elif defined(__LITTLE_ENDIAN)
+ uint8_t period_10us;
+ uint8_t reserved;
+ uint16_t num_meas;
+#endif
+};
+
+
+/*
+ * Input for measuring Pci Latency
+ */
+struct t_measure_pci_latency_data {
+#if defined(__BIG_ENDIAN)
+ uint16_t max_time_ns;
+ uint16_t min_time_ns;
+#elif defined(__LITTLE_ENDIAN)
+ uint16_t min_time_ns;
+ uint16_t max_time_ns;
+#endif
+#if defined(__BIG_ENDIAN)
+ uint16_t reserved;
+ uint16_t num_reads;
+#elif defined(__LITTLE_ENDIAN)
+ uint16_t num_reads;
+ uint16_t reserved;
+#endif
+ struct regpair sum_time_ns;
+};
+
+
/*
* zone A per-queue data
*/
-struct ustorm_queue_zone_data
-{
- union ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */;
+struct ustorm_queue_zone_data {
+ struct ustorm_eth_rx_producers eth_rx_producers;
struct regpair reserved[3];
};
@@ -6279,8 +6658,7 @@ struct ustorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct ustorm_vf_zone_data
-{
+struct ustorm_vf_zone_data {
struct regpair reserved;
};
@@ -6288,15 +6666,14 @@ struct ustorm_vf_zone_data
/*
* data per VF-PF channel
*/
-struct vf_pf_channel_data
-{
+struct vf_pf_channel_data {
#if defined(__BIG_ENDIAN)
uint16_t reserved0;
- uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
- uint8_t state /* channel state (ready / waiting for ack) */;
+ uint8_t valid;
+ uint8_t state;
#elif defined(__LITTLE_ENDIAN)
- uint8_t state /* channel state (ready / waiting for ack) */;
- uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
+ uint8_t state;
+ uint8_t valid;
uint16_t reserved0;
#endif
uint32_t reserved1;
@@ -6306,18 +6683,16 @@ struct vf_pf_channel_data
/*
* State of VF-PF channel
*/
-enum vf_pf_channel_state
-{
- VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */,
- VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */,
+enum vf_pf_channel_state {
+ VF_PF_CHANNEL_STATE_READY,
+ VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
MAX_VF_PF_CHANNEL_STATE};
/*
* vif_list_rule_kind
*/
-enum vif_list_rule_kind
-{
+enum vif_list_rule_kind {
VIF_LIST_RULE_SET,
VIF_LIST_RULE_GET,
VIF_LIST_RULE_CLEAR_ALL,
@@ -6328,8 +6703,7 @@ enum vif_list_rule_kind
/*
* zone A per-queue data
*/
-struct xstorm_queue_zone_data
-{
+struct xstorm_queue_zone_data {
struct regpair reserved[4];
};
@@ -6337,10 +6711,8 @@ struct xstorm_queue_zone_data
/*
* zone B per-VF data
*/
-struct xstorm_vf_zone_data
-{
+struct xstorm_vf_zone_data {
struct regpair reserved;
};
-
#endif /* ECORE_HSI_H */
diff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c
index 5ac22e725..ceac82815 100644
--- a/drivers/net/bnx2x/ecore_sp.c
+++ b/drivers/net/bnx2x/ecore_sp.c
@@ -3524,13 +3524,6 @@ static int ecore_setup_rss(struct bnx2x_softc *sc,
data->capabilities |=
ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
- if (ECORE_TEST_BIT(ECORE_RSS_TUNNELING, &p->rss_flags)) {
- data->udp_4tuple_dst_port_mask =
- ECORE_CPU_TO_LE16(p->tunnel_mask);
- data->udp_4tuple_dst_port_value =
- ECORE_CPU_TO_LE16(p->tunnel_value);
- }
-
/* Hashing mask */
data->rss_result_mask = p->rss_result_mask;
@@ -5088,8 +5081,6 @@ static int ecore_func_send_start(struct bnx2x_softc *sc,
rdata->sd_vlan_tag = ECORE_CPU_TO_LE16(start_params->sd_vlan_tag);
rdata->path_id = ECORE_PATH_ID(sc);
rdata->network_cos_mode = start_params->network_cos_mode;
- rdata->gre_tunnel_mode = start_params->gre_tunnel_mode;
- rdata->gre_tunnel_rss = start_params->gre_tunnel_rss;
/*
* No need for an explicit memory barrier here as long we would
@@ -5229,7 +5220,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st
rdata->dcb_enabled = tx_start_params->dcb_enabled;
rdata->dcb_version = tx_start_params->dcb_version;
- rdata->dont_add_pri_0 = tx_start_params->dont_add_pri_0;
+ rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;
for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
rdata->traffic_type_to_priority_cos[i] =
--
2.18.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 3/3] net/bnx2x: update to latest FW 7.13.11
2019-09-06 7:25 [dpdk-dev] [PATCH 0/5] net/bnx2x: update to latest FW Rasesh Mody
` (13 preceding siblings ...)
2019-10-02 19:14 ` [dpdk-dev] [PATCH v3 2/3] net/bnx2x: update HSI code Rasesh Mody
@ 2019-10-02 19:14 ` Rasesh Mody
14 siblings, 0 replies; 29+ messages in thread
From: Rasesh Mody @ 2019-10-02 19:14 UTC (permalink / raw)
To: dev, jerinj, ferruh.yigit; +Cc: Rasesh Mody, GR-Everest-DPDK-Dev
Use latest firmware 7.13.11.
Some of the fixes included with this FW are as following:
- Packets from a VF with pvid configured which were sent with a
different vlan were transmitted instead of being discarded.
- In some multi-function configurations, inter-PF and inter-VF
Tx switching is incorrectly enabled.
- Wrong assert code in FLR final cleanup in case it is sent not
after FLR.
- Chip may stall in very rare cases under heavy traffic with FW GRO
enabled.
- VF malicious notification error fixes.
- Default gre tunnel to IPGRE which allows proper RSS for IPGRE
packets, L2GRE traffic will reach single queue.
- Removes unnecessary internal mem config, latest FW performs this
autonomously.
Update the PMD version to 1.1.0.1.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
doc/guides/nics/bnx2x.rst | 4 +-
drivers/net/bnx2x/bnx2x.c | 40 +---
drivers/net/bnx2x/bnx2x.h | 5 +-
drivers/net/bnx2x/ecore_fw_defs.h | 252 ++++++++++++-----------
drivers/net/bnx2x/ecore_hsi.h | 2 +-
drivers/net/bnx2x/ecore_init.h | 214 ++++++++++----------
drivers/net/bnx2x/ecore_init_ops.h | 192 ++++++++----------
drivers/net/bnx2x/ecore_mfw_req.h | 11 +-
drivers/net/bnx2x/ecore_sp.c | 39 ++--
drivers/net/bnx2x/ecore_sp.h | 308 ++++++++++++++++++++++++-----
10 files changed, 640 insertions(+), 427 deletions(-)
diff --git a/doc/guides/nics/bnx2x.rst b/doc/guides/nics/bnx2x.rst
index 0a16f0c70..67d765af8 100644
--- a/doc/guides/nics/bnx2x.rst
+++ b/doc/guides/nics/bnx2x.rst
@@ -67,9 +67,9 @@ Supported QLogic NICs
Prerequisites
-------------
-- Requires firmware version **7.2.51.0**. It is included in most of the
+- Requires firmware version **7.13.11.0**. It is included in most of the
standard Linux distros. If it is not available visit
- `linux-firmware git repository <https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/plain/bnx2x/bnx2x-e2-7.2.51.0.fw>`_
+ `linux-firmware git repository <https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/plain/bnx2x/bnx2x-e2-7.13.11.0.fw>`_
to get the required firmware.
Pre-Installation Configuration
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 010e16088..e1dfe602c 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -29,8 +29,8 @@
#define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
#define BNX2X_PMD_VERSION_MAJOR 1
-#define BNX2X_PMD_VERSION_MINOR 0
-#define BNX2X_PMD_VERSION_REVISION 7
+#define BNX2X_PMD_VERSION_MINOR 1
+#define BNX2X_PMD_VERSION_REVISION 0
#define BNX2X_PMD_VERSION_PATCH 1
static inline const char *
@@ -5231,20 +5231,6 @@ static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
{
int i;
- if (IS_MF_SI(sc)) {
-/*
- * In switch independent mode, the TSTORM needs to accept
- * packets that failed classification, since approximate match
- * mac addresses aren't written to NIG LLH.
- */
- REG_WR8(sc,
- (BAR_TSTRORM_INTMEM +
- TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
- } else
- REG_WR8(sc,
- (BAR_TSTRORM_INTMEM +
- TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
-
/*
* Zero this manually as its initialization is currently missing
* in the initTool.
@@ -5798,15 +5784,12 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc)
VNICS_PER_PATH(sc));
/* RSS configuration object */
- ecore_init_rss_config_obj(&sc->rss_conf_obj,
- sc->fp[0].cl_id,
- sc->fp[0].index,
- SC_FUNC(sc),
- SC_FUNC(sc),
+ ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
+ sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
BNX2X_SP(sc, rss_rdata),
(rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
- ECORE_FILTER_RSS_CONF_PENDING,
- &sc->sp_state, ECORE_OBJ_TYPE_RX);
+ ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
+ ECORE_OBJ_TYPE_RX);
}
/*
@@ -5835,9 +5818,6 @@ static int bnx2x_func_start(struct bnx2x_softc *sc)
start_params->network_cos_mode = FW_WRR;
}
- start_params->gre_tunnel_mode = 0;
- start_params->gre_tunnel_rss = 0;
-
return ecore_func_state_change(sc, &func_params);
}
@@ -9651,8 +9631,8 @@ static void bnx2x_init_rte(struct bnx2x_softc *sc)
}
#define FW_HEADER_LEN 104
-#define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
-#define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
+#define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
+#define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
void bnx2x_load_firmware(struct bnx2x_softc *sc)
{
@@ -10368,7 +10348,7 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
/* clean the DMAE memory */
sc->dmae_ready = 1;
- ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
+ ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
@@ -11580,7 +11560,7 @@ static void bnx2x_reset_func(struct bnx2x_softc *sc)
ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
ilt_cli.client_num = ILT_CLIENT_TM;
- ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
+ ecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
}
/* this assumes that reset_port() called before reset_func() */
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 054d95424..43c60408a 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -83,9 +83,6 @@
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif
-#ifndef ARRSIZE
-#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-#endif
#ifndef DIV_ROUND_UP
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#endif
@@ -1020,6 +1017,8 @@ struct bnx2x_pci_cap {
uint16_t addr;
};
+struct ecore_ilt;
+
struct bnx2x_vfdb;
/* Top level device private data structure. */
diff --git a/drivers/net/bnx2x/ecore_fw_defs.h b/drivers/net/bnx2x/ecore_fw_defs.h
index 5984acd94..5397a701a 100644
--- a/drivers/net/bnx2x/ecore_fw_defs.h
+++ b/drivers/net/bnx2x/ecore_fw_defs.h
@@ -13,170 +13,170 @@
#ifndef ECORE_FW_DEFS_H
#define ECORE_FW_DEFS_H
-
-#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base)
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
- (IRO[147].base + ((assertListEntry) * IRO[147].m1))
+ (IRO[151].base + ((assertListEntry) * IRO[151].m1))
#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
- (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
- IRO[153].m2))
+ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
+ IRO[157].m2))
#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
- (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
- IRO[154].m2))
-#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
- (IRO[155].base + ((vfId) * IRO[155].m1))
-#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
- (IRO[156].base + ((vfId) * IRO[156].m1))
-#define CSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[150].base + ((funcId) * IRO[150].m1))
+ (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
+ IRO[158].m2))
#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
- (IRO[159].base + ((funcId) * IRO[159].m1))
+ (IRO[163].base + ((funcId) * IRO[163].m1))
#define CSTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[149].base + ((funcId) * IRO[149].m1))
+ (IRO[153].base + ((funcId) * IRO[153].m1))
#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
- (IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))
+ (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
- (IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \
- * IRO[138].m2) + ((sbId) * IRO[138].m3))
-#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
+ (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
+ * IRO[142].m2) + ((sbId) * IRO[142].m3))
+#define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
- (IRO[317].base + ((pfId) * IRO[317].m1))
+ (IRO[323].base + ((pfId) * IRO[323].m1))
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
- (IRO[318].base + ((pfId) * IRO[318].m1))
+ (IRO[324].base + ((pfId) * IRO[324].m1))
#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
- (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))
+ (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
- (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))
+ (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
- (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))
+ (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
- (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))
+ (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
- (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
-#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
(IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
+ (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
- (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))
+ (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
- (IRO[316].base + ((pfId) * IRO[316].m1))
+ (IRO[322].base + ((pfId) * IRO[322].m1))
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[308].base + ((pfId) * IRO[308].m1))
+ (IRO[314].base + ((pfId) * IRO[314].m1))
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[307].base + ((pfId) * IRO[307].m1))
+ (IRO[313].base + ((pfId) * IRO[313].m1))
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[306].base + ((pfId) * IRO[306].m1))
+ (IRO[312].base + ((pfId) * IRO[312].m1))
#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[151].base + ((funcId) * IRO[151].m1))
+ (IRO[155].base + ((funcId) * IRO[155].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
- (IRO[142].base + ((pfId) * IRO[142].m1))
+ (IRO[146].base + ((pfId) * IRO[146].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
- (IRO[143].base + ((pfId) * IRO[143].m1))
+ (IRO[147].base + ((pfId) * IRO[147].m1))
#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
- (IRO[141].base + ((pfId) * IRO[141].m1))
-#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)
+ (IRO[145].base + ((pfId) * IRO[145].m1))
+#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
- (IRO[144].base + ((pfId) * IRO[144].m1))
-#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)
+ (IRO[148].base + ((pfId) * IRO[148].m1))
+#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
- (IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))
+ (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
- (IRO[133].base + ((sbId) * IRO[133].m1))
+ (IRO[137].base + ((sbId) * IRO[137].m1))
#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
- (IRO[134].base + ((sbId) * IRO[134].m1))
+ (IRO[138].base + ((sbId) * IRO[138].m1))
#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
- (IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))
+ (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
- (IRO[132].base + ((sbId) * IRO[132].m1))
-#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)
+ (IRO[136].base + ((sbId) * IRO[136].m1))
+#define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
- (IRO[137].base + ((sbId) * IRO[137].m1))
-#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)
+ (IRO[141].base + ((sbId) * IRO[141].m1))
+#define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
+#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
+ (IRO[159].base + ((vfId) * IRO[159].m1))
+#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
+ (IRO[160].base + ((vfId) * IRO[160].m1))
#define CSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[150].base + ((funcId) * IRO[150].m1))
-#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base)
+ (IRO[154].base + ((funcId) * IRO[154].m1))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
- (IRO[203].base + ((pfId) * IRO[203].m1))
+ (IRO[207].base + ((pfId) * IRO[207].m1))
#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[101].base + ((assertListEntry) * IRO[101].m1))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
- (IRO[201].base + ((pfId) * IRO[201].m1))
+ (IRO[205].base + ((pfId) * IRO[205].m1))
#define TSTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[103].base + ((funcId) * IRO[103].m1))
+ (IRO[107].base + ((funcId) * IRO[107].m1))
#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
- (IRO[272].base + ((pfId) * IRO[272].m1))
+ (IRO[278].base + ((pfId) * IRO[278].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
+ (IRO[279].base + ((pfId) * IRO[279].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
+ (IRO[280].base + ((pfId) * IRO[280].m1))
+#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
+ (IRO[281].base + ((pfId) * IRO[281].m1))
#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[271].base + ((pfId) * IRO[271].m1))
+ (IRO[277].base + ((pfId) * IRO[277].m1))
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[270].base + ((pfId) * IRO[270].m1))
+ (IRO[276].base + ((pfId) * IRO[276].m1))
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[269].base + ((pfId) * IRO[269].m1))
+ (IRO[275].base + ((pfId) * IRO[275].m1))
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
- (IRO[268].base + ((pfId) * IRO[268].m1))
+ (IRO[274].base + ((pfId) * IRO[274].m1))
#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
- (IRO[278].base + ((pfId) * IRO[278].m1))
+ (IRO[284].base + ((pfId) * IRO[284].m1))
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
- (IRO[264].base + ((pfId) * IRO[264].m1))
+ (IRO[270].base + ((pfId) * IRO[270].m1))
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[265].base + ((pfId) * IRO[265].m1))
+ (IRO[271].base + ((pfId) * IRO[271].m1))
#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[266].base + ((pfId) * IRO[266].m1))
+ (IRO[272].base + ((pfId) * IRO[272].m1))
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
- (IRO[267].base + ((pfId) * IRO[267].m1))
+ (IRO[273].base + ((pfId) * IRO[273].m1))
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
- (IRO[202].base + ((pfId) * IRO[202].m1))
+ (IRO[206].base + ((pfId) * IRO[206].m1))
#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[105].base + ((funcId) * IRO[105].m1))
+ (IRO[109].base + ((funcId) * IRO[109].m1))
#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
- (IRO[217].base + ((pfId) * IRO[217].m1))
+ (IRO[223].base + ((pfId) * IRO[223].m1))
#define TSTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[104].base + ((funcId) * IRO[104].m1))
-#define USTORM_AGG_DATA_OFFSET (IRO[206].base)
-#define USTORM_AGG_DATA_SIZE (IRO[206].size)
-#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base)
+ (IRO[108].base + ((funcId) * IRO[108].m1))
+#define USTORM_AGG_DATA_OFFSET (IRO[212].base)
+#define USTORM_AGG_DATA_SIZE (IRO[212].size)
+#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
- (IRO[176].base + ((assertListEntry) * IRO[176].m1))
-#define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \
- (IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * IRO[205].m2))
+ (IRO[180].base + ((assertListEntry) * IRO[180].m1))
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
- (IRO[183].base + ((portId) * IRO[183].m1))
+ (IRO[187].base + ((portId) * IRO[187].m1))
#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
- (IRO[319].base + ((pfId) * IRO[319].m1))
+ (IRO[325].base + ((pfId) * IRO[325].m1))
#define USTORM_FUNC_EN_OFFSET(funcId) \
- (IRO[178].base + ((funcId) * IRO[178].m1))
+ (IRO[182].base + ((funcId) * IRO[182].m1))
#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
- (IRO[283].base + ((pfId) * IRO[283].m1))
+ (IRO[289].base + ((pfId) * IRO[289].m1))
#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
- (IRO[284].base + ((pfId) * IRO[284].m1))
+ (IRO[290].base + ((pfId) * IRO[290].m1))
#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
- (IRO[288].base + ((pfId) * IRO[288].m1))
+ (IRO[294].base + ((pfId) * IRO[294].m1))
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
- (IRO[285].base + ((pfId) * IRO[285].m1))
+ (IRO[291].base + ((pfId) * IRO[291].m1))
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[281].base + ((pfId) * IRO[281].m1))
+ (IRO[287].base + ((pfId) * IRO[287].m1))
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[280].base + ((pfId) * IRO[280].m1))
+ (IRO[286].base + ((pfId) * IRO[286].m1))
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[279].base + ((pfId) * IRO[279].m1))
+ (IRO[285].base + ((pfId) * IRO[285].m1))
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
- (IRO[282].base + ((pfId) * IRO[282].m1))
+ (IRO[288].base + ((pfId) * IRO[288].m1))
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
- (IRO[286].base + ((pfId) * IRO[286].m1))
+ (IRO[292].base + ((pfId) * IRO[292].m1))
#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
- (IRO[287].base + ((pfId) * IRO[287].m1))
+ (IRO[293].base + ((pfId) * IRO[293].m1))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
- (IRO[182].base + ((pfId) * IRO[182].m1))
+ (IRO[186].base + ((pfId) * IRO[186].m1))
#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
- (IRO[180].base + ((funcId) * IRO[180].m1))
+ (IRO[184].base + ((funcId) * IRO[184].m1))
#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
- (IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \
- IRO[209].m2))
+ (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
+ IRO[215].m2))
#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
- (IRO[210].base + ((qzoneId) * IRO[210].m1))
-#define USTORM_TPA_BTR_OFFSET (IRO[207].base)
-#define USTORM_TPA_BTR_SIZE (IRO[207].size)
+ (IRO[216].base + ((qzoneId) * IRO[216].m1))
+#define USTORM_TPA_BTR_OFFSET (IRO[213].base)
+#define USTORM_TPA_BTR_SIZE (IRO[213].size)
#define USTORM_VF_TO_PF_OFFSET(funcId) \
- (IRO[179].base + ((funcId) * IRO[179].m1))
+ (IRO[183].base + ((funcId) * IRO[183].m1))
#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
@@ -189,39 +189,39 @@
#define XSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[47].base + ((funcId) * IRO[47].m1))
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
- (IRO[296].base + ((pfId) * IRO[296].m1))
+ (IRO[302].base + ((pfId) * IRO[302].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
- (IRO[299].base + ((pfId) * IRO[299].m1))
+ (IRO[305].base + ((pfId) * IRO[305].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
- (IRO[300].base + ((pfId) * IRO[300].m1))
+ (IRO[306].base + ((pfId) * IRO[306].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
- (IRO[301].base + ((pfId) * IRO[301].m1))
+ (IRO[307].base + ((pfId) * IRO[307].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
- (IRO[302].base + ((pfId) * IRO[302].m1))
+ (IRO[308].base + ((pfId) * IRO[308].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
- (IRO[303].base + ((pfId) * IRO[303].m1))
+ (IRO[309].base + ((pfId) * IRO[309].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
- (IRO[304].base + ((pfId) * IRO[304].m1))
+ (IRO[310].base + ((pfId) * IRO[310].m1))
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
- (IRO[305].base + ((pfId) * IRO[305].m1))
+ (IRO[311].base + ((pfId) * IRO[311].m1))
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
- (IRO[295].base + ((pfId) * IRO[295].m1))
+ (IRO[301].base + ((pfId) * IRO[301].m1))
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
- (IRO[294].base + ((pfId) * IRO[294].m1))
+ (IRO[300].base + ((pfId) * IRO[300].m1))
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
- (IRO[293].base + ((pfId) * IRO[293].m1))
+ (IRO[299].base + ((pfId) * IRO[299].m1))
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
- (IRO[298].base + ((pfId) * IRO[298].m1))
+ (IRO[304].base + ((pfId) * IRO[304].m1))
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
- (IRO[297].base + ((pfId) * IRO[297].m1))
+ (IRO[303].base + ((pfId) * IRO[303].m1))
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
- (IRO[292].base + ((pfId) * IRO[292].m1))
+ (IRO[298].base + ((pfId) * IRO[298].m1))
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
- (IRO[291].base + ((pfId) * IRO[291].m1))
+ (IRO[297].base + ((pfId) * IRO[297].m1))
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
- (IRO[290].base + ((pfId) * IRO[290].m1))
+ (IRO[296].base + ((pfId) * IRO[296].m1))
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
- (IRO[289].base + ((pfId) * IRO[289].m1))
+ (IRO[295].base + ((pfId) * IRO[295].m1))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
(IRO[44].base + ((pfId) * IRO[44].m1))
#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
@@ -234,15 +234,18 @@
#define XSTORM_SPQ_PROD_OFFSET(funcId) \
(IRO[31].base + ((funcId) * IRO[31].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
- (IRO[211].base + ((portId) * IRO[211].m1))
+ (IRO[217].base + ((portId) * IRO[217].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
- (IRO[212].base + ((portId) * IRO[212].m1))
+ (IRO[218].base + ((portId) * IRO[218].m1))
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
- (IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \
- IRO[214].m2))
+ (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
+ IRO[220].m2))
#define XSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[48].base + ((funcId) * IRO[48].m1))
-#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base)
+#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+
+/* eth hsi version */
+#define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)
/* Ethernet Ring parameters */
@@ -250,19 +253,27 @@
#define FIRST_BD_IN_PKT 0
#define PARSE_BD_INDEX 1
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
+#define U_ETH_NUM_OF_SGES_TO_FETCH 8
+#define U_ETH_MAX_SGES_FOR_PACKET 3
/* Rx ring params */
#define U_ETH_LOCAL_BD_RING_SIZE 8
+#define U_ETH_LOCAL_SGE_RING_SIZE 10
#define U_ETH_SGL_SIZE 8
/* The fw will padd the buffer with this value, so the IP header \
will be align to 4 Byte */
#define IP_HEADER_ALIGNMENT_PADDING 2
+#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
+
#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
#define U_ETH_UNDEFINED_Q 0xFF
@@ -281,20 +292,25 @@
#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
/* Maximal L2 clients supported */
+#define ETH_MAX_RX_CLIENTS_E1 18
#define ETH_MAX_RX_CLIENTS_E1H 28
#define ETH_MAX_RX_CLIENTS_E2 152
/* Maximal statistics client Ids */
+#define MAX_STAT_COUNTER_ID_E1 36
#define MAX_STAT_COUNTER_ID_E1H 56
#define MAX_STAT_COUNTER_ID_E2 140
+#define MAX_MAC_CREDIT_E1 192 /* Per Chip */
#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
#define MAX_MAC_CREDIT_E2 272 /* Per Path */
+#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */
#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
#define MAX_VLAN_CREDIT_E2 272 /* Per Path */
/* Maximal aggregation queues supported */
+#define ETH_MAX_AGGREGATION_QUEUES_E1 32
#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
@@ -302,6 +318,8 @@
#define ETH_NUM_OF_MCAST_ENGINES_E2 72
#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
+#define ETH_MIN_RX_CQES_WITH_TPA_E1 \
+ (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)
#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
(ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
@@ -357,6 +375,7 @@
/* used for Host Coallescing */
#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
+#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
@@ -370,7 +389,7 @@
#define MAX_COS_NUMBER 4
#define MAX_TRAFFIC_TYPES 8
#define MAX_PFC_PRIORITIES 8
-
+#define MAX_VLAN_PRIORITIES 8
/* used by array traffic_type_to_priority[] to mark traffic type \
that is not mapped to priority*/
#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
@@ -397,5 +416,4 @@
#define MAX_NUM_FCOE_TASKS_PER_ENGINE \
4096 /*Each port can have at max 1 function*/
-
#endif /* ECORE_FW_DEFS_H */
diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index 2728deb1d..aaf8b048e 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -5508,7 +5508,7 @@ struct afex_vif_list_ramrod_data {
*
*/
struct c2s_pri_trans_table_entry {
- uint8_t val[8];
+ uint8_t val[MAX_VLAN_PRIORITIES];
};
diff --git a/drivers/net/bnx2x/ecore_init.h b/drivers/net/bnx2x/ecore_init.h
index 97dfe69b5..4e348612a 100644
--- a/drivers/net/bnx2x/ecore_init.h
+++ b/drivers/net/bnx2x/ecore_init.h
@@ -26,10 +26,6 @@ enum {
OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */
OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
- OP_IF_PHASE,
- OP_RT,
- OP_DELAY,
- OP_VERIFY,
OP_MAX
};
@@ -86,17 +82,6 @@ struct op_if_mode {
uint32_t mode_bit_map;
};
-struct op_if_phase {
- uint32_t op:8;
- uint32_t cmd_offset:24;
- uint32_t phase_bit_map;
-};
-
-struct op_delay {
- uint32_t op:8;
- uint32_t reserved:24;
- uint32_t delay;
-};
union init_op {
struct op_read read;
@@ -105,8 +90,6 @@ union init_op {
struct op_zero zero;
struct raw_op raw;
struct op_if_mode if_mode;
- struct op_if_phase if_phase;
- struct op_delay delay;
};
@@ -187,12 +170,7 @@ enum {
NUM_OF_INIT_BLOCKS
};
-
-
-
-
-
-
+#include "bnx2x.h"
/* Vnics per mode */
#define ECORE_PORT2_MODE_NUM_VNICS 4
@@ -239,7 +217,7 @@ static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint3
/* update parameters for 4port mode */
if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
- if (PORT_ID(sc)) {
+ if (SC_PORT(sc)) {
curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
}
@@ -248,7 +226,7 @@ static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint3
/* change queue mapping for each VNIC */
for (vnic = 0; vnic < num_vnics; vnic++) {
uint32_t pf_q_num =
- ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
+ ECORE_PF_Q_NUM(q_num, SC_PORT(sc), vnic);
uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
/* overwrite queue->VOQ mapping */
@@ -427,7 +405,11 @@ static inline void ecore_init_min(const struct cmng_init_input *input_data,
tFair = T_FAIR_COEF / input_data->port_rate;
/* this is the threshold below which we won't arm the timer anymore */
- pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
+ pdata->fair_vars.fair_threshold = QM_ARB_BYTES +
+ input_data->fairness_thr;
+
+ /*New limitation - minimal packet size to cause timeout to be armed */
+ pdata->fair_vars.size_thr = input_data->size_thr;
/*
* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
@@ -469,6 +451,7 @@ static inline void ecore_init_min(const struct cmng_init_input *input_data,
}
static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
+ uint32_t r_param __rte_unused,
struct cmng_init *ram_data)
{
uint32_t vnic, cos;
@@ -507,7 +490,9 @@ static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
}
}
-static inline void ecore_init_safc(struct cmng_init *ram_data)
+static inline void
+ecore_init_safc(const struct cmng_init_input *input_data __rte_unused,
+ struct cmng_init *ram_data)
{
/* in microSeconds */
ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
@@ -518,7 +503,7 @@ static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
struct cmng_init *ram_data)
{
uint32_t r_param;
- ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
+ ECORE_MEMSET(ram_data, 0, sizeof(struct cmng_init));
ram_data->port.flags = input_data->flags;
@@ -529,8 +514,8 @@ static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
r_param = BITS_TO_BYTES(input_data->port_rate);
ecore_init_max(input_data, r_param, ram_data);
ecore_init_min(input_data, r_param, ram_data);
- ecore_init_fw_wrr(input_data, ram_data);
- ecore_init_safc(ram_data);
+ ecore_init_fw_wrr(input_data, r_param, ram_data);
+ ecore_init_safc(input_data, ram_data);
}
@@ -585,25 +570,25 @@ struct src_ent {
/****************************************************************************
* Parity configuration
****************************************************************************/
-#define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK, \
block##_REG_##block##_PRTY_STS_CLR, \
- en_mask, {m1h, m2, m3}, #block \
+ en_mask, {m1, m1h, m2, m3}, #block \
}
-#define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK_0, \
block##_REG_##block##_PRTY_STS_CLR_0, \
- en_mask, {m1h, m2, m3}, #block"_0" \
+ en_mask, {m1, m1h, m2, m3}, #block "_0" \
}
-#define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \
+#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
{ \
block##_REG_##block##_PRTY_MASK_1, \
block##_REG_##block##_PRTY_STS_CLR_1, \
- en_mask, {m1h, m2, m3}, #block"_1" \
+ en_mask, {m1, m1h, m2, m3}, #block "_1" \
}
static const struct {
@@ -611,6 +596,7 @@ static const struct {
uint32_t sts_clr_addr;
uint32_t en_mask; /* Mask to enable parity attentions */
struct {
+ uint32_t e1; /* 57710 */
uint32_t e1h; /* 57711 */
uint32_t e2; /* 57712 */
uint32_t e3; /* 578xx */
@@ -620,63 +606,67 @@ static const struct {
*/
} ecore_blocks_parity_data[] = {
/* bit 19 masked */
- /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
+ /* REG_WR(sc, PXP_REG_PXP_PRTY_MASK, 0x80000); */
/* bit 5,18,20-31 */
- /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
+ /* REG_WR(sc, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
/* bit 5 */
- /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
- /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
- /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
+ /* REG_WR(sc, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
+ /* REG_WR(sc, HC_REG_HC_PRTY_MASK, 0x0); */
+ /* REG_WR(sc, MISC_REG_MISC_PRTY_MASK, 0x0); */
/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
* want to handle "system kill" flow at the moment.
*/
- BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,
+ BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
0x7ffffff),
- BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff,
+ BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff),
- BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),
- BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),
- BLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),
- BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0xff, 0xffff),
- BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
- BLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),
- BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),
- BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),
- BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
+ BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
+ BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
+ BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
+ BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
+ BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
+ BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
+ BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
+ BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
+ BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
- {0xf, 0xf, 0xf}, "UPB"},
+ {0xf, 0xf, 0xf, 0xf}, "UPB"},
{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
- {0xf, 0xf, 0xf}, "XPB"},
- BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
- BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),
- BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
- BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
- BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
- BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
- BLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),
- BLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),
- BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
- BLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
- BLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
- BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),
- BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),
- BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
- BLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),
+ {0xf, 0xf, 0xf, 0xf}, "XPB"},
+ BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
+ BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
+ BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
+ BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
+ BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
+ BLOCK_PRTY_INFO(PRS, (1 << 6), 0xff, 0xff, 0xff, 0xff),
+ BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
+ BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
+ BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
+ BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+ BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
+ BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
+ BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
+ BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff),
+ BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
};
@@ -685,45 +675,59 @@ static const struct {
* [30] MCP Latched ump_tx_parity
* [31] MCP Latched scpad_parity
*/
-#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
+#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
+
+#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
+ (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
/* Below registers control the MCP parity attention output. When
* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
* enabled, when cleared - disabled.
*/
-static const uint32_t mcp_attn_ctl_regs[] = {
- MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
- MISC_REG_AEU_ENABLE4_NIG_0,
- MISC_REG_AEU_ENABLE4_PXP_0,
- MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
- MISC_REG_AEU_ENABLE4_NIG_1,
- MISC_REG_AEU_ENABLE4_PXP_1
+static const struct {
+ uint32_t addr;
+ uint32_t bits;
+} mcp_attn_ctl_regs[] = {
+ { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
+ MISC_AEU_ENABLE_MCP_PRTY_BITS },
+ { MISC_REG_AEU_ENABLE4_NIG_0,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_PXP_0,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
+ MISC_AEU_ENABLE_MCP_PRTY_BITS },
+ { MISC_REG_AEU_ENABLE4_NIG_1,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
+ { MISC_REG_AEU_ENABLE4_PXP_1,
+ MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
};
static inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable)
{
- uint32_t i;
+ unsigned int i;
uint32_t reg_val;
- for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
- reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);
+ for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
+ reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);
if (enable)
- reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
+ reg_val |= mcp_attn_ctl_regs[i].bits;
else
- reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
+ reg_val &= ~mcp_attn_ctl_regs[i].bits;
- REG_WR(sc, mcp_attn_ctl_regs[i], reg_val);
+ REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val);
}
}
static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
{
- if (CHIP_IS_E1H(sc))
+ if (CHIP_IS_E1(sc))
+ return ecore_blocks_parity_data[idx].reg_mask.e1;
+ else if (CHIP_IS_E1H(sc))
return ecore_blocks_parity_data[idx].reg_mask.e1h;
else if (CHIP_IS_E2(sc))
return ecore_blocks_parity_data[idx].reg_mask.e2;
@@ -733,9 +737,9 @@ static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
if (dis_mask) {
@@ -748,7 +752,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
}
/* Disable MCP parity attentions */
- ecore_set_mcp_parity(sc, FALSE);
+ ecore_set_mcp_parity(sc, false);
}
/**
@@ -756,7 +760,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
*/
static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
uint32_t reg_val, mcp_aeu_bits =
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
@@ -769,7 +773,7 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
if (reg_mask) {
@@ -799,9 +803,9 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
{
- uint32_t i;
+ unsigned int i;
- for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+ for (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
if (reg_mask)
@@ -810,7 +814,7 @@ static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
}
/* Enable MCP parity attentions */
- ecore_set_mcp_parity(sc, TRUE);
+ ecore_set_mcp_parity(sc, true);
}
diff --git a/drivers/net/bnx2x/ecore_init_ops.h b/drivers/net/bnx2x/ecore_init_ops.h
index 733ad1aa8..0945e7999 100644
--- a/drivers/net/bnx2x/ecore_init_ops.h
+++ b/drivers/net/bnx2x/ecore_init_ops.h
@@ -28,16 +28,19 @@ static void ecore_init_str_wr(struct bnx2x_softc *sc, uint32_t addr,
REG_WR(sc, addr + i*4, data[i]);
}
-static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len)
+static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr,
+ uint32_t len, uint8_t wb __rte_unused)
{
if (DMAE_READY(sc))
ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
- else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
}
static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,
- uint32_t len)
+ uint32_t len, uint8_t wb)
{
uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
uint32_t buf_len32 = buf_len/4;
@@ -48,7 +51,7 @@ static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,
for (i = 0; i < len; i += buf_len32) {
uint32_t cur_len = min(buf_len32, len - i);
- ecore_write_big_buf(sc, addr + i*4, cur_len);
+ ecore_write_big_buf(sc, addr + i * 4, cur_len, wb);
}
}
@@ -57,7 +60,9 @@ static void ecore_write_big_buf_wb(struct bnx2x_softc *sc, uint32_t addr, uint32
if (DMAE_READY(sc))
ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
- else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
}
static void ecore_init_wr_64(struct bnx2x_softc *sc, uint32_t addr,
@@ -135,9 +140,12 @@ static void ecore_init_wr_wb(struct bnx2x_softc *sc, uint32_t addr,
if (DMAE_READY(sc))
VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
- else ecore_init_str_wr(sc, addr, data, len);
+ /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
+ else
+ ecore_init_str_wr(sc, addr, data, len);
}
+
static void ecore_wr_64(struct bnx2x_softc *sc, uint32_t reg, uint32_t val_lo,
uint32_t val_hi)
{
@@ -215,11 +223,14 @@ static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t st
ecore_init_wr_wb(sc, addr, data, len);
break;
case OP_ZR:
+ ecore_init_fill(sc, addr, 0, op->zero.len, 0);
+ break;
case OP_WB_ZR:
- ecore_init_fill(sc, addr, 0, op->zero.len);
+ ecore_init_fill(sc, addr, 0, op->zero.len, 1);
break;
case OP_ZP:
- ecore_init_wr_zp(sc, addr, len, op->arr_wr.data_off);
+ ecore_init_wr_zp(sc, addr, len,
+ op->arr_wr.data_off);
break;
case OP_WR_64:
ecore_init_wr_64(sc, addr, data, len);
@@ -241,11 +252,6 @@ static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t st
op->if_mode.mode_bit_map) == 0)
op_idx += op->if_mode.cmd_offset;
break;
- /* the following opcodes are unused at the moment. */
- case OP_IF_PHASE:
- case OP_RT:
- case OP_DELAY:
- case OP_VERIFY:
default:
/* Should never get here! */
@@ -490,7 +496,7 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
- if (CHIP_IS_E1H(sc) && (r_order == MAX_RD_ORD))
+ if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))
REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
if (CHIP_IS_E3(sc))
@@ -500,31 +506,33 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
else
REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
- /* MPS w_order optimal TH presently TH
- * 128 0 0 2
- * 256 1 1 3
- * >=512 2 2 3
- */
- /* DMAE is special */
- if (!CHIP_IS_E1H(sc)) {
- /* E2 can use optimal TH */
- val = w_order;
- REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
- } else {
- val = ((w_order == 0) ? 2 : 3);
- REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
- }
+ if (!CHIP_IS_E1(sc)) {
+ /* MPS w_order optimal TH presently TH
+ * 128 0 0 2
+ * 256 1 1 3
+ * >=512 2 2 3
+ */
+ /* DMAE is special */
+ if (!CHIP_IS_E1H(sc)) {
+ /* E2 can use optimal TH */
+ val = w_order;
+ REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
+ } else {
+ val = ((w_order == 0) ? 2 : 3);
+ REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
+ }
- REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
- REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
- REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
- REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
- REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
+ REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
+ }
/* Validate number of tags suppoted by device */
#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
@@ -559,18 +567,15 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
#define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
#define ILT_RANGE(f, l) (((l) << 10) | f)
-static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,
- struct ilt_line *line, uint32_t size, uint8_t memop, int cli_num, int i)
+static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc __rte_unused,
+ struct ilt_line *line, uint32_t size,
+ uint8_t memop)
{
-#define ECORE_ILT_NAMESIZE 10
- char str[ECORE_ILT_NAMESIZE];
-
if (memop == ILT_MEMOP_FREE) {
ECORE_ILT_FREE(line->page, line->page_mapping, line->size);
return 0;
}
- snprintf(str, ECORE_ILT_NAMESIZE, "ILT_%d_%d", cli_num, i);
- ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size, str);
+ ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size);
if (!line->page)
return -1;
line->size = size;
@@ -581,7 +586,7 @@ static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,
static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,
uint8_t memop)
{
- int i, rc = 0;
+ int i, rc;
struct ecore_ilt *ilt = SC_ILT(sc);
struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
@@ -591,25 +596,13 @@ static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,
if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
return 0;
- for (i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
+ for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],
- ilt_cli->page_size, memop, cli_num, i);
+ ilt_cli->page_size, memop);
}
return rc;
}
-static inline int ecore_ilt_mem_op_cnic(struct bnx2x_softc *sc, uint8_t memop)
-{
- int rc = 0;
-
- if (CONFIGURE_NIC_MODE(sc))
- rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
- if (!rc)
- rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);
-
- return rc;
-}
-
static int ecore_ilt_mem_op(struct bnx2x_softc *sc, uint8_t memop)
{
int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);
@@ -626,7 +619,10 @@ static void ecore_ilt_line_wr(struct bnx2x_softc *sc, int abs_idx,
{
uint32_t reg;
- reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
+ if (CHIP_IS_E1(sc))
+ reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx * 8;
+ else
+ reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx * 8;
ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
}
@@ -637,6 +633,7 @@ static void ecore_ilt_line_init_op(struct bnx2x_softc *sc,
ecore_dma_addr_t null_mapping;
int abs_idx = ilt->start_line + idx;
+
switch (initop) {
case INITOP_INIT:
/* set in the init-value array */
@@ -650,9 +647,10 @@ static void ecore_ilt_line_init_op(struct bnx2x_softc *sc,
}
}
-static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
- struct ilt_client_info *ilt_cli,
- uint32_t ilt_start)
+static void ecore_ilt_boundary_init_op(struct bnx2x_softc *sc,
+ struct ilt_client_info *ilt_cli,
+ uint32_t ilt_start,
+ uint8_t initop __rte_unused)
{
uint32_t start_reg = 0;
uint32_t end_reg = 0;
@@ -661,7 +659,26 @@ static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
CLEAR => SET and for now SET ~~ INIT */
/* find the appropriate regs */
- switch (ilt_cli->client_num) {
+ if (CHIP_IS_E1(sc)) {
+ switch (ilt_cli->client_num) {
+ case ILT_CLIENT_CDU:
+ start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
+ break;
+ case ILT_CLIENT_QM:
+ start_reg = PXP2_REG_PSWRQ_QM0_L2P;
+ break;
+ case ILT_CLIENT_SRC:
+ start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
+ break;
+ case ILT_CLIENT_TM:
+ start_reg = PXP2_REG_PSWRQ_TM0_L2P;
+ break;
+ }
+ REG_WR(sc, start_reg + SC_FUNC(sc) * 4,
+ ILT_RANGE((ilt_start + ilt_cli->start),
+ (ilt_start + ilt_cli->end)));
+ } else {
+ switch (ilt_cli->client_num) {
case ILT_CLIENT_CDU:
start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
@@ -678,9 +695,10 @@ static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,
start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
end_reg = PXP2_REG_RQ_TM_LAST_ILT;
break;
+ }
+ REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
+ REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
}
- REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
- REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
}
static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,
@@ -697,7 +715,7 @@ static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,
ecore_ilt_line_init_op(sc, ilt, i, initop);
/* init/clear the ILT boundries */
- ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line);
+ ecore_ilt_boundary_init_op(sc, ilt_cli, ilt->start_line, initop);
}
static void ecore_ilt_client_init_op(struct bnx2x_softc *sc,
@@ -717,13 +735,6 @@ static void ecore_ilt_client_id_init_op(struct bnx2x_softc *sc,
ecore_ilt_client_init_op(sc, ilt_cli, initop);
}
-static inline void ecore_ilt_init_op_cnic(struct bnx2x_softc *sc, uint8_t initop)
-{
- if (CONFIGURE_NIC_MODE(sc))
- ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
- ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);
-}
-
static void ecore_ilt_init_op(struct bnx2x_softc *sc, uint8_t initop)
{
ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);
@@ -771,7 +782,7 @@ static void ecore_ilt_init_page_size(struct bnx2x_softc *sc, uint8_t initop)
/****************************************************************************
* QM initializations
****************************************************************************/
-#define QM_QUEUES_PER_FUNC 16
+#define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
#define QM_INIT_MIN_CID_COUNT 31
#define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
@@ -831,33 +842,4 @@ static void ecore_qm_init_ptr_table(struct bnx2x_softc *sc, int qm_cid_count,
}
}
-/****************************************************************************
-* SRC initializations
-****************************************************************************/
-#ifdef ECORE_L5
-/* called during init func stage */
-static void ecore_src_init_t2(struct bnx2x_softc *sc, struct src_ent *t2,
- ecore_dma_addr_t t2_mapping, int src_cid_count)
-{
- int i;
- int port = SC_PORT(sc);
-
- /* Initialize T2 */
- for (i = 0; i < src_cid_count-1; i++)
- t2[i].next = (uint64_t)(t2_mapping +
- (i+1)*sizeof(struct src_ent));
-
- /* tell the searcher where the T2 table is */
- REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
-
- ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,
- U64_LO(t2_mapping), U64_HI(t2_mapping));
-
- ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,
- U64_LO((uint64_t)t2_mapping +
- (src_cid_count-1) * sizeof(struct src_ent)),
- U64_HI((uint64_t)t2_mapping +
- (src_cid_count-1) * sizeof(struct src_ent)));
-}
-#endif
#endif /* ECORE_INIT_OPS_H */
diff --git a/drivers/net/bnx2x/ecore_mfw_req.h b/drivers/net/bnx2x/ecore_mfw_req.h
index fe9450481..4ffd9daf7 100644
--- a/drivers/net/bnx2x/ecore_mfw_req.h
+++ b/drivers/net/bnx2x/ecore_mfw_req.h
@@ -14,7 +14,6 @@
#define ECORE_MFW_REQ_H
-
#define PORT_0 0
#define PORT_1 1
#define PORT_MAX 2
@@ -143,6 +142,15 @@ struct iscsi_stats_info {
uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
/* QoS Priority (per 802.1p). 0-7255 */
uint32_t qos_priority;
+#define ISCSI_QOS_PRIORITY_OFFSET 0
+#define ISCSI_QOS_PRIORITY_MASK (0xffff)
+
+#define ISCSI_IP_ADDRESS_TYPE_OFFSET 30
+#define ISCSI_IP_ADDRESS_TYPE_MASK (3 << 30)
+/* Driver does not have the IP address and type populated */
+#define ISCSI_IP_ADDRESS_TYPE_NOT_SET (0 << 30)
+#define ISCSI_IP_ADDRESS_TYPE_IPV4 (1 << 30) /* IPV4 IP address set */
+#define ISCSI_IP_ADDRESS_TYPE_IPV6 (2 << 30) /* IPV6 IP address set */
uint8_t initiator_name[64]; /* iSCSI Boot Initiator Node name. */
@@ -181,5 +189,4 @@ union drv_info_to_mcp {
struct iscsi_stats_info iscsi_stat;
};
-
#endif /* ECORE_MFW_REQ_H */
diff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c
index ceac82815..b9bca9115 100644
--- a/drivers/net/bnx2x/ecore_sp.c
+++ b/drivers/net/bnx2x/ecore_sp.c
@@ -501,7 +501,7 @@ static int __ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc __rte_unused,
*
* @details May sleep. Claims and releases execution queue lock during its run.
*/
-static int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
+int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *o)
{
int rc;
@@ -712,7 +712,7 @@ static uint8_t ecore_vlan_mac_get_rx_tx_flag(struct ecore_vlan_mac_obj
return rx_tx_flag;
}
-static void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
+void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
int add, unsigned char *dev_addr, int index)
{
uint32_t wb_data[2];
@@ -2764,12 +2764,16 @@ static int ecore_mcast_validate_e2(__rte_unused struct bnx2x_softc *sc,
static void ecore_mcast_revert_e2(__rte_unused struct bnx2x_softc *sc,
struct ecore_mcast_ramrod_params *p,
- int old_num_bins)
+ int old_num_bins,
+ enum ecore_mcast_cmd cmd)
{
struct ecore_mcast_obj *o = p->mcast_obj;
o->set_registry_size(o, old_num_bins);
o->total_pending_num -= p->mcast_list_len;
+
+ if (cmd == ECORE_MCAST_CMD_SET)
+ o->total_pending_num -= o->max_cmd_len;
}
/**
@@ -2915,7 +2919,8 @@ static int ecore_mcast_validate_e1h(__rte_unused struct bnx2x_softc *sc,
static void ecore_mcast_revert_e1h(__rte_unused struct bnx2x_softc *sc,
__rte_unused struct ecore_mcast_ramrod_params
- *p, __rte_unused int old_num_bins)
+ *p, __rte_unused int old_num_bins,
+ __rte_unused enum ecore_mcast_cmd cmd)
{
/* Do nothing */
}
@@ -3093,7 +3098,7 @@ int ecore_config_mcast(struct bnx2x_softc *sc,
r->clear_pending(r);
error_exit1:
- o->revert(sc, p, old_reg_size);
+ o->revert(sc, p, old_reg_size, cmd);
return rc;
}
@@ -3350,7 +3355,7 @@ static int ecore_credit_pool_get_entry_always_TRUE(__rte_unused struct
* If credit is negative pool operations will always succeed (unlimited pool).
*
*/
-static void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
+void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
int base, int credit)
{
/* Zero the object first */
@@ -3588,11 +3593,13 @@ int ecore_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *p)
return rc;
}
-void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
+void ecore_init_rss_config_obj(struct bnx2x_softc *sc __rte_unused,
+ struct ecore_rss_config_obj *rss_obj,
uint8_t cl_id, uint32_t cid, uint8_t func_id,
- uint8_t engine_id, void *rdata,
- ecore_dma_addr_t rdata_mapping, int state,
- unsigned long *pstate, ecore_obj_type type)
+ uint8_t engine_id,
+ void *rdata, ecore_dma_addr_t rdata_mapping,
+ int state, unsigned long *pstate,
+ ecore_obj_type type)
{
ecore_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,
rdata_mapping, state, pstate, type);
@@ -5107,8 +5114,14 @@ static int ecore_func_send_switch_update(struct bnx2x_softc *sc, struct ecore_fu
ECORE_MEMSET(rdata, 0, sizeof(*rdata));
/* Fill the ramrod data with provided parameters */
- rdata->tx_switch_suspend_change_flg = 1;
- rdata->tx_switch_suspend = switch_update_params->suspend;
+ if (ECORE_TEST_BIT(ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+ &switch_update_params->changes)) {
+ rdata->tx_switch_suspend_change_flg = 1;
+ rdata->tx_switch_suspend =
+ ECORE_TEST_BIT(ECORE_F_UPDATE_TX_SWITCH_SUSPEND,
+ &switch_update_params->changes);
+ }
+
rdata->echo = SWITCH_UPDATE;
return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
@@ -5220,7 +5233,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st
rdata->dcb_enabled = tx_start_params->dcb_enabled;
rdata->dcb_version = tx_start_params->dcb_version;
- rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;
+ rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en;
for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
rdata->traffic_type_to_priority_cos[i] =
diff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h
index fce715b6d..cc1db377a 100644
--- a/drivers/net/bnx2x/ecore_sp.h
+++ b/drivers/net/bnx2x/ecore_sp.h
@@ -135,16 +135,16 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
#define SC_ILT(sc) ((sc)->ilt)
#define ILOG2(x) bnx2x_ilog2(x)
-#define ECORE_ILT_ZALLOC(x, y, size, str) \
+#define ECORE_ILT_ZALLOC(x, y, size) \
do { \
x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \
if (x) { \
if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
size, (struct bnx2x_dma *)x, \
- str, RTE_CACHE_LINE_SIZE) != 0) { \
+ "ILT", RTE_CACHE_LINE_SIZE) != 0) { \
rte_free(x); \
x = NULL; \
- *y = 0; \
+ *(y) = 0; \
} else { \
*y = ((struct bnx2x_dma *)x)->paddr; \
} \
@@ -161,7 +161,7 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;
} \
} while (0)
-#define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE
+#define ECORE_IS_VALID_ETHER_ADDR(_mac) true
#define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE
#define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE
@@ -238,11 +238,11 @@ typedef struct ecore_list_t
(_list)->cnt = 0; \
} while (0)
-/* return TRUE if the element is the last on the list */
+/* return true if the element is the last on the list */
#define ECORE_LIST_IS_LAST(_elem, _list) \
(_elem == (_list)->tail)
-/* return TRUE if the list is empty */
+/* return true if the list is empty */
#define ECORE_LIST_IS_EMPTY(_list) \
((_list)->cnt == 0)
@@ -413,9 +413,6 @@ enum {
AFEX_UPDATE,
};
-
-
-
struct bnx2x_softc;
struct eth_context;
@@ -461,11 +458,18 @@ enum {
ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
ECORE_FILTER_FCOE_ETH_START_SCHED,
ECORE_FILTER_FCOE_ETH_STOP_SCHED,
+#ifdef ECORE_CHAR_DEV
+ ECORE_FILTER_BYPASS_RX_MODE_PENDING,
+ ECORE_FILTER_BYPASS_MAC_PENDING,
+ ECORE_FILTER_BYPASS_RSS_CONF_PENDING,
+#endif
ECORE_FILTER_MCAST_PENDING,
ECORE_FILTER_MCAST_SCHED,
ECORE_FILTER_RSS_CONF_PENDING,
ECORE_AFEX_FCOE_Q_UPDATE_PENDING,
- ECORE_AFEX_PENDING_VIFSET_MCP_ACK
+ ECORE_AFEX_PENDING_VIFSET_MCP_ACK,
+ ECORE_FILTER_VXLAN_PENDING,
+ ECORE_FILTER_PVLAN_PENDING
};
struct ecore_raw_obj {
@@ -488,7 +492,7 @@ struct ecore_raw_obj {
int (*wait_comp)(struct bnx2x_softc *sc,
struct ecore_raw_obj *o);
- int (*check_pending)(struct ecore_raw_obj *o);
+ bool (*check_pending)(struct ecore_raw_obj *o);
void (*clear_pending)(struct ecore_raw_obj *o);
void (*set_pending)(struct ecore_raw_obj *o);
};
@@ -509,10 +513,16 @@ struct ecore_vlan_mac_ramrod_data {
uint16_t vlan;
};
+struct ecore_vxlan_fltr_ramrod_data {
+ uint8_t innermac[ETH_ALEN];
+ uint32_t vni;
+};
+
union ecore_classification_ramrod_data {
struct ecore_mac_ramrod_data mac;
struct ecore_vlan_ramrod_data vlan;
struct ecore_vlan_mac_ramrod_data vlan_mac;
+ struct ecore_vxlan_fltr_ramrod_data vxlan_fltr;
};
/* VLAN_MAC commands */
@@ -541,6 +551,7 @@ union ecore_exe_queue_cmd_data {
struct ecore_vlan_mac_data vlan_mac;
struct {
+ /* TODO */
} mcast;
};
@@ -642,7 +653,7 @@ struct ecore_vlan_mac_registry_elem {
ecore_list_entry_t link;
/* Used to store the cam offset used for the mac/vlan/vlan-mac.
- * Relevant for 57711 only. VLANs and MACs share the
+ * Relevant for 57710 and 57711 only. VLANs and MACs share the
* same CAM for these chips.
*/
int cam_offset;
@@ -659,9 +670,18 @@ enum {
ECORE_ETH_MAC,
ECORE_ISCSI_ETH_MAC,
ECORE_NETQ_ETH_MAC,
+ ECORE_VLAN,
ECORE_DONT_CONSUME_CAM_CREDIT,
ECORE_DONT_CONSUME_CAM_CREDIT_DEST,
};
+/* When looking for matching filters, some flags are not interesting */
+#define ECORE_VLAN_MAC_CMP_MASK (1 << ECORE_UC_LIST_MAC | \
+ 1 << ECORE_ETH_MAC | \
+ 1 << ECORE_ISCSI_ETH_MAC | \
+ 1 << ECORE_NETQ_ETH_MAC | \
+ 1 << ECORE_VLAN)
+#define ECORE_VLAN_MAC_CMP_FLAGS(flags) \
+ ((flags) & ECORE_VLAN_MAC_CMP_MASK)
struct ecore_vlan_mac_ramrod_params {
/* Object to run the command from */
@@ -685,7 +705,7 @@ struct ecore_vlan_mac_obj {
* all these fields should only be accessed under the exe_queue lock
*/
uint8_t head_reader; /* Num. of readers accessing head list */
- int head_exe_request; /* Pending execution request. */
+ bool head_exe_request; /* Pending execution request. */
unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
/* Execution queue interface instance */
@@ -728,7 +748,7 @@ struct ecore_vlan_mac_obj {
/**
* Checks if DEL-ramrod with the given params may be performed.
*
- * @return TRUE if the element may be deleted
+ * @return true if the element may be deleted
*/
struct ecore_vlan_mac_registry_elem *
(*check_del)(struct bnx2x_softc *sc,
@@ -738,9 +758,9 @@ struct ecore_vlan_mac_obj {
/**
* Checks if DEL-ramrod with the given params may be performed.
*
- * @return TRUE if the element may be deleted
+ * @return true if the element may be deleted
*/
- int (*check_move)(struct bnx2x_softc *sc,
+ bool (*check_move)(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *src_o,
struct ecore_vlan_mac_obj *dst_o,
union ecore_classification_ramrod_data *data);
@@ -749,10 +769,10 @@ struct ecore_vlan_mac_obj {
* Update the relevant credit object(s) (consume/return
* correspondingly).
*/
- int (*get_credit)(struct ecore_vlan_mac_obj *o);
- int (*put_credit)(struct ecore_vlan_mac_obj *o);
- int (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
- int (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
+ bool (*get_credit)(struct ecore_vlan_mac_obj *o);
+ bool (*put_credit)(struct ecore_vlan_mac_obj *o);
+ bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
+ bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
/**
* Configures one rule in the ramrod data buffer.
@@ -838,6 +858,9 @@ enum {
ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
};
+void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
+ bool add, unsigned char *dev_addr, int index);
+
/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
/* RX_MODE ramrod special flags: set in rx_mode_flags field in
@@ -898,7 +921,7 @@ struct ecore_mcast_list_elem {
union ecore_mcast_config_data {
uint8_t *mac;
- uint8_t bin; /* used in a RESTORE flow */
+ uint8_t bin; /* used in a RESTORE/SET flows */
};
struct ecore_mcast_ramrod_params {
@@ -908,6 +931,14 @@ struct ecore_mcast_ramrod_params {
unsigned long ramrod_flags;
ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */
+ /** TODO:
+ * - rename it to macs_num.
+ * - Add a new command type for handling pending commands
+ * (remove "zero semantics").
+ *
+ * Length of mcast_list. If zero and ADD_CONT command - post
+ * pending commands.
+ */
int mcast_list_len;
};
@@ -916,6 +947,15 @@ enum ecore_mcast_cmd {
ECORE_MCAST_CMD_CONT,
ECORE_MCAST_CMD_DEL,
ECORE_MCAST_CMD_RESTORE,
+
+ /* Following this, multicast configuration should equal to approx
+ * the set of MACs provided [i.e., remove all else].
+ * The two sub-commands are used internally to decide whether a given
+ * bin is to be added or removed
+ */
+ ECORE_MCAST_CMD_SET,
+ ECORE_MCAST_CMD_SET_ADD,
+ ECORE_MCAST_CMD_SET_DEL,
};
struct ecore_mcast_obj {
@@ -989,14 +1029,14 @@ struct ecore_mcast_obj {
/** Checks if there are more mcast MACs to be set or a previous
* command is still pending.
*/
- int (*check_pending)(struct ecore_mcast_obj *o);
+ bool (*check_pending)(struct ecore_mcast_obj *o);
/**
* Set/Clear/Check SCHEDULED state of the object
*/
void (*set_sched)(struct ecore_mcast_obj *o);
void (*clear_sched)(struct ecore_mcast_obj *o);
- int (*check_sched)(struct ecore_mcast_obj *o);
+ bool (*check_sched)(struct ecore_mcast_obj *o);
/* Wait until all pending commands complete */
int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o);
@@ -1015,7 +1055,8 @@ struct ecore_mcast_obj {
*/
void (*revert)(struct bnx2x_softc *sc,
struct ecore_mcast_ramrod_params *p,
- int old_num_bins);
+ int old_num_bins,
+ enum ecore_mcast_cmd cmd);
int (*get_registry_size)(struct ecore_mcast_obj *o);
void (*set_registry_size)(struct ecore_mcast_obj *o, int n);
@@ -1045,33 +1086,33 @@ struct ecore_credit_pool_obj {
/**
* Get the next free pool entry.
*
- * @return TRUE if there was a free entry in the pool
+ * @return true if there was a free entry in the pool
*/
- int (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
+ bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
/**
* Return the entry back to the pool.
*
- * @return TRUE if entry is legal and has been successfully
+ * @return true if entry is legal and has been successfully
* returned to the pool.
*/
- int (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
+ bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
/**
* Get the requested amount of credit from the pool.
*
* @param cnt Amount of requested credit
- * @return TRUE if the operation is successful
+ * @return true if the operation is successful
*/
- int (*get)(struct ecore_credit_pool_obj *o, int cnt);
+ bool (*get)(struct ecore_credit_pool_obj *o, int cnt);
/**
* Returns the credit to the pool.
*
* @param cnt Amount of credit to return
- * @return TRUE if the operation is successful
+ * @return true if the operation is successful
*/
- int (*put)(struct ecore_credit_pool_obj *o, int cnt);
+ bool (*put)(struct ecore_credit_pool_obj *o, int cnt);
/**
* Reads the current amount of credit.
@@ -1094,7 +1135,9 @@ enum {
ECORE_RSS_IPV6_TCP,
ECORE_RSS_IPV6_UDP,
- ECORE_RSS_TUNNELING,
+ ECORE_RSS_IPV4_VXLAN,
+ ECORE_RSS_IPV6_VXLAN,
+ ECORE_RSS_TUNN_INNER_HDRS,
};
struct ecore_config_rss_params {
@@ -1117,10 +1160,6 @@ struct ecore_config_rss_params {
/* valid only if ECORE_RSS_UPDATE_TOE is set */
uint16_t toe_rss_bitmap;
-
- /* valid if ECORE_RSS_TUNNELING is set */
- uint16_t tunnel_value;
- uint16_t tunnel_mask;
};
struct ecore_rss_config_obj {
@@ -1158,6 +1197,8 @@ enum {
ECORE_Q_UPDATE_SILENT_VLAN_REM,
ECORE_Q_UPDATE_TX_SWITCHING_CHNG,
ECORE_Q_UPDATE_TX_SWITCHING,
+ ECORE_Q_UPDATE_PTP_PKTS_CHNG,
+ ECORE_Q_UPDATE_PTP_PKTS,
};
/* Allowed Queue states */
@@ -1222,12 +1263,16 @@ enum {
ECORE_Q_FLG_FORCE_DEFAULT_PRI,
ECORE_Q_FLG_REFUSE_OUTBAND_VLAN,
ECORE_Q_FLG_PCSUM_ON_PKT,
- ECORE_Q_FLG_TUN_INC_INNER_IP_ID
+ ECORE_Q_FLG_TUN_INC_INNER_IP_ID,
+ ECORE_Q_FLG_TPA_VLAN_DIS,
};
/* Queue type options: queue type may be a combination of below. */
enum ecore_q_type {
ECORE_Q_TYPE_FWD,
+ /** TODO: Consider moving both these flags into the init()
+ * ramrod params.
+ */
ECORE_Q_TYPE_HAS_RX,
ECORE_Q_TYPE_HAS_TX,
};
@@ -1238,6 +1283,10 @@ enum ecore_q_type {
#define ECORE_MULTI_TX_COS_E3B0 3
#define ECORE_MULTI_TX_COS 3 /* Maximum possible */
#define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)
+/* DMAE channel to be used by FW for timesync workaroun. A driver that sends
+ * timesync-related ramrods must not use this DMAE command ID.
+ */
+#define FW_DMAE_CMD_ID 6
struct ecore_queue_init_params {
struct {
@@ -1280,6 +1329,26 @@ struct ecore_queue_update_params {
uint8_t cid_index;
};
+struct ecore_queue_update_tpa_params {
+ ecore_dma_addr_t sge_map;
+ uint8_t update_ipv4;
+ uint8_t update_ipv6;
+ uint8_t max_tpa_queues;
+ uint8_t max_sges_pkt;
+ uint8_t complete_on_both_clients;
+ uint8_t dont_verify_thr;
+ uint8_t tpa_mode;
+ uint8_t _pad;
+
+ uint16_t sge_buff_sz;
+ uint16_t max_agg_sz;
+
+ uint16_t sge_pause_thr_low;
+ uint16_t sge_pause_thr_high;
+
+ uint8_t disable_tpa_over_vlan;
+};
+
struct rxq_pause_params {
uint16_t bd_th_lo;
uint16_t bd_th_hi;
@@ -1298,11 +1367,14 @@ struct ecore_general_setup_params {
uint8_t spcl_id;
uint16_t mtu;
uint8_t cos;
+
+ uint8_t fp_hsi;
};
struct ecore_rxq_setup_params {
/* dma */
ecore_dma_addr_t dscr_map;
+ ecore_dma_addr_t sge_map;
ecore_dma_addr_t rcq_map;
ecore_dma_addr_t rcq_np_map;
@@ -1313,6 +1385,8 @@ struct ecore_rxq_setup_params {
/* valid if ECORE_Q_FLG_TPA */
uint16_t tpa_agg_sz;
+ uint16_t sge_buf_sz;
+ uint8_t max_sges_pkt;
uint8_t max_tpa_queues;
uint8_t rss_engine_id;
@@ -1323,7 +1397,7 @@ struct ecore_rxq_setup_params {
uint8_t sb_cq_index;
- /* valid if BXN2X_Q_FLG_SILENT_VLAN_REM */
+ /* valid if ECORE_Q_FLG_SILENT_VLAN_REM */
uint16_t silent_removal_value;
uint16_t silent_removal_mask;
};
@@ -1371,6 +1445,7 @@ struct ecore_queue_state_params {
/* Params according to the current command */
union {
struct ecore_queue_update_params update;
+ struct ecore_queue_update_tpa_params update_tpa;
struct ecore_queue_setup_params setup;
struct ecore_queue_init_params init;
struct ecore_queue_setup_tx_only_params tx_only;
@@ -1450,6 +1525,24 @@ struct ecore_queue_sp_obj {
};
/********************** Function state update *********************************/
+
+/* UPDATE command options */
+enum {
+ ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+ ECORE_F_UPDATE_TX_SWITCH_SUSPEND,
+ ECORE_F_UPDATE_SD_VLAN_TAG_CHNG,
+ ECORE_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
+ ECORE_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
+ ECORE_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
+ ECORE_F_UPDATE_TUNNEL_CFG_CHNG,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
+ ECORE_F_UPDATE_TUNNEL_INNER_RSS,
+ ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN_INNER_VNI,
+ ECORE_F_UPDATE_VLAN_FILTERING_PVID_CHNG,
+};
+
/* Allowed Function states */
enum ecore_func_state {
ECORE_F_STATE_RESET,
@@ -1470,6 +1563,7 @@ enum ecore_func_cmd {
ECORE_F_CMD_TX_STOP,
ECORE_F_CMD_TX_START,
ECORE_F_CMD_SWITCH_UPDATE,
+ ECORE_F_CMD_SET_TIMESYNC,
ECORE_F_CMD_MAX,
};
@@ -1511,19 +1605,60 @@ struct ecore_func_start_params {
/* Function cos mode */
uint8_t network_cos_mode;
- /* NVGRE classification enablement */
- uint8_t nvgre_clss_en;
+ /* DMAE command id to be used for FW DMAE transactions */
+ uint8_t dmae_cmd_id;
+
+ /* UDP dest port for VXLAN */
+ uint16_t vxlan_dst_port;
+
+ /* UDP dest port for Geneve */
+ uint16_t geneve_dst_port;
+
+ /* Enable inner Rx classifications for L2GRE packets */
+ uint8_t inner_clss_l2gre;
+
+ /* Enable inner Rx classifications for L2-Geneve packets */
+ uint8_t inner_clss_l2geneve;
+
+ /* Enable inner Rx classification for vxlan packets */
+ uint8_t inner_clss_vxlan;
+
+ /* Enable RSS according to inner header */
+ uint8_t inner_rss;
+
+ /** Allows accepting of packets failing MF classification, possibly
+ * only matching a given ethertype
+ */
+ uint8_t class_fail;
+ uint16_t class_fail_ethtype;
+
+ /* Override priority of output packets */
+ uint8_t sd_vlan_force_pri;
+ uint8_t sd_vlan_force_pri_val;
+
+ /* Replace vlan's ethertype */
+ uint16_t sd_vlan_eth_type;
- /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
- uint8_t gre_tunnel_mode;
+ /* Prevent inner vlans from being added by FW */
+ uint8_t no_added_tags;
- /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
- uint8_t gre_tunnel_rss;
+ /* Inner-to-Outer vlan priority mapping */
+ uint8_t c2s_pri[MAX_VLAN_PRIORITIES];
+ uint8_t c2s_pri_default;
+ uint8_t c2s_pri_valid;
+ /* TX Vlan filtering configuration */
+ uint8_t tx_vlan_filtering_enable;
+ uint8_t tx_vlan_filtering_use_pvid;
};
struct ecore_func_switch_update_params {
- uint8_t suspend;
+ unsigned long changes; /* ECORE_F_UPDATE_XX bits */
+ uint16_t vlan;
+ uint16_t vlan_eth_type;
+ uint8_t vlan_force_prio;
+ uint16_t vxlan_dst_port;
+ uint16_t geneve_dst_port;
};
struct ecore_func_afex_update_params {
@@ -1538,11 +1673,28 @@ struct ecore_func_afex_viflists_params {
uint8_t afex_vif_list_command;
uint8_t func_to_clear;
};
+
struct ecore_func_tx_start_params {
struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
uint8_t dcb_enabled;
uint8_t dcb_version;
- uint8_t dont_add_pri_0;
+ uint8_t dont_add_pri_0_en;
+ uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];
+};
+
+struct ecore_func_set_timesync_params {
+ /* Reset, set or keep the current drift value */
+ uint8_t drift_adjust_cmd;
+ /* Dec, inc or keep the current offset */
+ uint8_t offset_cmd;
+ /* Drift value direction */
+ uint8_t add_sub_drift_adjust_value;
+ /* Drift, period and offset values to be used according to the commands
+ * above.
+ */
+ uint8_t drift_adjust_value;
+ uint32_t drift_adjust_period;
+ uint64_t offset_delta;
};
struct ecore_func_state_params {
@@ -1563,6 +1715,7 @@ struct ecore_func_state_params {
struct ecore_func_afex_update_params afex_update;
struct ecore_func_afex_viflists_params afex_viflists;
struct ecore_func_tx_start_params tx_start;
+ struct ecore_func_set_timesync_params set_timesync;
} params;
};
@@ -1583,6 +1736,10 @@ struct ecore_func_sp_drv_ops {
void (*reset_hw_port)(struct bnx2x_softc *sc);
void (*reset_hw_func)(struct bnx2x_softc *sc);
+ /* Init/Free GUNZIP resources */
+ int (*gunzip_init)(struct bnx2x_softc *sc);
+ void (*gunzip_end)(struct bnx2x_softc *sc);
+
/* Prepare/Release FW resources */
int (*init_fw)(struct bnx2x_softc *sc);
void (*release_fw)(struct bnx2x_softc *sc);
@@ -1669,6 +1826,9 @@ void ecore_init_queue_obj(struct bnx2x_softc *sc,
int ecore_queue_state_change(struct bnx2x_softc *sc,
struct ecore_queue_state_params *params);
+int ecore_get_q_logical_state(struct bnx2x_softc *sc,
+ struct ecore_queue_sp_obj *obj);
+
/********************* VLAN-MAC ****************/
void ecore_init_mac_obj(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *mac_obj,
@@ -1677,6 +1837,34 @@ void ecore_init_mac_obj(struct bnx2x_softc *sc,
unsigned long *pstate, ecore_obj_type type,
struct ecore_credit_pool_obj *macs_pool);
+void ecore_init_vlan_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id,
+ void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+void ecore_init_vlan_mac_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_mac_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id,
+ void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *macs_pool,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+void ecore_init_vxlan_fltr_obj(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *vlan_mac_obj,
+ uint8_t cl_id, uint32_t cid, uint8_t func_id,
+ void *rdata,
+ ecore_dma_addr_t rdata_mapping, int state,
+ unsigned long *pstate, ecore_obj_type type,
+ struct ecore_credit_pool_obj *macs_pool,
+ struct ecore_credit_pool_obj *vlans_pool);
+
+int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,
+ struct ecore_vlan_mac_obj *o);
void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *o);
int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc,
@@ -1719,7 +1907,7 @@ void ecore_init_mcast_obj(struct bnx2x_softc *sc,
/**
* ecore_config_mcast - Configure multicast MACs list.
*
- * @cmd: command to execute: BNX2X_MCAST_CMD_X
+ * @cmd: command to execute: ECORE_MCAST_CMD_X
*
* May configure a new list
* provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up
@@ -1747,9 +1935,12 @@ void ecore_init_mac_credit_pool(struct bnx2x_softc *sc,
void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,
struct ecore_credit_pool_obj *p, uint8_t func_id,
uint8_t func_num);
+void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
+ int base, int credit);
/****************** RSS CONFIGURATION ****************/
-void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
+void ecore_init_rss_config_obj(struct bnx2x_softc *sc,
+ struct ecore_rss_config_obj *rss_obj,
uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,
void *rdata, ecore_dma_addr_t rdata_mapping,
int state, unsigned long *pstate,
@@ -1763,5 +1954,24 @@ void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
int ecore_config_rss(struct bnx2x_softc *sc,
struct ecore_config_rss_params *p);
+/**
+ * ecore_get_rss_ind_table - Return the current ind_table configuration.
+ *
+ * @ind_table: buffer to fill with the current indirection
+ * table content. Should be at least
+ * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
+ */
+void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj,
+ uint8_t *ind_table);
+
+#define PF_MAC_CREDIT_E2(sc, func_num) \
+ ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_MAC_CREDIT_CNT) / \
+ (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT)
+
+#define PF_VLAN_CREDIT_E2(sc, func_num) \
+ ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_VLAN_CREDIT_CNT) / \
+ (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_VLAN_CREDIT_CNT)
+
+#define ECORE_PF_VLAN_CREDIT_VLAN_FILTERING 256
#endif /* ECORE_SP_H */
--
2.18.0
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