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* [PATCH 1/1] common/cnxk: added new macros to platform layer
@ 2022-04-12 17:42 Srikanth Yalavarthi
  2022-04-13  7:08 ` Morten Brørup
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Srikanth Yalavarthi @ 2022-04-12 17:42 UTC (permalink / raw)
  To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, jerinj, sshankarnara, Srikanth Yalavarthi

Added new macros for pointer operations, bitwise operations,
spinlocks and 32 bit read and write.

Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
---
 drivers/common/cnxk/roc_bits.h     | 12 ++++++++++++
 drivers/common/cnxk/roc_platform.h | 28 +++++++++++++++++++---------
 2 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/drivers/common/cnxk/roc_bits.h b/drivers/common/cnxk/roc_bits.h
index 11216d9d63..ce3dffa08d 100644
--- a/drivers/common/cnxk/roc_bits.h
+++ b/drivers/common/cnxk/roc_bits.h
@@ -29,4 +29,16 @@
 	 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
 #endif
 
+#ifndef IS_BIT_SET
+#define IS_BIT_SET(num, n) ((num) & (1 << (n)))
+#endif
+
+#ifndef SET_BIT
+#define SET_BIT(num, n) ((num) | (1 << (n)))
+#endif
+
+#ifndef CLEAR_BIT
+#define CLEAR_BIT(num, n) ((num) &= ~((1) << (n)))
+#endif
+
 #endif /* _ROC_BITS_H_ */
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 28004b1743..3671e55c23 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -41,6 +41,7 @@
 #define PLT_MEMZONE_NAMESIZE	 RTE_MEMZONE_NAMESIZE
 #define PLT_STD_C11		 RTE_STD_C11
 #define PLT_PTR_ADD		 RTE_PTR_ADD
+#define PLT_PTR_SUB		 RTE_PTR_SUB
 #define PLT_PTR_DIFF		 RTE_PTR_DIFF
 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID
 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET
@@ -70,12 +71,16 @@
 #define PLT_U32_CAST(val) ((uint32_t)(val))
 #define PLT_U16_CAST(val) ((uint16_t)(val))
 
+/* Add / Sub pointer with scalar and cast to uint64_t */
+#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x))
+#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x))
+
 /** Divide ceil */
-#define PLT_DIV_CEIL(x, y)			\
-	({					\
-		__typeof(x) __x = x;		\
-		__typeof(y) __y = y;		\
-		(__x + __y - 1) / __y;		\
+#define PLT_DIV_CEIL(x, y)                                                     \
+	({                                                                     \
+		__typeof(x) __x = x;                                           \
+		__typeof(y) __y = y;                                           \
+		(__x + __y - 1) / __y;                                         \
 	})
 
 #define __plt_cache_aligned __rte_cache_aligned
@@ -113,10 +118,11 @@
 #define plt_bitmap_scan			rte_bitmap_scan
 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint
 
-#define plt_spinlock_t	    rte_spinlock_t
-#define plt_spinlock_init   rte_spinlock_init
-#define plt_spinlock_lock   rte_spinlock_lock
-#define plt_spinlock_unlock rte_spinlock_unlock
+#define plt_spinlock_t	     rte_spinlock_t
+#define plt_spinlock_init    rte_spinlock_init
+#define plt_spinlock_lock    rte_spinlock_lock
+#define plt_spinlock_unlock  rte_spinlock_unlock
+#define plt_spinlock_trylock rte_spinlock_trylock
 
 #define plt_intr_callback_register   rte_intr_callback_register
 #define plt_intr_callback_unregister rte_intr_callback_unregister
@@ -165,6 +171,10 @@
 #define plt_write64(val, addr)                                                 \
 	rte_write64_relaxed((val), (volatile void *)(addr))
 
+#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr))
+#define plt_write32(val, addr)                                                 \
+	rte_write32_relaxed((val), (volatile void *)(addr))
+
 #define plt_wmb()		rte_wmb()
 #define plt_rmb()		rte_rmb()
 #define plt_io_wmb()		rte_io_wmb()
-- 
2.17.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* RE: [PATCH 1/1] common/cnxk: added new macros to platform layer
  2022-04-12 17:42 [PATCH 1/1] common/cnxk: added new macros to platform layer Srikanth Yalavarthi
@ 2022-04-13  7:08 ` Morten Brørup
  2022-05-14 12:20 ` Jerin Jacob
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Morten Brørup @ 2022-04-13  7:08 UTC (permalink / raw)
  To: Srikanth Yalavarthi, Nithin Dabilpuram, Kiran Kumar K,
	Sunil Kumar Kori, Satha Rao
  Cc: dev, jerinj, sshankarnara

> From: Srikanth Yalavarthi [mailto:syalavarthi@marvell.com]
> Sent: Tuesday, 12 April 2022 19.42
> 
> Added new macros for pointer operations, bitwise operations,
> spinlocks and 32 bit read and write.
> 
> Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
> ---
>  drivers/common/cnxk/roc_bits.h     | 12 ++++++++++++
>  drivers/common/cnxk/roc_platform.h | 28 +++++++++++++++++++---------
>  2 files changed, 31 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/common/cnxk/roc_bits.h
> b/drivers/common/cnxk/roc_bits.h
> index 11216d9d63..ce3dffa08d 100644
> --- a/drivers/common/cnxk/roc_bits.h
> +++ b/drivers/common/cnxk/roc_bits.h
> @@ -29,4 +29,16 @@
>  	 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
>  #endif
> 
> +#ifndef IS_BIT_SET
> +#define IS_BIT_SET(num, n) ((num) & (1 << (n)))
> +#endif
> +
> +#ifndef SET_BIT
> +#define SET_BIT(num, n) ((num) | (1 << (n)))
> +#endif
> +
> +#ifndef CLEAR_BIT
> +#define CLEAR_BIT(num, n) ((num) &= ~((1) << (n)))
> +#endif
> +
>  #endif /* _ROC_BITS_H_ */

You could consider replacing these with explicit 32/64 bit variants, using the RTE_BIT64() and RTE_BIT32() macros instead of (1 << (n)).

Just a suggestion - I'll leave it up to you.

-Morten


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/1] common/cnxk: added new macros to platform layer
  2022-04-12 17:42 [PATCH 1/1] common/cnxk: added new macros to platform layer Srikanth Yalavarthi
  2022-04-13  7:08 ` Morten Brørup
@ 2022-05-14 12:20 ` Jerin Jacob
  2022-05-16 17:20 ` [PATCH v2 1/1] common/cnxk: added additional platform macros Srikanth Yalavarthi
  2022-05-16 17:26 ` [PATCH v2 1/1] common/cnxk: added new macros to platform layer Srikanth Yalavarthi
  3 siblings, 0 replies; 5+ messages in thread
From: Jerin Jacob @ 2022-05-14 12:20 UTC (permalink / raw)
  To: Srikanth Yalavarthi
  Cc: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao,
	dpdk-dev, Jerin Jacob, sshankarnara

On Tue, Apr 12, 2022 at 11:12 PM Srikanth Yalavarthi
<syalavarthi@marvell.com> wrote:
>
> Added new macros for pointer operations, bitwise operations,
> spinlocks and 32 bit read and write.
>
> Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
> ---
>  drivers/common/cnxk/roc_bits.h     | 12 ++++++++++++
>  drivers/common/cnxk/roc_platform.h | 28 +++++++++++++++++++---------
>  2 files changed, 31 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_bits.h b/drivers/common/cnxk/roc_bits.h
> index 11216d9d63..ce3dffa08d 100644
> --- a/drivers/common/cnxk/roc_bits.h
> +++ b/drivers/common/cnxk/roc_bits.h
> @@ -29,4 +29,16 @@
>          (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
>  #endif
>
> +#ifndef IS_BIT_SET
> +#define IS_BIT_SET(num, n) ((num) & (1 << (n)))
> +#endif
> +
> +#ifndef SET_BIT
> +#define SET_BIT(num, n) ((num) | (1 << (n)))
> +#endif
> +
> +#ifndef CLEAR_BIT
> +#define CLEAR_BIT(num, n) ((num) &= ~((1) << (n)))
> +#endif


lib/eal/include/rte_bitops.h has similar ops already, Please use those
schemes now.
ie.
#define plt_bit_relaxed_get32 rte_bit_relaxed_get32


>  #endif /* _ROC_BITS_H_ */
> diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
> index 28004b1743..3671e55c23 100644
> --- a/drivers/common/cnxk/roc_platform.h
> +++ b/drivers/common/cnxk/roc_platform.h
> @@ -41,6 +41,7 @@
>  #define PLT_MEMZONE_NAMESIZE    RTE_MEMZONE_NAMESIZE
>  #define PLT_STD_C11             RTE_STD_C11
>  #define PLT_PTR_ADD             RTE_PTR_ADD
> +#define PLT_PTR_SUB             RTE_PTR_SUB
>  #define PLT_PTR_DIFF            RTE_PTR_DIFF
>  #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID
>  #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET
> @@ -70,12 +71,16 @@
>  #define PLT_U32_CAST(val) ((uint32_t)(val))
>  #define PLT_U16_CAST(val) ((uint16_t)(val))
>
> +/* Add / Sub pointer with scalar and cast to uint64_t */
> +#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x))
> +#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x))
> +
>  /** Divide ceil */
> -#define PLT_DIV_CEIL(x, y)                     \
> -       ({                                      \
> -               __typeof(x) __x = x;            \
> -               __typeof(y) __y = y;            \
> -               (__x + __y - 1) / __y;          \
> +#define PLT_DIV_CEIL(x, y)                                                     \
> +       ({                                                                     \
> +               __typeof(x) __x = x;                                           \
> +               __typeof(y) __y = y;                                           \
> +               (__x + __y - 1) / __y;                                         \
>         })

Please remove formatting changes.


>
>  #define __plt_cache_aligned __rte_cache_aligned
> @@ -113,10 +118,11 @@
>  #define plt_bitmap_scan                        rte_bitmap_scan
>  #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint
>
> -#define plt_spinlock_t     rte_spinlock_t
> -#define plt_spinlock_init   rte_spinlock_init
> -#define plt_spinlock_lock   rte_spinlock_lock
> -#define plt_spinlock_unlock rte_spinlock_unlock
> +#define plt_spinlock_t      rte_spinlock_t
> +#define plt_spinlock_init    rte_spinlock_init
> +#define plt_spinlock_lock    rte_spinlock_lock
> +#define plt_spinlock_unlock  rte_spinlock_unlock
> +#define plt_spinlock_trylock rte_spinlock_trylock
>
>  #define plt_intr_callback_register   rte_intr_callback_register
>  #define plt_intr_callback_unregister rte_intr_callback_unregister
> @@ -165,6 +171,10 @@
>  #define plt_write64(val, addr)                                                 \
>         rte_write64_relaxed((val), (volatile void *)(addr))
>
> +#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr))
> +#define plt_write32(val, addr)                                                 \
> +       rte_write32_relaxed((val), (volatile void *)(addr))
> +
>  #define plt_wmb()              rte_wmb()
>  #define plt_rmb()              rte_rmb()
>  #define plt_io_wmb()           rte_io_wmb()
> --
> 2.17.1
>

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v2 1/1] common/cnxk: added additional platform macros
  2022-04-12 17:42 [PATCH 1/1] common/cnxk: added new macros to platform layer Srikanth Yalavarthi
  2022-04-13  7:08 ` Morten Brørup
  2022-05-14 12:20 ` Jerin Jacob
@ 2022-05-16 17:20 ` Srikanth Yalavarthi
  2022-05-16 17:26 ` [PATCH v2 1/1] common/cnxk: added new macros to platform layer Srikanth Yalavarthi
  3 siblings, 0 replies; 5+ messages in thread
From: Srikanth Yalavarthi @ 2022-05-16 17:20 UTC (permalink / raw)
  To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, jerinj, sshankarnara, Srikanth Yalavarthi

Added new platform layer macros for pointer operations,
bitwise operations, spinlocks and 32 bit read and write.

Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
Change-Id: Icb039b19492e927d922bbd66232416e963db2892
---
 drivers/common/cnxk/roc_platform.h | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 86987aea3b..1ad3c16705 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -41,6 +41,7 @@
 #define PLT_MEMZONE_NAMESIZE	 RTE_MEMZONE_NAMESIZE
 #define PLT_STD_C11		 RTE_STD_C11
 #define PLT_PTR_ADD		 RTE_PTR_ADD
+#define PLT_PTR_SUB		 RTE_PTR_SUB
 #define PLT_PTR_DIFF		 RTE_PTR_DIFF
 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID
 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET
@@ -70,6 +71,10 @@
 #define PLT_U32_CAST(val) ((uint32_t)(val))
 #define PLT_U16_CAST(val) ((uint16_t)(val))
 
+/* Add / Sub pointer with scalar and cast to uint64_t */
+#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x))
+#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x))
+
 /** Divide ceil */
 #define PLT_DIV_CEIL(x, y)			\
 	({					\
@@ -113,10 +118,11 @@
 #define plt_bitmap_scan			rte_bitmap_scan
 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint
 
-#define plt_spinlock_t	    rte_spinlock_t
-#define plt_spinlock_init   rte_spinlock_init
-#define plt_spinlock_lock   rte_spinlock_lock
-#define plt_spinlock_unlock rte_spinlock_unlock
+#define plt_spinlock_t	     rte_spinlock_t
+#define plt_spinlock_init    rte_spinlock_init
+#define plt_spinlock_lock    rte_spinlock_lock
+#define plt_spinlock_unlock  rte_spinlock_unlock
+#define plt_spinlock_trylock rte_spinlock_trylock
 
 #define plt_intr_callback_register   rte_intr_callback_register
 #define plt_intr_callback_unregister rte_intr_callback_unregister
@@ -165,12 +171,24 @@
 #define plt_write64(val, addr)                                                 \
 	rte_write64_relaxed((val), (volatile void *)(addr))
 
+#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr))
+#define plt_write32(val, addr)                                                 \
+	rte_write32_relaxed((val), (volatile void *)(addr))
+
 #define plt_wmb()		rte_wmb()
 #define plt_rmb()		rte_rmb()
 #define plt_io_wmb()		rte_io_wmb()
 #define plt_io_rmb()		rte_io_rmb()
 #define plt_atomic_thread_fence rte_atomic_thread_fence
 
+#define plt_bit_relaxed_get32   rte_bit_relaxed_get32
+#define plt_bit_relaxed_set32   rte_bit_relaxed_set32
+#define plt_bit_relaxed_clear32 rte_bit_relaxed_clear32
+
+#define plt_bit_relaxed_get64   rte_bit_relaxed_get64
+#define plt_bit_relaxed_set64   rte_bit_relaxed_set64
+#define plt_bit_relaxed_clear64 rte_bit_relaxed_clear64
+
 #define plt_mmap       mmap
 #define PLT_PROT_READ  PROT_READ
 #define PLT_PROT_WRITE PROT_WRITE
-- 
2.17.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v2 1/1] common/cnxk: added new macros to platform layer
  2022-04-12 17:42 [PATCH 1/1] common/cnxk: added new macros to platform layer Srikanth Yalavarthi
                   ` (2 preceding siblings ...)
  2022-05-16 17:20 ` [PATCH v2 1/1] common/cnxk: added additional platform macros Srikanth Yalavarthi
@ 2022-05-16 17:26 ` Srikanth Yalavarthi
  3 siblings, 0 replies; 5+ messages in thread
From: Srikanth Yalavarthi @ 2022-05-16 17:26 UTC (permalink / raw)
  To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, jerinj, sshankarnara, Srikanth Yalavarthi

Added new platform layer macros for pointer operations,
bitwise operations, spinlocks and 32 bit read and write.

Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
---
 drivers/common/cnxk/roc_platform.h | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 86987aea3b..1ad3c16705 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -41,6 +41,7 @@
 #define PLT_MEMZONE_NAMESIZE	 RTE_MEMZONE_NAMESIZE
 #define PLT_STD_C11		 RTE_STD_C11
 #define PLT_PTR_ADD		 RTE_PTR_ADD
+#define PLT_PTR_SUB		 RTE_PTR_SUB
 #define PLT_PTR_DIFF		 RTE_PTR_DIFF
 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID
 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET
@@ -70,6 +71,10 @@
 #define PLT_U32_CAST(val) ((uint32_t)(val))
 #define PLT_U16_CAST(val) ((uint16_t)(val))
 
+/* Add / Sub pointer with scalar and cast to uint64_t */
+#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x))
+#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x))
+
 /** Divide ceil */
 #define PLT_DIV_CEIL(x, y)			\
 	({					\
@@ -113,10 +118,11 @@
 #define plt_bitmap_scan			rte_bitmap_scan
 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint
 
-#define plt_spinlock_t	    rte_spinlock_t
-#define plt_spinlock_init   rte_spinlock_init
-#define plt_spinlock_lock   rte_spinlock_lock
-#define plt_spinlock_unlock rte_spinlock_unlock
+#define plt_spinlock_t	     rte_spinlock_t
+#define plt_spinlock_init    rte_spinlock_init
+#define plt_spinlock_lock    rte_spinlock_lock
+#define plt_spinlock_unlock  rte_spinlock_unlock
+#define plt_spinlock_trylock rte_spinlock_trylock
 
 #define plt_intr_callback_register   rte_intr_callback_register
 #define plt_intr_callback_unregister rte_intr_callback_unregister
@@ -165,12 +171,24 @@
 #define plt_write64(val, addr)                                                 \
 	rte_write64_relaxed((val), (volatile void *)(addr))
 
+#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr))
+#define plt_write32(val, addr)                                                 \
+	rte_write32_relaxed((val), (volatile void *)(addr))
+
 #define plt_wmb()		rte_wmb()
 #define plt_rmb()		rte_rmb()
 #define plt_io_wmb()		rte_io_wmb()
 #define plt_io_rmb()		rte_io_rmb()
 #define plt_atomic_thread_fence rte_atomic_thread_fence
 
+#define plt_bit_relaxed_get32   rte_bit_relaxed_get32
+#define plt_bit_relaxed_set32   rte_bit_relaxed_set32
+#define plt_bit_relaxed_clear32 rte_bit_relaxed_clear32
+
+#define plt_bit_relaxed_get64   rte_bit_relaxed_get64
+#define plt_bit_relaxed_set64   rte_bit_relaxed_set64
+#define plt_bit_relaxed_clear64 rte_bit_relaxed_clear64
+
 #define plt_mmap       mmap
 #define PLT_PROT_READ  PROT_READ
 #define PLT_PROT_WRITE PROT_WRITE
-- 
2.17.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2022-05-16 17:27 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-12 17:42 [PATCH 1/1] common/cnxk: added new macros to platform layer Srikanth Yalavarthi
2022-04-13  7:08 ` Morten Brørup
2022-05-14 12:20 ` Jerin Jacob
2022-05-16 17:20 ` [PATCH v2 1/1] common/cnxk: added additional platform macros Srikanth Yalavarthi
2022-05-16 17:26 ` [PATCH v2 1/1] common/cnxk: added new macros to platform layer Srikanth Yalavarthi

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