From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2868FA04FD; Tue, 14 Jan 2020 05:34:48 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8630C1C224; Tue, 14 Jan 2020 05:34:47 +0100 (CET) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by dpdk.org (Postfix) with ESMTP id E8CE91C223 for ; Tue, 14 Jan 2020 05:34:45 +0100 (CET) Received: by mail-io1-f65.google.com with SMTP id t26so12357512ioi.13 for ; Mon, 13 Jan 2020 20:34:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=jR8UBWVHa2keR9fT1O86zuU4ur+KWQyZXC6+4i4zL9g=; b=S/bhJNKw4BdOYh0tyc3ttFqD7iqvtcgqT0xhumZ+YP/vgtyERt9fgcSpS+qwpvaCh0 VT4krnLhSVWCW3igiauu7StLECa8N7hjO+3extf5DxR+RWbidtj7GZ6pyNkYMq6rCUzA nMIpjPKjcNhDASFAJeZQPMeOYwbjJOWlpdfd75rm5Y8m2VQ60T5n4nm6sT99zpTtBdBJ ZXPJwYs8P2Te+VPahWJ6ShwvU0uLzzNIOx5tZVoGT1ZEPoEhp4/rNM9NEbfa4H6xDzHZ NqcZxYdraub7B0CpB4vcyhDzLrIc/UfSiqYzQKROZT86MlVbZw6+50yMNEb0LROoU7Vn ukNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jR8UBWVHa2keR9fT1O86zuU4ur+KWQyZXC6+4i4zL9g=; b=SOo/cAgBr0ss6e83iYcRFq0UbK4Q5zhSLttIBH/Q7oZGcpbiSZvPm79UMOesmul9Q9 j5qCxjsfySLR6sMb/PuSeerCjluZUJilWnfGJyNuOFgKNOki//GthWNJjoGuBTx6YBpk EAW3kAtgvpsTpGshbIRft/H/r+PGtVdHmeY0z8eHFZglIqMdktyGILgqhdMbsJ7uwv+1 b/9onrbHNTwRplbN3QHu89b8BMKSc33V4mTKyQkHlNIVLNo050LKkzgp6/GEwafCJJPg 5EJqqimWiUo1hSAtKB6yIZXXVbYK7H0cN8RxnEwi70H7nZJOsbdPMNufVRb6bXnVs2WC wZAg== X-Gm-Message-State: APjAAAXdWMS/aINfsudqc4QXL5DlhRx7QNX9loM60YveSKJKxXA73PFe jTXROm0SC5E//D4RqK/HfdeR7EMTqXGj1YGGUCI= X-Google-Smtp-Source: APXvYqxRf/Io9HEOHtO8uz5DGANo8WP9CUYyMvDVYnPJqmP/CyGndxbdmXYqFargJc9qs5mvGt/40bJjEavNsK5AlDw= X-Received: by 2002:a6b:c742:: with SMTP id x63mr15634812iof.162.1578976485199; Mon, 13 Jan 2020 20:34:45 -0800 (PST) MIME-Version: 1.0 References: <20191221013451.28588-1-rmody@marvell.com> In-Reply-To: <20191221013451.28588-1-rmody@marvell.com> From: Jerin Jacob Date: Tue, 14 Jan 2020 10:04:29 +0530 Message-ID: To: Rasesh Mody , Ferruh Yigit Cc: dpdk-dev , Jerin Jacob , GR-Everest-DPDK-Dev , stable@dpdk.com Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH] net/qede/base: fix number of ports per engine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Sat, Dec 21, 2019 at 7:05 AM Rasesh Mody wrote: > > Fix the way in which the number of ports per engine of an adapter is > determined by reading port mode register. Set default value to 1. > > Fixes: 3b307c55f2ac ("net/qede/base: update FW to 8.40.25.0") > Cc: stable@dpdk.com Corrected Cc to stable@dpdk.org Applied to dpdk-next-net-mrvl/master. Thanks > > Signed-off-by: Rasesh Mody > --- > drivers/net/qede/base/ecore_dev.c | 38 ++++++++++++++++++++++--------- > 1 file changed, 27 insertions(+), 11 deletions(-) > > diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c > index 9d1db14590..f33b9910c0 100644 > --- a/drivers/net/qede/base/ecore_dev.c > +++ b/drivers/net/qede/base/ecore_dev.c > @@ -5253,7 +5253,6 @@ static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn, > > /* MISCS_REG_ECO_RESERVED[15:12]: num of ports in an engine */ > eco_reserved = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED); > - > switch ((eco_reserved & 0xf000) >> 12) { > case 1: > p_dev->num_ports_in_engine = 1; > @@ -5268,7 +5267,7 @@ static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn, > DP_NOTICE(p_hwfn, false, > "Emulation: Unknown port mode [ECO_RESERVED 0x%08x]\n", > eco_reserved); > - p_dev->num_ports_in_engine = 2; /* Default to something */ > + p_dev->num_ports_in_engine = 1; /* Default to something */ > break; > } > > @@ -5281,8 +5280,8 @@ static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn, > static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, > struct ecore_ptt *p_ptt) > { > + u32 addr, global_offsize, global_addr, port_mode; > struct ecore_dev *p_dev = p_hwfn->p_dev; > - u32 addr, global_offsize, global_addr; > > #ifndef ASIC_ONLY > if (CHIP_REV_IS_TEDIBEAR(p_dev)) { > @@ -5304,15 +5303,32 @@ static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, > return; > } > > - addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, > - PUBLIC_GLOBAL); > - global_offsize = ecore_rd(p_hwfn, p_ptt, addr); > - global_addr = SECTION_ADDR(global_offsize, 0); > - addr = global_addr + OFFSETOF(struct public_global, max_ports); > - p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr); > + /* Determine the number of ports per engine */ > + port_mode = ecore_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE); > + switch (port_mode) { > + case 0x0: > + p_dev->num_ports_in_engine = 1; > + break; > + case 0x1: > + p_dev->num_ports_in_engine = 2; > + break; > + case 0x2: > + p_dev->num_ports_in_engine = 4; > + break; > + default: > + DP_NOTICE(p_hwfn, false, "Unknown port mode 0x%08x\n", > + port_mode); > + p_dev->num_ports_in_engine = 1; /* Default to something */ > + break; > + } > > - p_dev->num_ports_in_engine = p_dev->num_ports >> > - (ecore_device_num_engines(p_dev) - 1); > + /* Get the total number of ports of the device */ > + addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, > + PUBLIC_GLOBAL); > + global_offsize = ecore_rd(p_hwfn, p_ptt, addr); > + global_addr = SECTION_ADDR(global_offsize, 0); > + addr = global_addr + OFFSETOF(struct public_global, max_ports); > + p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr); > } > > static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn, > -- > 2.18.0 >