From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C9FCDA04F3; Fri, 20 Dec 2019 05:34:44 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DA7281BE3D; Fri, 20 Dec 2019 05:34:43 +0100 (CET) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by dpdk.org (Postfix) with ESMTP id 7545C1BDFD for ; Fri, 20 Dec 2019 05:34:42 +0100 (CET) Received: by mail-io1-f67.google.com with SMTP id b10so8085321iof.11 for ; Thu, 19 Dec 2019 20:34:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=s0aUnVtaFyxOtSWnx+9TLqJtXf1mYwmCd1D7rDEFb6k=; b=Mv6wKUw2orBUzT+h+AW1db6k6R4UDS+EESj04GG7GvVSBuCje1k/P/YbISZY/vEipc 8cekcgx+Lz3fDr8GK6LOgmuiOz8rffi3jgYPZAiT3YPB+YSTNRG1a1WgmkBw3bDjiXAB DOsFTR9G43agWz1WETN6IjStThNDFLK1IVJ7CKaRXLwEw4K+5/y/XTcocCSvR9fbVAOr p+1zDQYwKXSsmuEBeUNPVM1YaEm1Q5Q6gHfcJq8rz43aQiGCGj1bm6aF7yTwZSDYsfq3 NuWRlEhl3Bx9kb4bsjCIKdaXXGbr0vtA8YSv7udkLDR3DbQyAuVKkwCbm+The6J0hNMY scAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=s0aUnVtaFyxOtSWnx+9TLqJtXf1mYwmCd1D7rDEFb6k=; b=cXVthmineZzG/mPM1HQLHPGBZUIgK3WQ0xxuKCbDgoKHzvmZtX/L1WfKUANykh9NRi phXA/4Z0iW5f0g2UA1aQY6K5ENEeYJCQ7KwDgu4DJEwUmNgap4l7UXMwU/7eYiHwTR66 CWpuGF5kr54wJg/I2Z1EBYQFFVdCTLAEbmIbNsDv+AoaUZLobM5S31wkWQ88DBWf096A ZbcDJaDoWb87wYFHHmk3ICRW4GUIC6BOvug6REmgNOmy9dWwrS07SVAV20eeBgY8fInC 3Bc0sqOQmILXKjpwjn8ECZZ23xItc23NNlT/NLhts0BpQlOK1Q4CR+UGcYNqO2HTHcJY XR/A== X-Gm-Message-State: APjAAAUuTaOeA6QoJBBm/0l8VP8FC6qkRCRjEKDzvpt6YlEdpHavw98W jduM3IwoXlS4x9ceqJV5uzYXUAn7GItAIqpdELo= X-Google-Smtp-Source: APXvYqy7cT2xfb4bPLnwH+QALAZ/ob3Ct1w1JjrF4QpK4ybmxdROEBN7SqNZtsawqj1Vim/1HUBuJin6mISl6Z+X+Ks= X-Received: by 2002:a05:6638:a2c:: with SMTP id 12mr10674058jao.60.1576816481613; Thu, 19 Dec 2019 20:34:41 -0800 (PST) MIME-Version: 1.0 References: <1571758074-16445-1-git-send-email-gavin.hu@arm.com> <1576811391-19131-1-git-send-email-gavin.hu@arm.com> <1576811391-19131-2-git-send-email-gavin.hu@arm.com> In-Reply-To: From: Jerin Jacob Date: Fri, 20 Dec 2019 10:04:25 +0530 Message-ID: To: Gavin Hu Cc: dpdk-dev , nd , David Marchand , "thomas@monjalon.net" , "rasland@mellanox.com" , "maxime.coquelin@redhat.com" , "tiwei.bie@intel.com" , "hemant.agrawal@nxp.com" , "jerinj@marvell.com" , Pavan Nikhilesh , Honnappa Nagarahalli , Ruifeng Wang , Phil Yang , Joyce Kong , Steve Capper Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Dec 20, 2019 at 9:49 AM Gavin Hu wrote: > > Hi Jerin, > > Thanks for review, inline comments, > > > -----Original Message----- > > From: Jerin Jacob > > Sent: Friday, December 20, 2019 11:38 AM > > To: Gavin Hu > > Cc: dpdk-dev ; nd ; David Marchand > > ; thomas@monjalon.net; > > rasland@mellanox.com; maxime.coquelin@redhat.com; > > tiwei.bie@intel.com; hemant.agrawal@nxp.com; jerinj@marvell.com; > > Pavan Nikhilesh ; Honnappa Nagarahalli > > ; Ruifeng Wang > > ; Phil Yang ; Joyce Kong > > ; Steve Capper > > Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for > > aarch64 > > > > On Fri, Dec 20, 2019 at 9:03 AM Jerin Jacob > > wrote: > > > > > > On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu wrote: > > > > > > > > Armv8's peripheral coherence order is a total order on all reads and > > writes > > > > to that peripheral.[1] > > > > > > > > The peripheral coherence order for a memory-mapped peripheral > > signifies the > > > > order in which accesses arrive at the endpoint. For a read or a write > > RW1 > > > > and a read or a write RW2 to the same peripheral, then RW1 will appear > > in > > > > the peripheral coherence order for the peripheral before RW2 if either > > of > > > > the following cases apply: > > > > 1. RW1 and RW2 are accesses using Non-cacheable or Device attributes > > and > > > > RW1 is Ordered-before RW2. > > > > 2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE > > attributes > > > > and RW1 appears in program order before RW2. > > > > > > > > > This is true if RW1 and RW2 addresses are device memory. i.e the > > > registers in the PCI bar address. > > > If RW1 is DDR address which is been used by the controller(say NIC > > > ring descriptor) then there will be an issue. > > > For example Intel i40e driver, the admin queue update in Host DDR > > > memory and it updates the doorbell. > > > In such a case, this patch will create an issue. Correct? Have you > > > checked this patch with ARM64 + XL710 controllers? > > This patch relaxes the rte_io_*mb barriers for pure PCI device memory accesses. Yes. This would break cases for mixed access fro i40e drivers. > > For mixed accesses of DDR and PCI device memory, rte_smp_*mb(DMB ISH) is not sufficient. > But rte_cio_*mb(DMB OSH) is sufficient and can be used. Yes. Let me share a bit of history. 1) There are a lot of drivers(initially developed in x86) that have mixed access and don't have any barriers as x86 does not need it. 2) rte_io introduced to fix that 3) Item (2) introduced the performance issues in the fast path as an optimization rte_cio_* introduced. So in the current of the scheme of things, we have APIs to FIX portability issue(rte_io) and performance issue(rte_cio). IMO, we may not need any change in infra code now. If you think, the documentation is missing then we can enhance it. If we make infra change then again drivers needs to be updated and tested.