From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D33D5A00BE; Thu, 17 Feb 2022 14:25:43 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B5F3C40150; Thu, 17 Feb 2022 14:25:43 +0100 (CET) Received: from mail-il1-f178.google.com (mail-il1-f178.google.com [209.85.166.178]) by mails.dpdk.org (Postfix) with ESMTP id 13F0340042 for ; Thu, 17 Feb 2022 14:25:42 +0100 (CET) Received: by mail-il1-f178.google.com with SMTP id d7so2226870ilf.8 for ; Thu, 17 Feb 2022 05:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VCTQaziyYvYglmDsoDq6Cs3deslwBKvv3XWlV7QT7ow=; b=NLl2+INgCvP+KoNenRum0jDkqmoew4yTvxzVVE7A6t1iNLCmgRHZm+1ylygQ9ZSK/E gLwII3hWR2R/6CDXOex+p9sXbFPMF1LTyu0YgoRuT7fJ7IsKuFXFMsEnWVvHVMK19waq YCfSKtECOchPvdtna4MCcUUChJi/G/Zp242PqSFT773si7smAamZFom1XmBe5qQD5xDx HjIpfOAbUCj9R165gDBsH5YRzkc6EQLS94xEq4MhzKga2M6V6OHzeGndCK6r11yJL4Bz 3jJvivMbB3sedLKmUqJ73CdA7v9BG3WCcP7laX8veMgGCSu3gM0wIKBqisUtyVsZLbru TQHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VCTQaziyYvYglmDsoDq6Cs3deslwBKvv3XWlV7QT7ow=; b=PEj2jJhvkRPdlLrFTV8fbDk2jaJJwiMGOXpbTCCBZ9AULh78mITexkg2iCTxoez6vQ PqQODKwoiEul6+ZrywLFxM54nSTxEyLKVmRCJhqSzBS/Uke9rnaLjp/mbSsK38Xj2eI9 yGqy8D/z7rJA7CCfI6pNNcLLvo4VSJVlPMm3O5XpCSxiCDW17NGYEU2hff+MKqrhrJ4x Ba1iL+u99SZCu5kmYQ5vghg6XV2vGFTwnb76JWXifihalykWtIk8E1miluI7+xD2uctW IP9i+B4INgwWfekHEjJe9o/B68CVRjCS2L2Udo6rsp9MqlUb6iJJNcDwN6yXEgZwkJm3 TfVQ== X-Gm-Message-State: AOAM530Hs7fz8VXfD+MWAVCeJ8icGCdOOp3Vjlr6gE4B8FD7vVITdFVP MRajqssW+LIJOWvQkYgNz00LmANffcKuww63eUE= X-Google-Smtp-Source: ABdhPJzsTmuknqp0xdpiq647cSrisSr3m9xadQC3VjXDFtaDvY4Tb+SSnc0wbKJ7J6mui7iiMOwfD832Hej70IkWE+I= X-Received: by 2002:a05:6e02:1c22:b0:2b9:dcbb:e810 with SMTP id m2-20020a056e021c2200b002b9dcbbe810mr1885343ilh.262.1645104337486; Thu, 17 Feb 2022 05:25:37 -0800 (PST) MIME-Version: 1.0 References: <20220207072932.22409-1-ndabilpuram@marvell.com> <20220207072932.22409-8-ndabilpuram@marvell.com> In-Reply-To: <20220207072932.22409-8-ndabilpuram@marvell.com> From: Jerin Jacob Date: Thu, 17 Feb 2022 18:55:11 +0530 Message-ID: Subject: Re: [PATCH 08/20] common/cnxk: use SSO time counter threshold for IRQ To: Nithin Dabilpuram Cc: Jerin Jacob , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , dpdk-dev Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Mon, Feb 7, 2022 at 1:00 PM Nithin Dabilpuram wrote: > > Enable time counter based threshold for raising SSO > EXE_INT instead of IAQ threshold. Please update the reason for doing the same. > > Signed-off-by: Nithin Dabilpuram > --- > drivers/common/cnxk/roc_nix_inl_dev_irq.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c > index d758e0c..8a0cb74 100644 > --- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c > +++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c > @@ -5,6 +5,8 @@ > #include "roc_api.h" > #include "roc_priv.h" > > +#define WORK_LIMIT 1000 > + > static void > nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev) > { > @@ -15,6 +17,7 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev) > __uint128_t get_work; > uint64_t u64[2]; > } gw; > + uint16_t cnt = 0; > uint64_t work; > > again: > @@ -33,7 +36,9 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev) > else > plt_warn("Undelivered inl dev work gw0: %p gw1: %p", > (void *)gw.u64[0], (void *)gw.u64[1]); > - goto again; > + cnt++; > + if (cnt < WORK_LIMIT) > + goto again; > } > > plt_atomic_thread_fence(__ATOMIC_ACQ_REL); > @@ -138,8 +143,10 @@ nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev) > /* Enable hw interrupt */ > plt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1S); > > - /* Setup threshold for work exec interrupt to 1 wqe in IAQ */ > - plt_write64(0x1ull, sso_base + SSO_LF_GGRP_INT_THR); > + /* Setup threshold for work exec interrupt to 100us timeout > + * based on time counter. > + */ > + plt_write64(BIT_ULL(63) | 10ULL << 48, sso_base + SSO_LF_GGRP_INT_THR); > > return rc; > } > -- > 2.8.4 >