From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DC45CA0C43; Mon, 6 Sep 2021 15:20:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 67BA7410EF; Mon, 6 Sep 2021 15:20:57 +0200 (CEST) Received: from mail-il1-f174.google.com (mail-il1-f174.google.com [209.85.166.174]) by mails.dpdk.org (Postfix) with ESMTP id CFDBF410ED for ; Mon, 6 Sep 2021 15:20:55 +0200 (CEST) Received: by mail-il1-f174.google.com with SMTP id l10so6803033ilh.8 for ; Mon, 06 Sep 2021 06:20:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CDO0TE9+bNJo6tKVGsAlSLbb3pNAeR7K3Sa5704pkcU=; b=G5WNziv9m6vJw9WsuBj2ZIC7QFtIb1FKCLmB9w9wDZwrMJulovEJmPU29LPstC+0Sq V+nsuQsaDLsIiFl2aGAuW8ztzEvedVXxH2NZSHfIuINyPylwHdcFWGd6QTtF0lAyp3Z4 /8zKe6fx+18j2hfH/KGttlLhUvXq9KOxZyBLLcFG3WdUy7MMnuJNz6QYXzoCPACFWfNq pYwOCZs6zSGvEUhmUI/o6vMjtHY5vteZ1+X4Eje2AzoLwcsKpL9QwwSFXxQCf4ICg4Xe OEKUsB1655y8baquDJkX7DFiGfDn/OcNmAz85NIL784QCbKzTYTxMbyXiRhJOt+UF6ik B68Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CDO0TE9+bNJo6tKVGsAlSLbb3pNAeR7K3Sa5704pkcU=; b=cOP8f+eyw3+8v5uwbv7bZDUnmJKLj7sMlVNWJadQK6MjzV/Dr9N9DfCA51S6pBqkz0 AJAdMciqDAsL87eM+sEy9HcEWyfjD9D4BbAweNRm5t9wsLAoCw9AMYWXFTdZJqa49HT8 UcfXaOkX7WZYumpGzmgd+TL1mjrrXbAmcv/uKaLt9c43Ssl/X8x/odkcBN7UrkV9V1tq TMOmCSe5JrwL1G58/5s03mw92gfZUNnEslIlX1zoClSm3v81nBVJKpXKfjvyyM0so5EW pt4pS4tBMTERJnFD9Ws/HNjWWAfOttlWmi+ydg+Nw6g7zj+uUEnQ5ruOryhbyevkcCfp nbKA== X-Gm-Message-State: AOAM532ew7k4Rj2avlnI/Xhl7jSnCFn9hUTpP5XUzcpjL+Cv6SaMwL3w hgRUFLil4ULfi2PlNZGLw+Un7vfxjjWOJlGY/SY= X-Google-Smtp-Source: ABdhPJzriSIMtrqvegWt+92FQXfUZED7RnBnz9ieYoI1nwrgI4Yz9rY+sdqfxX7/JY8Tiu3z/J2LoaYdJdcY01zqYh0= X-Received: by 2002:a05:6e02:1a4f:: with SMTP id u15mr8312628ilv.251.1630934455107; Mon, 06 Sep 2021 06:20:55 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Jerin Jacob Date: Mon, 6 Sep 2021 18:50:28 +0530 Message-ID: To: Shijith Thotton Cc: dpdk-dev , Jerin Jacob , Pavan Nikhilesh Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2] event/cnxk: reduce max timer chunk pool cache size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Aug 30, 2021 at 9:45 PM Shijith Thotton wrote: > > Reduced max chunk pool cache size from RTE_MEMPOOL_CACHE_MAX_SIZE(512) > to 128. > > If chunk pool cache is empty, it gets filled during arm. Filling 512 > entries at a time will fail arm if timeout is shorter. > > Fixes: 0e792433d051 ("event/cnxk: create and free timer adapter") > > Signed-off-by: Shijith Thotton Applied to dpdk-next-net-eventdev/for-main. Thanks > --- > v2: > * Rebased. > > drivers/event/cnxk/cnxk_tim_evdev.c | 4 ++-- > drivers/event/cnxk/cnxk_tim_evdev.h | 1 + > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c > index 9d40e336d7..c3e9dc508c 100644 > --- a/drivers/event/cnxk/cnxk_tim_evdev.c > +++ b/drivers/event/cnxk/cnxk_tim_evdev.c > @@ -27,8 +27,8 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring, > snprintf(pool_name, sizeof(pool_name), "cnxk_tim_chunk_pool%d", > tim_ring->ring_id); > > - if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE) > - cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE; > + if (cache_sz > CNXK_TIM_MAX_POOL_CACHE_SZ) > + cache_sz = CNXK_TIM_MAX_POOL_CACHE_SZ; > cache_sz = cache_sz != 0 ? cache_sz : 2; > tim_ring->nb_chunks += (cache_sz * rte_lcore_count()); > if (!tim_ring->disable_npa) { > diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h > index c369f6f472..9d95c45a7b 100644 > --- a/drivers/event/cnxk/cnxk_tim_evdev.h > +++ b/drivers/event/cnxk/cnxk_tim_evdev.h > @@ -31,6 +31,7 @@ > #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1) > #define CNXK_TIM_MIN_CHUNK_SLOTS (0x1) > #define CNXK_TIM_MAX_CHUNK_SLOTS (0x1FFE) > +#define CNXK_TIM_MAX_POOL_CACHE_SZ (128) > > #define CN9K_TIM_MIN_TMO_TKS (256) > > -- > 2.25.1 >