From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BD79AA0032; Thu, 17 Feb 2022 10:27:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8619A40150; Thu, 17 Feb 2022 10:27:42 +0100 (CET) Received: from mail-il1-f172.google.com (mail-il1-f172.google.com [209.85.166.172]) by mails.dpdk.org (Postfix) with ESMTP id 3BDA840042 for ; Thu, 17 Feb 2022 10:27:41 +0100 (CET) Received: by mail-il1-f172.google.com with SMTP id m8so1818390ilg.7 for ; Thu, 17 Feb 2022 01:27:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=TXyzzcS3b1Va8/XB023NPJqGGHDOQB9r44pPhIblo8s=; b=i3Tkkac85i+EkFxWZzQjOjR07k0CpmUdM4Z0HyXyHAW6FZPZFXqgel9o7BLZR7oIYT AXj4CR00kE6Sn/aExqA9UMXYpewish6xo5oCg3VjWuySMFtpaS+YV5qvMhyQddjg+zyA 7/00JytOzR2/QtF0qITnQUbeBJy82IJx3xTxwlHIEK4BBJdT5KhqauBruJlmOKL3Zwsm TgrfAdUBaKVN4PhXvfRVu52Gp0UKG1AYnTpbdewVpb1eeQuVP8RLnKdBJMXrFCRl+Uk2 5uHD5N3iPSwOfXcea/XTdLVMo1AGs/xhndSvCKUrRrWQHOw0jI9AfuKEDF0f8ox4hEC0 NU4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=TXyzzcS3b1Va8/XB023NPJqGGHDOQB9r44pPhIblo8s=; b=nZG5davZlPB5r8pTxvGj9JvpCezowtEHy5SpHPhbagl1s4Cqgn/+LRQ3mvnzhfTpMP R7HzZKcmddYfEM3clXnfJQdPEhNZf5kntbr5sCe3wgth6xLrCn41dda9Wh5p2Q4DWxMY wOe5W0M8XMso9cgIF0MRTNedWfQW9HQBcduTbSIAuWxoBH3vrVOjpNUlYHdAuv9kXsKy 1ryVfNOtLQTVVMwfz1P/bSXRCzuUc8NuaDlK+k7zw5xLuUBKPb3CfpVBSuayk2GSFNYf JVi59s3opEWXh7chMTcYJXXvxzaHT1w9sk0bg1otT3mJD6IofVmkhD6kd6vwqB7PM9Th Es6Q== X-Gm-Message-State: AOAM532NVPu2OLNrCFf0kuEfgfw6Vxi7X7VqYPSQoxnQn5WCod2xGQhg k0RRhw9D69jlnzzLgJvqx03e6nG1YHkvE0jx5bg= X-Google-Smtp-Source: ABdhPJzxkkP8maBz6Dwxf7okJIuk5MpibimOTD8GXCQ7QtaFbkZfB9Ei5EJE2sVkAC19vkPlnbFdj1JMNulY+zC8k3E= X-Received: by 2002:a05:6e02:1788:b0:2be:ffc9:8bb2 with SMTP id y8-20020a056e02178800b002beffc98bb2mr1566100ilu.294.1645090060583; Thu, 17 Feb 2022 01:27:40 -0800 (PST) MIME-Version: 1.0 References: <20220113121807.187105-1-hkalra@marvell.com> <20220131105210.183152-1-hkalra@marvell.com> In-Reply-To: <20220131105210.183152-1-hkalra@marvell.com> From: Jerin Jacob Date: Thu, 17 Feb 2022 14:57:14 +0530 Message-ID: Subject: Re: [PATCH v2] common/cnxk: enable NIX Tx interrupts errata To: Harman Kalra Cc: dpdk-dev , Nithin Dabilpuram Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Mon, Jan 31, 2022 at 4:22 PM Harman Kalra wrote: > > An errata exists whereby NIX may incorrectly overwrite the value in > NIX_SQ_CTX_S[SQ_INT]. This may cause set interrupts to get cleared or > causing an QINT when no error is outstanding. > As a workaround, software should always read all SQ debug registers > and not just rely on NIX_SQINT_E bits set in NIX_SQ_CTX_S[SQ_INT]. > Also for detecting SQB faults software must read SQ context and > check id next_sqb is NULL. > > Signed-off-by: Harman Kalra Acked-by: Jerin Jacob Applied to dpdk-next-net-mrvl/for-next-net. Thanks > --- > V2: > * Rebase on branch code > > drivers/common/cnxk/roc_nix_irq.c | 64 ++++++++++++++++++++++--------- > 1 file changed, 46 insertions(+), 18 deletions(-) > > diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c > index 7dcd533ea9..71971ef261 100644 > --- a/drivers/common/cnxk/roc_nix_irq.c > +++ b/drivers/common/cnxk/roc_nix_irq.c > @@ -196,18 +196,42 @@ nix_lf_sq_irq_get_and_clear(struct nix *nix, uint16_t sq) > return nix_lf_q_irq_get_and_clear(nix, sq, NIX_LF_SQ_OP_INT, ~0x1ff00); > } > > -static inline void > +static inline bool > +nix_lf_is_sqb_null(struct dev *dev, int q) > +{ > + bool is_sqb_null = false; > + volatile void *ctx; > + int rc; > + > + rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, &ctx); > + if (rc) { > + plt_err("Failed to get sq context"); > + } else { > + is_sqb_null = > + roc_model_is_cn9k() ? > + (((__io struct nix_sq_ctx_s *)ctx)->next_sqb == > + 0) : > + (((__io struct nix_cn10k_sq_ctx_s *)ctx) > + ->next_sqb == 0); > + } > + > + return is_sqb_null; > +} > + > +static inline uint8_t > nix_lf_sq_debug_reg(struct nix *nix, uint32_t off) > { > + uint8_t err = 0; > uint64_t reg; > > reg = plt_read64(nix->base + off); > if (reg & BIT_ULL(44)) { > - plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff), > - (uint8_t)(reg & 0xff)); > + err = reg & 0xff; > /* Clear valid bit */ > plt_write64(BIT_ULL(44), nix->base + off); > } > + > + return err; > } > > static void > @@ -229,6 +253,7 @@ nix_lf_q_irq(void *param) > struct dev *dev = &nix->dev; > int q, cq, rq, sq; > uint64_t intr; > + uint8_t rc; > > intr = plt_read64(nix->base + NIX_LF_QINTX_INT(qintx)); > if (intr == 0) > @@ -269,22 +294,25 @@ nix_lf_q_irq(void *param) > sq = q % nix->qints; > irq = nix_lf_sq_irq_get_and_clear(nix, sq); > > - if (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) { > - plt_err("SQ=%d NIX_SQINT_LMT_ERR", sq); > - nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG); > - } > - if (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) { > - plt_err("SQ=%d NIX_SQINT_MNQ_ERR", sq); > - nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG); > - } > - if (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) { > - plt_err("SQ=%d NIX_SQINT_SEND_ERR", sq); > - nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); > - } > - if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) { > + /* Detect LMT store error */ > + rc = nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG); > + if (rc) > + plt_err("SQ=%d NIX_SQINT_LMT_ERR, errcode %x", sq, rc); > + > + /* Detect Meta-descriptor enqueue error */ > + rc = nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG); > + if (rc) > + plt_err("SQ=%d NIX_SQINT_MNQ_ERR, errcode %x", sq, rc); > + > + /* Detect Send error */ > + rc = nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); > + if (rc) > + plt_err("SQ=%d NIX_SQINT_SEND_ERR, errcode %x", sq, rc); > + > + /* Detect SQB fault, read SQ context to check SQB NULL case */ > + if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL) || > + nix_lf_is_sqb_null(dev, q)) > plt_err("SQ=%d NIX_SQINT_SQB_ALLOC_FAIL", sq); > - nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); > - } > } > > /* Clear interrupt */ > -- > 2.18.0 >