From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BA29A04B3; Sat, 21 Dec 2019 06:06:35 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A9ECA378E; Sat, 21 Dec 2019 06:06:33 +0100 (CET) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by dpdk.org (Postfix) with ESMTP id 599771252; Sat, 21 Dec 2019 06:06:32 +0100 (CET) Received: by mail-il1-f195.google.com with SMTP id f5so9794048ilq.5; Fri, 20 Dec 2019 21:06:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5ZLVXGiOqwvW1vmZpQri4Fb3dUpaefU2QvUYfvDbrK8=; b=RkrgtlduKNbV9HECMBZcFD4W0T3w8DHe328f6XIEUk+277z7w2XyKNmDs7dxYAQ1sW cwboWW5hpheCbcweEpFO7uA7FsPR66nGcCQTq7UIn95k0LLeQgTcqhcs8KxSxFmBcfH6 5P4E8x02Eo5Hkl4Ja4hN55kj5uE2nx2gOKpv2iyIw4AefZHAdsSyO2L7NNrYdACUq9yC sL3/WgOLRt5zMzq5YclDVt3BL0r5zhNgV+cejdQp2cYfA5Uj53aSfITP5OND5XPAD3WD fCth5p8MfgWnT0QbelfWXKfKgIfjBIeKN7+l9DNhSa8eaTA1E1ideLS3Y7s6ZuoAcV78 dYfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=5ZLVXGiOqwvW1vmZpQri4Fb3dUpaefU2QvUYfvDbrK8=; b=i51e/7m09thpaNszoIRBRGD6cXbKv/CQu8KDGbxVHSrkliUpdl6HlPFq82F6IshJ+1 wmWrYb2T8zFaaw2MJ5qzcYFon4bkk7lDmCMEt7tHtkZJsqnmbG0XoJntl3Q5zNFPtWyn YZCpxNy3HUyKcS6eqWcDZGRT6jC5ZfEEYYbGvMtJF04TpfduoC5Nngx8GeVxnyxjWiAT JdUbAUPs2s12bgOgd4CETW7kwrx6u4lBcw7GJcRE6q1EFW2BYYghu1HGWAMVDMjAfNKo xp9wDYCz8gFQ3DrDOMcMz7+KykWaSsUMsHZ3EmpFLoonPEDzg4189qZMWRjsBi+f+KeP X+wA== X-Gm-Message-State: APjAAAXdnT3Jwi4ckG8TaafRxdbe2YP05/65nabw5xehfXgcQ4U/dEJ1 w7E71UdD+b55w4wooi+PU17GC2IAFIw3GXFMrkU= X-Google-Smtp-Source: APXvYqx492t/MvWXdJebqe4wxxJr2r+pN1kjhQAxs9qdQIZMsPALiDMfaTldvkedM2NURlbyW9D4Oczdw4rAailXBlo= X-Received: by 2002:a92:481d:: with SMTP id v29mr15751552ila.271.1576904791550; Fri, 20 Dec 2019 21:06:31 -0800 (PST) MIME-Version: 1.0 References: <20191219134227.3841799-1-jerinj@marvell.com> In-Reply-To: From: Jerin Jacob Date: Sat, 21 Dec 2019 10:36:15 +0530 Message-ID: To: Honnappa Nagarahalli Cc: "jerinj@marvell.com" , "dev@dpdk.org" , "thomas@monjalon.net" , "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "bruce.richardson@intel.com" , "konstantin.ananyev@intel.com" , "hemant.agrawal@nxp.com" , "shahafs@mellanox.com" , Gavin Hu , "viktorin@rehivetech.com" , "drc@linux.vnet.ibm.com" , "anatoly.burakov@intel.com" , "stable@dpdk.org" , nd Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH] mempool: fix mempool obj alignment for non x86 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Sat, Dec 21, 2019 at 2:37 AM Honnappa Nagarahalli wrote: > > > > > > From: Jerin Jacob > > > > > > > > The exiting optimize_object_size() function address the memory > > > > object alignment constraint on x86 for better performance. > > > > > > > > Different (Mirco) architecture may have different memory alignment > > > > constraint for better performance and it not same as the existing > > > > optimize_object_size() function. Some use, XOR(kind of CRC) scheme > > > > to enable DRAM channel distribution based on the address and some > > > > may have a different formula. > > > If I understand correctly, address interleaving is the characteristic of the > > memory controller and not the CPU. > > > For ex: different SoCs using the same Arm architecture might have different > > memory controllers. So, the solution should not be architecture specific, but > > SoC specific. > > > > Yes. See below. > > > > > > -static unsigned optimize_object_size(unsigned obj_size) > > > > +static unsigned > > > > +arch_mem_object_align(unsigned obj_size) > > > > { > > > > unsigned nrank, nchan; > > > > unsigned new_obj_size; > > > > @@ -99,6 +101,13 @@ static unsigned optimize_object_size(unsigned > > > > obj_size) > > > > new_obj_size++; > > > > return new_obj_size * RTE_MEMPOOL_ALIGN; } > > > > +#else > > > This applies to add Arm (PPC as well) SoCs which might have different > > schemes depending on the memory controller. IMO, this should not be > > architecture specific. > > > > I agree in principle. > > I will summarize the > > https://www.mail-archive.com/dev@dpdk.org/msg149157.html feedback: > > > > 1) For x86 arch, it is architecture-specific > > 2) For power PC arch, It is architecture-specific > > 3) For the ARM case, it will be the memory controller specific. > > 4) For the ARM case, The memory controller is not using the existing > > x86 arch formula. > > 5) If it is memory/arch-specific, Can userspace code find the optimal > > alignment? In the case of octeontx2/arm64, the memory controller does XOR > > on PA address which userspace code doesn't have much control. > > > > This patch address the known case of (1), (2), (4) and (5). (2) can be added to > > this framework when POWER9 folks want it. > > > > We can extend this patch to address (3) if there is a case. Without the actual > > requirement(If some can share the formula of alignment which is the > > memory controller specific and it does not come under (4))) then we can > > create extra layer for the memory controller and abstraction to probe it. > > Again there is no standard way of probing the memory controller in > > userspace and we need platform #define, which won't work for distribution > > build. > > So solution needs to be arch-specific and then fine-tune to memory controller > > if possible. > > > > I can work on creating an extra layer of code if some can provide the details > > of the memory controller and probing mechanism or this patch be extended > Inputs for BlueField, DPAAx, ThunderX2 would be helpful. Yes. Probably memory controller used in n1sdp SoC also. > > > to support such case if it arises in future. > > > > Thoughts? > How much memory will this save for your platform? Is it affecting performance? No performance difference. The existing code adding the tailer for each objs. Additional space/Trailer space will be function of number of objects in mempool and its obj_size, its alignment and selected rte_memory_get_nchannel() and rte_memory_get_nrank() I will wait for inputs from Bluefield, DPAAx, ThunderX2 and n1sdp(if any) for any rework on the patch. > > > > > > > > > > +static unsigned > > > > +arch_mem_object_align(unsigned obj_size) { > > > > + return obj_size; > > > > +} > > > > +#endif > > > > > > > > struct pagesz_walk_arg { > > > > int socket_id; > > > > @@ -234,8 +243,8 @@ rte_mempool_calc_obj_size(uint32_t elt_size, > > > > uint32_t flags, > > > > */ > > > > if ((flags & MEMPOOL_F_NO_SPREAD) == 0) { > > > > unsigned new_size; > > > > - new_size = optimize_object_size(sz->header_size + sz- > > > > >elt_size + > > > > - sz->trailer_size); > > > > + new_size = arch_mem_object_align > > > > + (sz->header_size + sz->elt_size + > > > > + sz->trailer_size); > > > > sz->trailer_size = new_size - sz->header_size - sz->elt_size; > > > > } > > > > > > > > -- > > > > 2.24.1 > > >