* [dpdk-dev] [PATCH] common/cnxk: avoid using stype STSTP in batch alloc
@ 2021-08-30 14:08 Ashwin Sekhar T K
2021-08-30 16:29 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Ashwin Sekhar T K
0 siblings, 1 reply; 8+ messages in thread
From: Ashwin Sekhar T K @ 2021-08-30 14:08 UTC (permalink / raw)
To: dev
Cc: jerinj, skori, skoteshwar, pbhagavatula, kirankumark, psatheesh,
asekhar, ndabilpuram, gakhil
Avoid using stype STSTP in batch alloc.
This is a workaround for errata IPBUNPA-37480.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
drivers/common/cnxk/roc_nix_queue.c | 5 +++++
drivers/common/cnxk/roc_nix_tm_ops.c | 8 ++++++++
drivers/common/cnxk/roc_npa.h | 2 +-
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 7e2f86eca7..1c1de8310d 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -585,6 +585,11 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
memset(&aura, 0, sizeof(aura));
aura.fc_ena = 1;
+ if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0())
+ /* Setting for cn10ka A0 due to Errata IPBUNPA-37480 */
+ aura.fc_stype = 0x0; /* STF */
+ else
+ aura.fc_stype = 0x3; /* STSTP */
aura.fc_addr = (uint64_t)sq->fc;
aura.fc_hyst_bits = 0; /* Store count on all updates */
rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, NIX_MAX_SQB, &aura,
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index ed244d4214..abddf54dcc 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -38,6 +38,14 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)
req->aura.fc_ena = enable;
req->aura_mask.fc_ena = 1;
+ if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0()) {
+ /* Setting for cn10ka A0 due to Errata IPBUNPA-37480 */
+ req->aura.fc_stype = 0x0; /* STF */
+ req->aura_mask.fc_stype = 0x0; /* STF */
+ } else {
+ req->aura.fc_stype = 0x3; /* STSTP */
+ req->aura_mask.fc_stype = 0x3; /* STSTP */
+ }
rc = mbox_process(mbox);
if (rc)
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 3fc6192e57..af0274ecb6 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -214,7 +214,7 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf,
cmp.u = 0;
cmp.compare_s.aura = roc_npa_aura_handle_to_aura(aura_handle);
cmp.compare_s.drop = drop;
- cmp.compare_s.stype = ALLOC_STYPE_STSTP;
+ cmp.compare_s.stype = ALLOC_STYPE_STF; /* Errata IPBUNPA-37480 */
cmp.compare_s.dis_wait = dis_wait;
cmp.compare_s.count = num;
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models
2021-08-30 14:08 [dpdk-dev] [PATCH] common/cnxk: avoid using stype STSTP in batch alloc Ashwin Sekhar T K
@ 2021-08-30 16:29 ` Ashwin Sekhar T K
2021-08-30 16:29 ` [dpdk-dev] [PATCH 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Ashwin Sekhar T K @ 2021-08-30 16:29 UTC (permalink / raw)
To: dev
Cc: jerinj, skori, skoteshwar, pbhagavatula, kirankumark, psatheesh,
asekhar, ndabilpuram, gakhil
Update roc models.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
drivers/common/cnxk/roc_model.c | 51 +++++++++++++++----------------
drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++--------
2 files changed, 67 insertions(+), 37 deletions(-)
diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index bc255b53cc..e5aeabe2e2 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -13,14 +13,14 @@ struct roc_model *roc_model;
#define SOC_PART_CN10K 0xD49
-#define PART_106XX 0xB9
-#define PART_105XX 0xBA
-#define PART_105XXN 0xBC
-#define PART_98XX 0xB1
-#define PART_96XX 0xB2
-#define PART_95XX 0xB3
-#define PART_95XXN 0xB4
-#define PART_95XXMM 0xB5
+#define PART_106xx 0xB9
+#define PART_105xx 0xBA
+#define PART_105xxN 0xBC
+#define PART_98xx 0xB1
+#define PART_96xx 0xB2
+#define PART_95xx 0xB3
+#define PART_95xxN 0xB4
+#define PART_95xxMM 0xB5
#define PART_95O 0xB6
#define MODEL_IMPL_BITS 8
@@ -44,20 +44,21 @@ static const struct model_db {
uint64_t flag;
char name[ROC_MODEL_STR_LEN_MAX];
} model_db[] = {
- {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"},
- {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"},
- {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"},
- {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
- {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
- {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
- {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
- {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
- {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
- {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"},
- {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"},
- {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0,
- "cnf95xxmm_a0"}
-};
+ {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"},
+ {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"},
+ {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
+ {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
+ {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
+ {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
+ {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
+ {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"},
+ {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
+ {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
+ {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
+ {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
+ {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
+ {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
+ "cnf95xxmm_a0"}};
static uint32_t
cn10k_part_get(void)
@@ -85,11 +86,11 @@ cn10k_part_get(void)
}
ptr++;
if (strcmp("cn10ka", ptr) == 0) {
- soc = PART_106XX;
+ soc = PART_106xx;
} else if (strcmp("cnf10ka", ptr) == 0) {
- soc = PART_105XX;
+ soc = PART_105xx;
} else if (strcmp("cnf10kb", ptr) == 0) {
- soc = PART_105XXN;
+ soc = PART_105xxN;
} else {
plt_err("Unidentified 'CPU compatible': <%s>", ptr);
goto fclose;
diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index c1d11b77c6..a54f435b46 100644
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -15,13 +15,14 @@ struct roc_model {
#define ROC_MODEL_CN96xx_C0 BIT_ULL(2)
#define ROC_MODEL_CNF95xx_A0 BIT_ULL(4)
#define ROC_MODEL_CNF95xx_B0 BIT_ULL(6)
-#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8)
-#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12)
-#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13)
+#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8)
+#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
+#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
+#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)
#define ROC_MODEL_CN98xx_A0 BIT_ULL(16)
-#define ROC_MODEL_CN106XX BIT_ULL(20)
-#define ROC_MODEL_CNF105XX BIT_ULL(21)
-#define ROC_MODEL_CNF105XXN BIT_ULL(22)
+#define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
+#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
+#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)
uint64_t flag;
#define ROC_MODEL_STR_LEN_MAX 128
@@ -31,11 +32,15 @@ struct roc_model {
#define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0)
#define ROC_MODEL_CN9K \
(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \
- ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \
- ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0)
+ ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \
+ ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
+ ROC_MODEL_CNF95xxN_A1)
+#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
+#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)
+#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0)
#define ROC_MODEL_CN10K \
- (ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN)
+ (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
/* Runtime variants */
static inline uint64_t
@@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void)
return (roc_model->flag & ROC_MODEL_CN96xx_Ax);
}
+static inline uint64_t
+roc_model_is_cn96_cx(void)
+{
+ return (roc_model->flag & ROC_MODEL_CN96xx_C0);
+}
+
static inline uint64_t
roc_model_is_cn95_a0(void)
{
@@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void)
static inline uint64_t
roc_model_is_cn10ka(void)
{
- return roc_model->flag & ROC_MODEL_CN106XX;
+ return roc_model->flag & ROC_MODEL_CN106xx;
}
static inline uint64_t
roc_model_is_cnf10ka(void)
{
- return roc_model->flag & ROC_MODEL_CNF105XX;
+ return roc_model->flag & ROC_MODEL_CNF105xx;
}
static inline uint64_t
roc_model_is_cnf10kb(void)
{
- return roc_model->flag & ROC_MODEL_CNF105XXN;
+ return roc_model->flag & ROC_MODEL_CNF105xxN;
+}
+
+static inline uint64_t
+roc_model_is_cn10ka_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CN106xx_A0;
+}
+
+static inline uint64_t
+roc_model_is_cnf10ka_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CNF105xx_A0;
+}
+
+static inline uint64_t
+roc_model_is_cnf10kb_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CNF105xxN_A0;
}
int roc_model_init(struct roc_model *model);
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [dpdk-dev] [PATCH 2/2] common/cnxk: avoid using stashing option of stype
2021-08-30 16:29 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Ashwin Sekhar T K
@ 2021-08-30 16:29 ` Ashwin Sekhar T K
2021-09-16 14:36 ` Jerin Jacob
2021-09-16 14:37 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Jerin Jacob
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 " Ashwin Sekhar T K
2 siblings, 1 reply; 8+ messages in thread
From: Ashwin Sekhar T K @ 2021-08-30 16:29 UTC (permalink / raw)
To: dev
Cc: jerinj, skori, skoteshwar, pbhagavatula, kirankumark, psatheesh,
asekhar, ndabilpuram, gakhil
Avoid using stashing option of stype in NPA in cn10k-a0 stepping.
This is a workaround for a HW Errata due to which NPA stashing operations
will never result in writing the data into L2 cache. But instead, it will
be written into LLC.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
drivers/common/cnxk/roc_nix_queue.c | 4 ++++
drivers/common/cnxk/roc_nix_tm_ops.c | 7 +++++++
drivers/common/cnxk/roc_npa.h | 2 +-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 7e2f86eca7..76e439e7a9 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -585,6 +585,10 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
memset(&aura, 0, sizeof(aura));
aura.fc_ena = 1;
+ if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0())
+ aura.fc_stype = 0x0; /* STF */
+ else
+ aura.fc_stype = 0x3; /* STSTP */
aura.fc_addr = (uint64_t)sq->fc;
aura.fc_hyst_bits = 0; /* Store count on all updates */
rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, NIX_MAX_SQB, &aura,
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index ed244d4214..f2173c9a58 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -38,6 +38,13 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)
req->aura.fc_ena = enable;
req->aura_mask.fc_ena = 1;
+ if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0()) {
+ req->aura.fc_stype = 0x0; /* STF */
+ req->aura_mask.fc_stype = 0x0; /* STF */
+ } else {
+ req->aura.fc_stype = 0x3; /* STSTP */
+ req->aura_mask.fc_stype = 0x3; /* STSTP */
+ }
rc = mbox_process(mbox);
if (rc)
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 3fc6192e57..1cf50e5c4e 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -214,7 +214,7 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf,
cmp.u = 0;
cmp.compare_s.aura = roc_npa_aura_handle_to_aura(aura_handle);
cmp.compare_s.drop = drop;
- cmp.compare_s.stype = ALLOC_STYPE_STSTP;
+ cmp.compare_s.stype = ALLOC_STYPE_STF;
cmp.compare_s.dis_wait = dis_wait;
cmp.compare_s.count = num;
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [dpdk-dev] [PATCH 2/2] common/cnxk: avoid using stashing option of stype
2021-08-30 16:29 ` [dpdk-dev] [PATCH 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
@ 2021-09-16 14:36 ` Jerin Jacob
0 siblings, 0 replies; 8+ messages in thread
From: Jerin Jacob @ 2021-09-16 14:36 UTC (permalink / raw)
To: Ashwin Sekhar T K
Cc: dpdk-dev, Jerin Jacob, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Pavan Nikhilesh, Kiran Kumar K,
Satheesh Paul, Nithin Dabilpuram, Akhil Goyal
On Mon, Aug 30, 2021 at 10:00 PM Ashwin Sekhar T K <asekhar@marvell.com> wrote:
>
> Avoid using stashing option of stype in NPA in cn10k-a0 stepping.
>
> This is a workaround for a HW Errata due to which NPA stashing operations
> will never result in writing the data into L2 cache. But instead, it will
> be written into LLC.
>
> Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
> ---
> drivers/common/cnxk/roc_nix_queue.c | 4 ++++
> drivers/common/cnxk/roc_nix_tm_ops.c | 7 +++++++
> drivers/common/cnxk/roc_npa.h | 2 +-
> 3 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
> index 7e2f86eca7..76e439e7a9 100644
> --- a/drivers/common/cnxk/roc_nix_queue.c
> +++ b/drivers/common/cnxk/roc_nix_queue.c
> @@ -585,6 +585,10 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
>
> memset(&aura, 0, sizeof(aura));
> aura.fc_ena = 1;
> + if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0())
> + aura.fc_stype = 0x0; /* STF */
> + else
> + aura.fc_stype = 0x3; /* STSTP */
> aura.fc_addr = (uint64_t)sq->fc;
> aura.fc_hyst_bits = 0; /* Store count on all updates */
> rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, NIX_MAX_SQB, &aura,
> diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
> index ed244d4214..f2173c9a58 100644
> --- a/drivers/common/cnxk/roc_nix_tm_ops.c
> +++ b/drivers/common/cnxk/roc_nix_tm_ops.c
> @@ -38,6 +38,13 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)
>
> req->aura.fc_ena = enable;
> req->aura_mask.fc_ena = 1;
> + if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0()) {
> + req->aura.fc_stype = 0x0; /* STF */
> + req->aura_mask.fc_stype = 0x0; /* STF */
> + } else {
> + req->aura.fc_stype = 0x3; /* STSTP */
> + req->aura_mask.fc_stype = 0x3; /* STSTP */
> + }
>
> rc = mbox_process(mbox);
> if (rc)
> diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
> index 3fc6192e57..1cf50e5c4e 100644
> --- a/drivers/common/cnxk/roc_npa.h
> +++ b/drivers/common/cnxk/roc_npa.h
> @@ -214,7 +214,7 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf,
> cmp.u = 0;
> cmp.compare_s.aura = roc_npa_aura_handle_to_aura(aura_handle);
> cmp.compare_s.drop = drop;
> - cmp.compare_s.stype = ALLOC_STYPE_STSTP;
> + cmp.compare_s.stype = ALLOC_STYPE_STF;
> cmp.compare_s.dis_wait = dis_wait;
> cmp.compare_s.count = num;
>
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models
2021-08-30 16:29 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Ashwin Sekhar T K
2021-08-30 16:29 ` [dpdk-dev] [PATCH 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
@ 2021-09-16 14:37 ` Jerin Jacob
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 " Ashwin Sekhar T K
2 siblings, 0 replies; 8+ messages in thread
From: Jerin Jacob @ 2021-09-16 14:37 UTC (permalink / raw)
To: Ashwin Sekhar T K
Cc: dpdk-dev, Jerin Jacob, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Pavan Nikhilesh, Kiran Kumar K,
Satheesh Paul, Nithin Dabilpuram, Akhil Goyal
On Mon, Aug 30, 2021 at 10:00 PM Ashwin Sekhar T K <asekhar@marvell.com> wrote:
>
> Update roc models.
Please update git comment for more details on what is updated.
>
> Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
> ---
> drivers/common/cnxk/roc_model.c | 51 +++++++++++++++----------------
> drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++--------
> 2 files changed, 67 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
> index bc255b53cc..e5aeabe2e2 100644
> --- a/drivers/common/cnxk/roc_model.c
> +++ b/drivers/common/cnxk/roc_model.c
> @@ -13,14 +13,14 @@ struct roc_model *roc_model;
>
> #define SOC_PART_CN10K 0xD49
>
> -#define PART_106XX 0xB9
> -#define PART_105XX 0xBA
> -#define PART_105XXN 0xBC
> -#define PART_98XX 0xB1
> -#define PART_96XX 0xB2
> -#define PART_95XX 0xB3
> -#define PART_95XXN 0xB4
> -#define PART_95XXMM 0xB5
> +#define PART_106xx 0xB9
> +#define PART_105xx 0xBA
> +#define PART_105xxN 0xBC
> +#define PART_98xx 0xB1
> +#define PART_96xx 0xB2
> +#define PART_95xx 0xB3
> +#define PART_95xxN 0xB4
> +#define PART_95xxMM 0xB5
> #define PART_95O 0xB6
>
> #define MODEL_IMPL_BITS 8
> @@ -44,20 +44,21 @@ static const struct model_db {
> uint64_t flag;
> char name[ROC_MODEL_STR_LEN_MAX];
> } model_db[] = {
> - {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"},
> - {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"},
> - {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"},
> - {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
> - {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
> - {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
> - {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
> - {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
> - {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
> - {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"},
> - {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"},
> - {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0,
> - "cnf95xxmm_a0"}
> -};
> + {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"},
> + {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"},
> + {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
> + {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
> + {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
> + {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
> + {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
> + {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"},
> + {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
> + {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
> + {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
> + {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
> + {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
> + {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
> + "cnf95xxmm_a0"}};
>
> static uint32_t
> cn10k_part_get(void)
> @@ -85,11 +86,11 @@ cn10k_part_get(void)
> }
> ptr++;
> if (strcmp("cn10ka", ptr) == 0) {
> - soc = PART_106XX;
> + soc = PART_106xx;
> } else if (strcmp("cnf10ka", ptr) == 0) {
> - soc = PART_105XX;
> + soc = PART_105xx;
> } else if (strcmp("cnf10kb", ptr) == 0) {
> - soc = PART_105XXN;
> + soc = PART_105xxN;
> } else {
> plt_err("Unidentified 'CPU compatible': <%s>", ptr);
> goto fclose;
> diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
> index c1d11b77c6..a54f435b46 100644
> --- a/drivers/common/cnxk/roc_model.h
> +++ b/drivers/common/cnxk/roc_model.h
> @@ -15,13 +15,14 @@ struct roc_model {
> #define ROC_MODEL_CN96xx_C0 BIT_ULL(2)
> #define ROC_MODEL_CNF95xx_A0 BIT_ULL(4)
> #define ROC_MODEL_CNF95xx_B0 BIT_ULL(6)
> -#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8)
> -#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12)
> -#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13)
> +#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8)
> +#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
> +#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
> +#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)
> #define ROC_MODEL_CN98xx_A0 BIT_ULL(16)
> -#define ROC_MODEL_CN106XX BIT_ULL(20)
> -#define ROC_MODEL_CNF105XX BIT_ULL(21)
> -#define ROC_MODEL_CNF105XXN BIT_ULL(22)
> +#define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
> +#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
> +#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)
>
> uint64_t flag;
> #define ROC_MODEL_STR_LEN_MAX 128
> @@ -31,11 +32,15 @@ struct roc_model {
> #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0)
> #define ROC_MODEL_CN9K \
> (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \
> - ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \
> - ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0)
> + ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \
> + ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
> + ROC_MODEL_CNF95xxN_A1)
>
> +#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
> +#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)
> +#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0)
> #define ROC_MODEL_CN10K \
> - (ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN)
> + (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
>
> /* Runtime variants */
> static inline uint64_t
> @@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void)
> return (roc_model->flag & ROC_MODEL_CN96xx_Ax);
> }
>
> +static inline uint64_t
> +roc_model_is_cn96_cx(void)
> +{
> + return (roc_model->flag & ROC_MODEL_CN96xx_C0);
> +}
> +
> static inline uint64_t
> roc_model_is_cn95_a0(void)
> {
> @@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void)
> static inline uint64_t
> roc_model_is_cn10ka(void)
> {
> - return roc_model->flag & ROC_MODEL_CN106XX;
> + return roc_model->flag & ROC_MODEL_CN106xx;
> }
>
> static inline uint64_t
> roc_model_is_cnf10ka(void)
> {
> - return roc_model->flag & ROC_MODEL_CNF105XX;
> + return roc_model->flag & ROC_MODEL_CNF105xx;
> }
>
> static inline uint64_t
> roc_model_is_cnf10kb(void)
> {
> - return roc_model->flag & ROC_MODEL_CNF105XXN;
> + return roc_model->flag & ROC_MODEL_CNF105xxN;
> +}
> +
> +static inline uint64_t
> +roc_model_is_cn10ka_a0(void)
> +{
> + return roc_model->flag & ROC_MODEL_CN106xx_A0;
> +}
> +
> +static inline uint64_t
> +roc_model_is_cnf10ka_a0(void)
> +{
> + return roc_model->flag & ROC_MODEL_CNF105xx_A0;
> +}
> +
> +static inline uint64_t
> +roc_model_is_cnf10kb_a0(void)
> +{
> + return roc_model->flag & ROC_MODEL_CNF105xxN_A0;
> }
>
> int roc_model_init(struct roc_model *model);
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models
2021-08-30 16:29 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Ashwin Sekhar T K
2021-08-30 16:29 ` [dpdk-dev] [PATCH 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
2021-09-16 14:37 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Jerin Jacob
@ 2021-09-17 9:34 ` Ashwin Sekhar T K
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
2021-09-20 8:51 ` [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models Jerin Jacob
2 siblings, 2 replies; 8+ messages in thread
From: Ashwin Sekhar T K @ 2021-09-17 9:34 UTC (permalink / raw)
To: dev
Cc: jerinj, skori, skoteshwar, pbhagavatula, kirankumark, psatheesh,
asekhar, anoobj, gakhil
Make following updates to roc models.
- Use consistent upper/lower case in macros defining different
ROC models.
- Add api to detect cn96 Cx stepping.
- Make all current cn10k models as A0 stepping.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
drivers/common/cnxk/roc_model.c | 51 +++++++++++++++----------------
drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++--------
2 files changed, 67 insertions(+), 37 deletions(-)
diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index bc255b53cc..e5aeabe2e2 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -13,14 +13,14 @@ struct roc_model *roc_model;
#define SOC_PART_CN10K 0xD49
-#define PART_106XX 0xB9
-#define PART_105XX 0xBA
-#define PART_105XXN 0xBC
-#define PART_98XX 0xB1
-#define PART_96XX 0xB2
-#define PART_95XX 0xB3
-#define PART_95XXN 0xB4
-#define PART_95XXMM 0xB5
+#define PART_106xx 0xB9
+#define PART_105xx 0xBA
+#define PART_105xxN 0xBC
+#define PART_98xx 0xB1
+#define PART_96xx 0xB2
+#define PART_95xx 0xB3
+#define PART_95xxN 0xB4
+#define PART_95xxMM 0xB5
#define PART_95O 0xB6
#define MODEL_IMPL_BITS 8
@@ -44,20 +44,21 @@ static const struct model_db {
uint64_t flag;
char name[ROC_MODEL_STR_LEN_MAX];
} model_db[] = {
- {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"},
- {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"},
- {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"},
- {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
- {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
- {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
- {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
- {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
- {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
- {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"},
- {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"},
- {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0,
- "cnf95xxmm_a0"}
-};
+ {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"},
+ {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"},
+ {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
+ {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
+ {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
+ {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
+ {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
+ {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"},
+ {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
+ {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
+ {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
+ {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
+ {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
+ {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
+ "cnf95xxmm_a0"}};
static uint32_t
cn10k_part_get(void)
@@ -85,11 +86,11 @@ cn10k_part_get(void)
}
ptr++;
if (strcmp("cn10ka", ptr) == 0) {
- soc = PART_106XX;
+ soc = PART_106xx;
} else if (strcmp("cnf10ka", ptr) == 0) {
- soc = PART_105XX;
+ soc = PART_105xx;
} else if (strcmp("cnf10kb", ptr) == 0) {
- soc = PART_105XXN;
+ soc = PART_105xxN;
} else {
plt_err("Unidentified 'CPU compatible': <%s>", ptr);
goto fclose;
diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index c1d11b77c6..a54f435b46 100644
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -15,13 +15,14 @@ struct roc_model {
#define ROC_MODEL_CN96xx_C0 BIT_ULL(2)
#define ROC_MODEL_CNF95xx_A0 BIT_ULL(4)
#define ROC_MODEL_CNF95xx_B0 BIT_ULL(6)
-#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8)
-#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12)
-#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13)
+#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8)
+#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
+#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
+#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)
#define ROC_MODEL_CN98xx_A0 BIT_ULL(16)
-#define ROC_MODEL_CN106XX BIT_ULL(20)
-#define ROC_MODEL_CNF105XX BIT_ULL(21)
-#define ROC_MODEL_CNF105XXN BIT_ULL(22)
+#define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
+#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
+#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)
uint64_t flag;
#define ROC_MODEL_STR_LEN_MAX 128
@@ -31,11 +32,15 @@ struct roc_model {
#define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0)
#define ROC_MODEL_CN9K \
(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \
- ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \
- ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0)
+ ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \
+ ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
+ ROC_MODEL_CNF95xxN_A1)
+#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
+#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)
+#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0)
#define ROC_MODEL_CN10K \
- (ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN)
+ (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
/* Runtime variants */
static inline uint64_t
@@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void)
return (roc_model->flag & ROC_MODEL_CN96xx_Ax);
}
+static inline uint64_t
+roc_model_is_cn96_cx(void)
+{
+ return (roc_model->flag & ROC_MODEL_CN96xx_C0);
+}
+
static inline uint64_t
roc_model_is_cn95_a0(void)
{
@@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void)
static inline uint64_t
roc_model_is_cn10ka(void)
{
- return roc_model->flag & ROC_MODEL_CN106XX;
+ return roc_model->flag & ROC_MODEL_CN106xx;
}
static inline uint64_t
roc_model_is_cnf10ka(void)
{
- return roc_model->flag & ROC_MODEL_CNF105XX;
+ return roc_model->flag & ROC_MODEL_CNF105xx;
}
static inline uint64_t
roc_model_is_cnf10kb(void)
{
- return roc_model->flag & ROC_MODEL_CNF105XXN;
+ return roc_model->flag & ROC_MODEL_CNF105xxN;
+}
+
+static inline uint64_t
+roc_model_is_cn10ka_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CN106xx_A0;
+}
+
+static inline uint64_t
+roc_model_is_cnf10ka_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CNF105xx_A0;
+}
+
+static inline uint64_t
+roc_model_is_cnf10kb_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CNF105xxN_A0;
}
int roc_model_init(struct roc_model *model);
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [dpdk-dev] [PATCH v2 2/2] common/cnxk: avoid using stashing option of stype
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 " Ashwin Sekhar T K
@ 2021-09-17 9:34 ` Ashwin Sekhar T K
2021-09-20 8:51 ` [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models Jerin Jacob
1 sibling, 0 replies; 8+ messages in thread
From: Ashwin Sekhar T K @ 2021-09-17 9:34 UTC (permalink / raw)
To: dev
Cc: jerinj, skori, skoteshwar, pbhagavatula, kirankumark, psatheesh,
asekhar, anoobj, gakhil
Avoid using stashing option of stype in NPA in cn10k-a0 stepping.
This is a workaround for a HW Errata due to which NPA stashing operations
will never result in writing the data into L2 cache. But instead, it will
be written into LLC.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
---
drivers/common/cnxk/roc_nix_queue.c | 4 ++++
drivers/common/cnxk/roc_nix_tm_ops.c | 7 +++++++
drivers/common/cnxk/roc_npa.h | 2 +-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 7e2f86eca7..76e439e7a9 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -585,6 +585,10 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
memset(&aura, 0, sizeof(aura));
aura.fc_ena = 1;
+ if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0())
+ aura.fc_stype = 0x0; /* STF */
+ else
+ aura.fc_stype = 0x3; /* STSTP */
aura.fc_addr = (uint64_t)sq->fc;
aura.fc_hyst_bits = 0; /* Store count on all updates */
rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, NIX_MAX_SQB, &aura,
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index ed244d4214..f2173c9a58 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -38,6 +38,13 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)
req->aura.fc_ena = enable;
req->aura_mask.fc_ena = 1;
+ if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0()) {
+ req->aura.fc_stype = 0x0; /* STF */
+ req->aura_mask.fc_stype = 0x0; /* STF */
+ } else {
+ req->aura.fc_stype = 0x3; /* STSTP */
+ req->aura_mask.fc_stype = 0x3; /* STSTP */
+ }
rc = mbox_process(mbox);
if (rc)
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 3fc6192e57..1cf50e5c4e 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -214,7 +214,7 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf,
cmp.u = 0;
cmp.compare_s.aura = roc_npa_aura_handle_to_aura(aura_handle);
cmp.compare_s.drop = drop;
- cmp.compare_s.stype = ALLOC_STYPE_STSTP;
+ cmp.compare_s.stype = ALLOC_STYPE_STF;
cmp.compare_s.dis_wait = dis_wait;
cmp.compare_s.count = num;
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 " Ashwin Sekhar T K
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
@ 2021-09-20 8:51 ` Jerin Jacob
1 sibling, 0 replies; 8+ messages in thread
From: Jerin Jacob @ 2021-09-20 8:51 UTC (permalink / raw)
To: Ashwin Sekhar T K, Ferruh Yigit
Cc: dpdk-dev, Jerin Jacob, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Pavan Nikhilesh, Kiran Kumar K,
Satheesh Paul, Anoob Joseph, Akhil Goyal
On Fri, Sep 17, 2021 at 3:06 PM Ashwin Sekhar T K <asekhar@marvell.com> wrote:
>
> Make following updates to roc models.
> - Use consistent upper/lower case in macros defining different
> ROC models.
> - Add api to detect cn96 Cx stepping.
> - Make all current cn10k models as A0 stepping.
>
> Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Series Acked-by: Jerin Jacob <jerinj@marvell.com>
Series applied to dpdk-next-net-mrvl/for-next-net. Thanks.
> ---
> drivers/common/cnxk/roc_model.c | 51 +++++++++++++++----------------
> drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++--------
> 2 files changed, 67 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
> index bc255b53cc..e5aeabe2e2 100644
> --- a/drivers/common/cnxk/roc_model.c
> +++ b/drivers/common/cnxk/roc_model.c
> @@ -13,14 +13,14 @@ struct roc_model *roc_model;
>
> #define SOC_PART_CN10K 0xD49
>
> -#define PART_106XX 0xB9
> -#define PART_105XX 0xBA
> -#define PART_105XXN 0xBC
> -#define PART_98XX 0xB1
> -#define PART_96XX 0xB2
> -#define PART_95XX 0xB3
> -#define PART_95XXN 0xB4
> -#define PART_95XXMM 0xB5
> +#define PART_106xx 0xB9
> +#define PART_105xx 0xBA
> +#define PART_105xxN 0xBC
> +#define PART_98xx 0xB1
> +#define PART_96xx 0xB2
> +#define PART_95xx 0xB3
> +#define PART_95xxN 0xB4
> +#define PART_95xxMM 0xB5
> #define PART_95O 0xB6
>
> #define MODEL_IMPL_BITS 8
> @@ -44,20 +44,21 @@ static const struct model_db {
> uint64_t flag;
> char name[ROC_MODEL_STR_LEN_MAX];
> } model_db[] = {
> - {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"},
> - {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"},
> - {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"},
> - {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
> - {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
> - {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
> - {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
> - {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
> - {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
> - {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"},
> - {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"},
> - {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0,
> - "cnf95xxmm_a0"}
> -};
> + {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"},
> + {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"},
> + {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
> + {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
> + {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
> + {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
> + {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
> + {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"},
> + {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
> + {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
> + {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
> + {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
> + {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
> + {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
> + "cnf95xxmm_a0"}};
>
> static uint32_t
> cn10k_part_get(void)
> @@ -85,11 +86,11 @@ cn10k_part_get(void)
> }
> ptr++;
> if (strcmp("cn10ka", ptr) == 0) {
> - soc = PART_106XX;
> + soc = PART_106xx;
> } else if (strcmp("cnf10ka", ptr) == 0) {
> - soc = PART_105XX;
> + soc = PART_105xx;
> } else if (strcmp("cnf10kb", ptr) == 0) {
> - soc = PART_105XXN;
> + soc = PART_105xxN;
> } else {
> plt_err("Unidentified 'CPU compatible': <%s>", ptr);
> goto fclose;
> diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
> index c1d11b77c6..a54f435b46 100644
> --- a/drivers/common/cnxk/roc_model.h
> +++ b/drivers/common/cnxk/roc_model.h
> @@ -15,13 +15,14 @@ struct roc_model {
> #define ROC_MODEL_CN96xx_C0 BIT_ULL(2)
> #define ROC_MODEL_CNF95xx_A0 BIT_ULL(4)
> #define ROC_MODEL_CNF95xx_B0 BIT_ULL(6)
> -#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8)
> -#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12)
> -#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13)
> +#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8)
> +#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
> +#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
> +#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)
> #define ROC_MODEL_CN98xx_A0 BIT_ULL(16)
> -#define ROC_MODEL_CN106XX BIT_ULL(20)
> -#define ROC_MODEL_CNF105XX BIT_ULL(21)
> -#define ROC_MODEL_CNF105XXN BIT_ULL(22)
> +#define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
> +#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
> +#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)
>
> uint64_t flag;
> #define ROC_MODEL_STR_LEN_MAX 128
> @@ -31,11 +32,15 @@ struct roc_model {
> #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0)
> #define ROC_MODEL_CN9K \
> (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \
> - ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \
> - ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0)
> + ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \
> + ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
> + ROC_MODEL_CNF95xxN_A1)
>
> +#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
> +#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)
> +#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0)
> #define ROC_MODEL_CN10K \
> - (ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN)
> + (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
>
> /* Runtime variants */
> static inline uint64_t
> @@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void)
> return (roc_model->flag & ROC_MODEL_CN96xx_Ax);
> }
>
> +static inline uint64_t
> +roc_model_is_cn96_cx(void)
> +{
> + return (roc_model->flag & ROC_MODEL_CN96xx_C0);
> +}
> +
> static inline uint64_t
> roc_model_is_cn95_a0(void)
> {
> @@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void)
> static inline uint64_t
> roc_model_is_cn10ka(void)
> {
> - return roc_model->flag & ROC_MODEL_CN106XX;
> + return roc_model->flag & ROC_MODEL_CN106xx;
> }
>
> static inline uint64_t
> roc_model_is_cnf10ka(void)
> {
> - return roc_model->flag & ROC_MODEL_CNF105XX;
> + return roc_model->flag & ROC_MODEL_CNF105xx;
> }
>
> static inline uint64_t
> roc_model_is_cnf10kb(void)
> {
> - return roc_model->flag & ROC_MODEL_CNF105XXN;
> + return roc_model->flag & ROC_MODEL_CNF105xxN;
> +}
> +
> +static inline uint64_t
> +roc_model_is_cn10ka_a0(void)
> +{
> + return roc_model->flag & ROC_MODEL_CN106xx_A0;
> +}
> +
> +static inline uint64_t
> +roc_model_is_cnf10ka_a0(void)
> +{
> + return roc_model->flag & ROC_MODEL_CNF105xx_A0;
> +}
> +
> +static inline uint64_t
> +roc_model_is_cnf10kb_a0(void)
> +{
> + return roc_model->flag & ROC_MODEL_CNF105xxN_A0;
> }
>
> int roc_model_init(struct roc_model *model);
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-09-20 8:52 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-30 14:08 [dpdk-dev] [PATCH] common/cnxk: avoid using stype STSTP in batch alloc Ashwin Sekhar T K
2021-08-30 16:29 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Ashwin Sekhar T K
2021-08-30 16:29 ` [dpdk-dev] [PATCH 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
2021-09-16 14:36 ` Jerin Jacob
2021-09-16 14:37 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Jerin Jacob
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 " Ashwin Sekhar T K
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
2021-09-20 8:51 ` [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models Jerin Jacob
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