From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 59FDEA0548; Mon, 20 Sep 2021 10:52:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 44B8140E5A; Mon, 20 Sep 2021 10:52:02 +0200 (CEST) Received: from mail-il1-f176.google.com (mail-il1-f176.google.com [209.85.166.176]) by mails.dpdk.org (Postfix) with ESMTP id 49EDB40DF5 for ; Mon, 20 Sep 2021 10:52:01 +0200 (CEST) Received: by mail-il1-f176.google.com with SMTP id v16so17830682ilg.3 for ; Mon, 20 Sep 2021 01:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=WE0Be8/hYvH4mRj4+3yXmRw6odhhAHcRKW6GrpAjF+w=; b=fjRLSPT087bueYhB/eMfV4m4cz7Ywz/0IhiXZ4eEek4SyfWDe024MN97wjaPHWjIIc PLu3kQek2HynwjbzOmRqrj1klP7D7gfQ84HGE4cw51dhzEIc5YwIma5JpOmT0JhWAZlK TrGK0tJ+MFHT1Z+65EhU6yssI5w+2r5YDROscdVhWuVOn9i585ljdWEvvztPWwhPX4Oa RQIBNBK1zmp4LD1iRYr79rPiXLcVz7F7CuPfWfRiaxyp587+2m97CdC0AFhAOP1KQNkY v9a3xhpZtpAw44DWZQLZZm603inoghczePIITuVUINW9Do5JzDyXL7Ah4Xmn3azipT9W pIgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WE0Be8/hYvH4mRj4+3yXmRw6odhhAHcRKW6GrpAjF+w=; b=yP2W3VhsiI1jOhkHo0MlSFawUwKfMss6iVvYuLj+aog3hVLdBj2zvZSPFKmLsW95+K C+9RI/tlYLZWsfWZ2Th3azuvE1/CNO3sD3iVzBovTftiWrQ8YURMIavyW7z9A4k/R0VA IsQMDQFPZOXk30JoFfemzDzUwOjmcLLPiS02bf+X9vG7GFoJtow6hCILIYUO1UnoNjaH s1AC5T9ZV4eXbtiqTFX2NmH+3hlZua/Y7mK9bf+6ryfZjH1lArqjuIgwxixOiHSnM2cX zeeCA7aSrnNLHPZan+QYHRigXMchlhQ2Rfp0NaMskYbd6QiE0GyWJ1XGQRCZtppwKMR2 aGYQ== X-Gm-Message-State: AOAM530MaVKCntOzVEXkLyP2m4jTzGmWhC28BENiOAK49r5RRvJbYxIZ zcdYuQ+ORg9G+DUHVAyh1H9HZXp8OM/xzZL8ocjI4W2b0gGRvQ== X-Google-Smtp-Source: ABdhPJyKjwUBmni/6ABNfdzKQQwYrLePAEPSmWZMtPov9HXo+jUstMmt9qoLRzwOB5zvg1rv/hMPC8QsJPvC3Xw52TI= X-Received: by 2002:a92:c548:: with SMTP id a8mr9226318ilj.295.1632127920532; Mon, 20 Sep 2021 01:52:00 -0700 (PDT) MIME-Version: 1.0 References: <20210830162903.2736191-1-asekhar@marvell.com> <20210917093437.269363-1-asekhar@marvell.com> In-Reply-To: <20210917093437.269363-1-asekhar@marvell.com> From: Jerin Jacob Date: Mon, 20 Sep 2021 14:21:34 +0530 Message-ID: To: Ashwin Sekhar T K , Ferruh Yigit Cc: dpdk-dev , Jerin Jacob , Sunil Kumar Kori , Satha Koteswara Rao Kottidi , Pavan Nikhilesh , Kiran Kumar K , Satheesh Paul , Anoob Joseph , Akhil Goyal Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Sep 17, 2021 at 3:06 PM Ashwin Sekhar T K wrote: > > Make following updates to roc models. > - Use consistent upper/lower case in macros defining different > ROC models. > - Add api to detect cn96 Cx stepping. > - Make all current cn10k models as A0 stepping. > > Signed-off-by: Ashwin Sekhar T K Series Acked-by: Jerin Jacob Series applied to dpdk-next-net-mrvl/for-next-net. Thanks. > --- > drivers/common/cnxk/roc_model.c | 51 +++++++++++++++---------------- > drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++-------- > 2 files changed, 67 insertions(+), 37 deletions(-) > > diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c > index bc255b53cc..e5aeabe2e2 100644 > --- a/drivers/common/cnxk/roc_model.c > +++ b/drivers/common/cnxk/roc_model.c > @@ -13,14 +13,14 @@ struct roc_model *roc_model; > > #define SOC_PART_CN10K 0xD49 > > -#define PART_106XX 0xB9 > -#define PART_105XX 0xBA > -#define PART_105XXN 0xBC > -#define PART_98XX 0xB1 > -#define PART_96XX 0xB2 > -#define PART_95XX 0xB3 > -#define PART_95XXN 0xB4 > -#define PART_95XXMM 0xB5 > +#define PART_106xx 0xB9 > +#define PART_105xx 0xBA > +#define PART_105xxN 0xBC > +#define PART_98xx 0xB1 > +#define PART_96xx 0xB2 > +#define PART_95xx 0xB3 > +#define PART_95xxN 0xB4 > +#define PART_95xxMM 0xB5 > #define PART_95O 0xB6 > > #define MODEL_IMPL_BITS 8 > @@ -44,20 +44,21 @@ static const struct model_db { > uint64_t flag; > char name[ROC_MODEL_STR_LEN_MAX]; > } model_db[] = { > - {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"}, > - {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"}, > - {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"}, > - {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, > - {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, > - {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"}, > - {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"}, > - {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"}, > - {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"}, > - {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"}, > - {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"}, > - {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0, > - "cnf95xxmm_a0"} > -}; > + {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"}, > + {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"}, > + {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"}, > + {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, > + {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, > + {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"}, > + {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"}, > + {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"}, > + {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"}, > + {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"}, > + {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"}, > + {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"}, > + {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"}, > + {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0, > + "cnf95xxmm_a0"}}; > > static uint32_t > cn10k_part_get(void) > @@ -85,11 +86,11 @@ cn10k_part_get(void) > } > ptr++; > if (strcmp("cn10ka", ptr) == 0) { > - soc = PART_106XX; > + soc = PART_106xx; > } else if (strcmp("cnf10ka", ptr) == 0) { > - soc = PART_105XX; > + soc = PART_105xx; > } else if (strcmp("cnf10kb", ptr) == 0) { > - soc = PART_105XXN; > + soc = PART_105xxN; > } else { > plt_err("Unidentified 'CPU compatible': <%s>", ptr); > goto fclose; > diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h > index c1d11b77c6..a54f435b46 100644 > --- a/drivers/common/cnxk/roc_model.h > +++ b/drivers/common/cnxk/roc_model.h > @@ -15,13 +15,14 @@ struct roc_model { > #define ROC_MODEL_CN96xx_C0 BIT_ULL(2) > #define ROC_MODEL_CNF95xx_A0 BIT_ULL(4) > #define ROC_MODEL_CNF95xx_B0 BIT_ULL(6) > -#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8) > -#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12) > -#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13) > +#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8) > +#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12) > +#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13) > +#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14) > #define ROC_MODEL_CN98xx_A0 BIT_ULL(16) > -#define ROC_MODEL_CN106XX BIT_ULL(20) > -#define ROC_MODEL_CNF105XX BIT_ULL(21) > -#define ROC_MODEL_CNF105XXN BIT_ULL(22) > +#define ROC_MODEL_CN106xx_A0 BIT_ULL(20) > +#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) > +#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22) > > uint64_t flag; > #define ROC_MODEL_STR_LEN_MAX 128 > @@ -31,11 +32,15 @@ struct roc_model { > #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0) > #define ROC_MODEL_CN9K \ > (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \ > - ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \ > - ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0) > + ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \ > + ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \ > + ROC_MODEL_CNF95xxN_A1) > > +#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0) > +#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0) > +#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0) > #define ROC_MODEL_CN10K \ > - (ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN) > + (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN) > > /* Runtime variants */ > static inline uint64_t > @@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void) > return (roc_model->flag & ROC_MODEL_CN96xx_Ax); > } > > +static inline uint64_t > +roc_model_is_cn96_cx(void) > +{ > + return (roc_model->flag & ROC_MODEL_CN96xx_C0); > +} > + > static inline uint64_t > roc_model_is_cn95_a0(void) > { > @@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void) > static inline uint64_t > roc_model_is_cn10ka(void) > { > - return roc_model->flag & ROC_MODEL_CN106XX; > + return roc_model->flag & ROC_MODEL_CN106xx; > } > > static inline uint64_t > roc_model_is_cnf10ka(void) > { > - return roc_model->flag & ROC_MODEL_CNF105XX; > + return roc_model->flag & ROC_MODEL_CNF105xx; > } > > static inline uint64_t > roc_model_is_cnf10kb(void) > { > - return roc_model->flag & ROC_MODEL_CNF105XXN; > + return roc_model->flag & ROC_MODEL_CNF105xxN; > +} > + > +static inline uint64_t > +roc_model_is_cn10ka_a0(void) > +{ > + return roc_model->flag & ROC_MODEL_CN106xx_A0; > +} > + > +static inline uint64_t > +roc_model_is_cnf10ka_a0(void) > +{ > + return roc_model->flag & ROC_MODEL_CNF105xx_A0; > +} > + > +static inline uint64_t > +roc_model_is_cnf10kb_a0(void) > +{ > + return roc_model->flag & ROC_MODEL_CNF105xxN_A0; > } > > int roc_model_init(struct roc_model *model); > -- > 2.32.0 >