From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B331DA034E; Fri, 21 Jan 2022 11:18:56 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 41E544273E; Fri, 21 Jan 2022 11:18:56 +0100 (CET) Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) by mails.dpdk.org (Postfix) with ESMTP id DD27E40042 for ; Fri, 21 Jan 2022 11:18:54 +0100 (CET) Received: by mail-io1-f53.google.com with SMTP id p7so10257666iod.2 for ; Fri, 21 Jan 2022 02:18:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=umcL1xuh75xa7w8N1x2kX6C3LK7APH53OcknZ1IaVsc=; b=GSsTS37ttjN4dxaHzYu8fgjSY9egXI6m8SDt29yOPhsXcSeCCaDP9qjkQZQ65XY95u GsTeff6n0VsXxiz+LWPz17pFF07jd5ipesQOVRtNQUwC3UNj503tR5YlhtoJO7kSBa+c MSMm250/C7TbvdcIx5jmZSAHyNxLWG5Qv7a4Q2y/MNpEBuWV2hWPrc0yTCeQYvvkYeL/ dQSQUrY+GkPi/ep9n3KvxMdzfOdoGxTYlB9mgHe9wWUsEsbxvuNLthDLtm+MbR5CWiDn igSyFt3xRAXs/JxV4kOmczS2UM1AG+BHgMKRapTJezERmM4UjOgz67hceccfF9fTTdru IGCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=umcL1xuh75xa7w8N1x2kX6C3LK7APH53OcknZ1IaVsc=; b=7cYQT+HZzaAmpt0xxcFniVq1D91UPW8Yyl2MTj0j4LZYomjI/MXttSaHyny6s9SKna vpQDzj1fG527trUfUrwoDpOoxdA/TJNh5gJwFu65D6sVoegTW7rSE14Ee8QgctSmqVed nCdo+iqbXb2XGp3gOaLzZqgwWUpwgqr3pY0oamMdyRTSDqjfP6b0yjmK0PjDgkkKycmL 5DqPcMjlAviytlRDXpo7+oaoQdrizDV2SdkIY/i6S0DOxXNC2vJXoQUG58pVuLuCQkUC 4ze6CvQq0ATYDxxV6K35DB50i+MSjtx2P8QI+KLpidByoEjmWMHFsx9pYwACMmKmaCXj XxYQ== X-Gm-Message-State: AOAM532PIFsxJ1S0Qnc8vaHAB2iLWfb0RzsgLvdSXKB0vLL+1wC+3dmj VHXi/ueHeE0aBt4ywOEO9rIVMj2TdU17O8P8govOj9XrVlo= X-Google-Smtp-Source: ABdhPJw3q01HhnLnlU11bUeV4+ABEB2XwiFmxNa00R5HytJUvHhr5ePGHOqsMfyLe2ZUGrrbXXaimtHumoXIhCRaUEQ= X-Received: by 2002:a02:9f05:: with SMTP id z5mr1346619jal.280.1642760334167; Fri, 21 Jan 2022 02:18:54 -0800 (PST) MIME-Version: 1.0 References: <20211009080426.18482-1-pbhagavatula@marvell.com> <20211213111345.5046-1-pbhagavatula@marvell.com> In-Reply-To: <20211213111345.5046-1-pbhagavatula@marvell.com> From: Jerin Jacob Date: Fri, 21 Jan 2022 15:48:28 +0530 Message-ID: Subject: Re: [PATCH v5 1/2] event/cnxk: update min interval calculation To: Pavan Nikhilesh Cc: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Shijith Thotton , dpdk-dev Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Mon, Dec 13, 2021 at 4:44 PM wrote: > > From: Pavan Nikhilesh > > Minimum supported interval should now be retrieved from > mailbox based on the clock source and clock frequency. > > Signed-off-by: Pavan Nikhilesh > --- > v5: > - Rebase on master. Applied to dpdk-next-net-eventdev/for-main. Thanks > v4: > - Rebase on master, fix NULL checks. > v3: > - Add new mbox interface. > v2: > - Fixed devargs parsing and rebased. > > drivers/common/cnxk/roc_tim.c | 32 +++++++++++- > drivers/common/cnxk/roc_tim.h | 9 +++- > drivers/common/cnxk/version.map | 1 + > drivers/event/cnxk/cnxk_tim_evdev.c | 69 +++++++++++++++++------- > drivers/event/cnxk/cnxk_tim_evdev.h | 81 +++++++++++++++++------------ > 5 files changed, 138 insertions(+), 54 deletions(-) > > diff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c > index 534b697bee..cefd9bc89d 100644 > --- a/drivers/common/cnxk/roc_tim.c > +++ b/drivers/common/cnxk/roc_tim.c > @@ -145,7 +145,7 @@ int > roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, > enum roc_tim_clk_src clk_src, uint8_t ena_periodic, > uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz, > - uint32_t interval) > + uint32_t interval, uint64_t intervalns, uint64_t clockfreq) > { > struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev; > struct tim_config_req *req; > @@ -162,6 +162,8 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, > req->enableperiodic = ena_periodic; > req->enabledontfreebuffer = ena_dfb; > req->interval = interval; > + req->intervalns = intervalns; > + req->clockfreq = clockfreq; > req->gpioedge = TIM_GPIO_LTOH_TRANS; > > rc = mbox_process(dev->mbox); > @@ -173,6 +175,34 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, > return 0; > } > > +int > +roc_tim_lf_interval(struct roc_tim *roc_tim, enum roc_tim_clk_src clk_src, > + uint64_t clockfreq, uint64_t *intervalns, > + uint64_t *interval) > +{ > + struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev; > + struct tim_intvl_req *req; > + struct tim_intvl_rsp *rsp; > + int rc = -ENOSPC; > + > + req = mbox_alloc_msg_tim_get_min_intvl(dev->mbox); > + if (req == NULL) > + return rc; > + > + req->clockfreq = clockfreq; > + req->clocksource = clk_src; > + rc = mbox_process_msg(dev->mbox, (void **)&rsp); > + if (rc < 0) { > + tim_err_desc(rc); > + return rc; > + } > + > + *intervalns = rsp->intvl_ns; > + *interval = rsp->intvl_cyc; > + > + return 0; > +} > + > int > roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk) > { > diff --git a/drivers/common/cnxk/roc_tim.h b/drivers/common/cnxk/roc_tim.h > index 159b021a31..392732eae2 100644 > --- a/drivers/common/cnxk/roc_tim.h > +++ b/drivers/common/cnxk/roc_tim.h > @@ -10,6 +10,8 @@ enum roc_tim_clk_src { > ROC_TIM_CLK_SRC_GPIO, > ROC_TIM_CLK_SRC_GTI, > ROC_TIM_CLK_SRC_PTP, > + ROC_TIM_CLK_SRC_SYNCE, > + ROC_TIM_CLK_SRC_BTS, > ROC_TIM_CLK_SRC_INVALID, > }; > > @@ -33,7 +35,12 @@ int __roc_api roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, > enum roc_tim_clk_src clk_src, > uint8_t ena_periodic, uint8_t ena_dfb, > uint32_t bucket_sz, uint32_t chunk_sz, > - uint32_t interval); > + uint32_t interval, uint64_t intervalns, > + uint64_t clockfreq); > +int __roc_api roc_tim_lf_interval(struct roc_tim *roc_tim, > + enum roc_tim_clk_src clk_src, > + uint64_t clockfreq, uint64_t *intervalns, > + uint64_t *interval); > int __roc_api roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, > uint64_t *clk); > int __roc_api roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id); > diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map > index 07c6720f0c..5379ed2d39 100644 > --- a/drivers/common/cnxk/version.map > +++ b/drivers/common/cnxk/version.map > @@ -346,6 +346,7 @@ INTERNAL { > roc_tim_lf_disable; > roc_tim_lf_enable; > roc_tim_lf_free; > + roc_tim_lf_interval; > roc_se_ctx_swap; > > local: *; > diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c > index 99b3acee7c..becab1d1b1 100644 > --- a/drivers/event/cnxk/cnxk_tim_evdev.c > +++ b/drivers/event/cnxk/cnxk_tim_evdev.c > @@ -2,6 +2,8 @@ > * Copyright(C) 2021 Marvell. > */ > > +#include > + > #include "cnxk_eventdev.h" > #include "cnxk_tim_evdev.h" > > @@ -120,7 +122,10 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) > { > struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf; > struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); > + uint64_t min_intvl_ns, min_intvl_cyc; > struct cnxk_tim_ring *tim_ring; > + enum roc_tim_clk_src clk_src; > + uint64_t clk_freq = 0; > int i, rc; > > if (dev == NULL) > @@ -139,25 +144,52 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) > goto tim_ring_free; > } > > - if (NSEC2TICK(RTE_ALIGN_MUL_CEIL( > - rcfg->timer_tick_ns, > - cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())), > - cnxk_tim_cntfrq()) < > - cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) { > - if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES) > - rcfg->timer_tick_ns = TICK2NSEC( > - cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()), > - cnxk_tim_cntfrq()); > - else { > + clk_src = cnxk_tim_convert_clk_src(rcfg->clk_src); > + if (clk_src == ROC_TIM_CLK_SRC_INVALID) { > + plt_err("Invalid clock source"); > + goto tim_hw_free; > + } > + > + rc = cnxk_tim_get_clk_freq(dev, clk_src, &clk_freq); > + if (rc < 0) { > + plt_err("Failed to get clock frequency"); > + goto tim_hw_free; > + } > + > + rc = roc_tim_lf_interval(&dev->tim, clk_src, clk_freq, &min_intvl_ns, > + &min_intvl_cyc); > + if (rc < 0) { > + plt_err("Failed to get min interval details"); > + goto tim_hw_free; > + } > + > + if (rcfg->timer_tick_ns < min_intvl_ns) { > + if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES) { > + rcfg->timer_tick_ns = min_intvl_ns; > + } else { > rc = -ERANGE; > goto tim_hw_free; > } > } > + > + if (rcfg->timer_tick_ns > rcfg->max_tmo_ns) { > + plt_err("Max timeout to too high"); > + rc = -ERANGE; > + goto tim_hw_free; > + } > + > + /* Round */ > + tim_ring->tck_nsec = > + round(RTE_ALIGN_MUL_NEAR((long double)rcfg->timer_tick_ns, > + cnxk_tim_ns_per_tck(clk_freq))); > + > + tim_ring->tck_int = round((long double)tim_ring->tck_nsec / > + cnxk_tim_ns_per_tck(clk_freq)); > + tim_ring->tck_nsec = > + ceil(tim_ring->tck_int * cnxk_tim_ns_per_tck(clk_freq)); > + > tim_ring->ring_id = adptr->data->id; > - tim_ring->clk_src = (int)rcfg->clk_src; > - tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL( > - rcfg->timer_tick_ns, > - cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())); > + tim_ring->clk_src = clk_src; > tim_ring->max_tout = rcfg->max_tmo_ns; > tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); > tim_ring->nb_timers = rcfg->nb_timers; > @@ -201,11 +233,9 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) > if (rc < 0) > goto tim_bkt_free; > > - rc = roc_tim_lf_config( > - &dev->tim, tim_ring->ring_id, > - cnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0, > - tim_ring->nb_bkts, tim_ring->chunk_sz, > - NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq())); > + rc = roc_tim_lf_config(&dev->tim, tim_ring->ring_id, clk_src, 0, 0, > + tim_ring->nb_bkts, tim_ring->chunk_sz, > + tim_ring->tck_int, tim_ring->tck_nsec, clk_freq); > if (rc < 0) { > plt_err("Failed to configure timer ring"); > goto tim_chnk_free; > @@ -300,7 +330,6 @@ cnxk_tim_ring_start(const struct rte_event_timer_adapter *adptr) > if (rc < 0) > return rc; > > - tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()); > tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts; > tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int); > tim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts); > diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h > index 2478a5c1df..1fb17f571d 100644 > --- a/drivers/event/cnxk/cnxk_tim_evdev.h > +++ b/drivers/event/cnxk/cnxk_tim_evdev.h > @@ -98,13 +98,6 @@ struct cnxk_tim_evdev { > struct cnxk_tim_ctl *ring_ctl_data; > }; > > -enum cnxk_tim_clk_src { > - CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK, > - CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0, > - CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1, > - CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2, > -}; > - > struct cnxk_tim_bkt { > uint64_t first_chunk; > union { > @@ -147,7 +140,7 @@ struct cnxk_tim_ring { > uint64_t max_tout; > uint64_t nb_chunks; > uint64_t chunk_sz; > - enum cnxk_tim_clk_src clk_src; > + enum roc_tim_clk_src clk_src; > } __rte_cache_aligned; > > struct cnxk_tim_ent { > @@ -167,31 +160,10 @@ cnxk_tim_priv_get(void) > return mz->addr; > } > > -static inline uint64_t > -cnxk_tim_min_tmo_ticks(uint64_t freq) > +static inline long double > +cnxk_tim_ns_per_tck(uint64_t freq) > { > - if (roc_model_runtime_is_cn9k()) > - return CN9K_TIM_MIN_TMO_TKS; > - else /* CN10K min tick is of 1us */ > - return freq / USECPERSEC; > -} > - > -static inline uint64_t > -cnxk_tim_min_resolution_ns(uint64_t freq) > -{ > - return NSECPERSEC / freq; > -} > - > -static inline enum roc_tim_clk_src > -cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src) > -{ > - switch (clk_src) { > - case RTE_EVENT_TIMER_ADAPTER_CPU_CLK: > - return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS : > - ROC_TIM_CLK_SRC_GTI; > - default: > - return ROC_TIM_CLK_SRC_INVALID; > - } > + return (long double)NSECPERSEC / freq; > } > > #ifdef RTE_ARCH_ARM64 > @@ -226,6 +198,51 @@ cnxk_tim_cntfrq(void) > } > #endif > > +static inline enum roc_tim_clk_src > +cnxk_tim_convert_clk_src(enum rte_event_timer_adapter_clk_src clk_src) > +{ > + switch (clk_src) { > + case RTE_EVENT_TIMER_ADAPTER_CPU_CLK: > + return ROC_TIM_CLK_SRC_GTI; > + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK0: > + return ROC_TIM_CLK_SRC_10NS; > + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK1: > + return ROC_TIM_CLK_SRC_GPIO; > + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK2: > + return ROC_TIM_CLK_SRC_PTP; > + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK3: > + return roc_model_constant_is_cn9k() ? ROC_TIM_CLK_SRC_INVALID : > + ROC_TIM_CLK_SRC_SYNCE; > + default: > + return ROC_TIM_CLK_SRC_INVALID; > + } > +} > + > +static inline int > +cnxk_tim_get_clk_freq(struct cnxk_tim_evdev *dev, enum roc_tim_clk_src clk_src, > + uint64_t *freq) > +{ > + if (freq == NULL) > + return -EINVAL; > + > + PLT_SET_USED(dev); > + switch (clk_src) { > + case ROC_TIM_CLK_SRC_GTI: > + *freq = cnxk_tim_cntfrq(); > + break; > + case ROC_TIM_CLK_SRC_10NS: > + *freq = 1E8; > + break; > + case ROC_TIM_CLK_SRC_GPIO: > + case ROC_TIM_CLK_SRC_PTP: > + case ROC_TIM_CLK_SRC_SYNCE: > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > #define TIM_ARM_FASTPATH_MODES \ > FP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ > FP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \ > -- > 2.17.1 >