[dpdk-dev] [PATCH 1/2] net/octeontx2: fix ptype translation logic

[dpdk-dev] [PATCH 1/2] net/octeontx2: fix ptype translation logic

[Nithin Dabilpuram]

Extract and use layer type LB..LE for non-tunnel ptype and
LF..LH as tunnel ptype translation.

Fixes: 6e892eabce11 ("net/octeontx2: support packet type")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/octeontx2/otx2_lookup.c | 22 ++++++++++++----------
 drivers/net/octeontx2/otx2_rx.h     | 15 ++++++++-------
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/drivers/net/octeontx2/otx2_lookup.c b/drivers/net/octeontx2/otx2_lookup.c
index 99199d0..13c26a9 100644
--- a/drivers/net/octeontx2/otx2_lookup.c
+++ b/drivers/net/octeontx2/otx2_lookup.c
@@ -78,7 +78,8 @@ static void
 nix_create_non_tunnel_ptype_array(uint16_t *ptype)
 {
 	uint8_t lb, lc, ld, le;
-	uint16_t idx, val;
+	uint16_t val;
+	uint32_t idx;
 
 	for (idx = 0; idx < PTYPE_NON_TUNNEL_ARRAY_SZ; idx++) {
 		lb = idx & 0xF;
@@ -180,28 +181,29 @@ nix_create_non_tunnel_ptype_array(uint16_t *ptype)
 	}
 }
 
-#define TU_SHIFT(x) ((x) >> PTYPE_WIDTH)
+#define TU_SHIFT(x) ((x) >> PTYPE_NON_TUNNEL_WIDTH)
 static void
 nix_create_tunnel_ptype_array(uint16_t *ptype)
 {
-	uint8_t le, lf, lg;
-	uint16_t idx, val;
+	uint8_t lf, lg, lh;
+	uint16_t val;
+	uint32_t idx;
 
 	/* Skip non tunnel ptype array memory */
 	ptype = ptype + PTYPE_NON_TUNNEL_ARRAY_SZ;
 
 	for (idx = 0; idx < PTYPE_TUNNEL_ARRAY_SZ; idx++) {
-		le = idx & 0xF;
-		lf = (idx & 0xF0) >> 4;
-		lg = (idx & 0xF00) >> 8;
+		lf = idx & 0xF;
+		lg = (idx & 0xF0) >> 4;
+		lh = (idx & 0xF00) >> 8;
 		val = RTE_PTYPE_UNKNOWN;
 
-		switch (le) {
+		switch (lf) {
 		case NPC_LT_LF_TU_ETHER:
 			val |= TU_SHIFT(RTE_PTYPE_INNER_L2_ETHER);
 			break;
 		}
-		switch (lf) {
+		switch (lg) {
 		case NPC_LT_LG_TU_IP:
 			val |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV4);
 			break;
@@ -209,7 +211,7 @@ nix_create_tunnel_ptype_array(uint16_t *ptype)
 			val |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV6);
 			break;
 		}
-		switch (lg) {
+		switch (lh) {
 		case NPC_LT_LH_TU_TCP:
 			val |= TU_SHIFT(RTE_PTYPE_INNER_L4_TCP);
 			break;
diff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h
index d12e8b8..1a1ac40 100644
--- a/drivers/net/octeontx2/otx2_rx.h
+++ b/drivers/net/octeontx2/otx2_rx.h
@@ -8,9 +8,10 @@
 /* Default mark value used when none is provided. */
 #define OTX2_FLOW_ACTION_FLAG_DEFAULT	0xffff
 
-#define PTYPE_WIDTH 12
-#define PTYPE_NON_TUNNEL_ARRAY_SZ	BIT(PTYPE_WIDTH)
-#define PTYPE_TUNNEL_ARRAY_SZ		BIT(PTYPE_WIDTH)
+#define PTYPE_NON_TUNNEL_WIDTH		16
+#define PTYPE_TUNNEL_WIDTH		12
+#define PTYPE_NON_TUNNEL_ARRAY_SZ	BIT(PTYPE_NON_TUNNEL_WIDTH)
+#define PTYPE_TUNNEL_ARRAY_SZ		BIT(PTYPE_TUNNEL_WIDTH)
 #define PTYPE_ARRAY_SZ			((PTYPE_NON_TUNNEL_ARRAY_SZ +\
 					 PTYPE_TUNNEL_ARRAY_SZ) *\
 					 sizeof(uint16_t))
@@ -97,11 +98,11 @@ static __rte_always_inline uint32_t
 nix_ptype_get(const void * const lookup_mem, const uint64_t in)
 {
 	const uint16_t * const ptype = lookup_mem;
-	const uint16_t lg_lf_le = (in & 0xFFF000000000000) >> 48;
-	const uint16_t tu_l2 = ptype[(in & 0x000FFF000000000) >> 36];
-	const uint16_t il4_tu = ptype[PTYPE_NON_TUNNEL_ARRAY_SZ + lg_lf_le];
+	const uint16_t lh_lg_lf = (in & 0xFFF0000000000000) >> 52;
+	const uint16_t tu_l2 = ptype[(in & 0x000FFFF000000000) >> 36];
+	const uint16_t il4_tu = ptype[PTYPE_NON_TUNNEL_ARRAY_SZ + lh_lg_lf];
 
-	return (il4_tu << PTYPE_WIDTH) | tu_l2;
+	return (il4_tu << PTYPE_NON_TUNNEL_WIDTH) | tu_l2;
 }
 
 static __rte_always_inline uint32_t
-- 
2.8.4

[dpdk-dev] [PATCH 2/2] net/octeontx2: add ptype translation for ICMP6

[Nithin Dabilpuram]

Update ptype translation logic with ICMP6
in both outer and inner layers.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/octeontx2/otx2_lookup.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/octeontx2/otx2_lookup.c b/drivers/net/octeontx2/otx2_lookup.c
index 13c26a9..fd0bc10 100644
--- a/drivers/net/octeontx2/otx2_lookup.c
+++ b/drivers/net/octeontx2/otx2_lookup.c
@@ -138,6 +138,7 @@ nix_create_non_tunnel_ptype_array(uint16_t *ptype)
 			val |= RTE_PTYPE_L4_SCTP;
 			break;
 		case NPC_LT_LD_ICMP:
+		case NPC_LT_LD_ICMP6:
 			val |= RTE_PTYPE_L4_ICMP;
 			break;
 		case NPC_LT_LD_IGMP:
@@ -222,6 +223,7 @@ nix_create_tunnel_ptype_array(uint16_t *ptype)
 			val |= TU_SHIFT(RTE_PTYPE_INNER_L4_SCTP);
 			break;
 		case NPC_LT_LH_TU_ICMP:
+		case NPC_LT_LH_TU_ICMP6:
 			val |= TU_SHIFT(RTE_PTYPE_INNER_L4_ICMP);
 			break;
 		}
-- 
2.8.4

Re: [dpdk-dev] [PATCH 1/2] net/octeontx2: fix ptype translation logic

[Jerin Jacob]

On Wed, Sep 4, 2019 at 1:34 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> Extract and use layer type LB..LE for non-tunnel ptype and
> LF..LH as tunnel ptype translation.
>
> Fixes: 6e892eabce11 ("net/octeontx2: support packet type")
> Cc: stable@dpdk.org
>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

Acked-by: Jerin Jacob <jerinj@marvell.com>

Series applied to dpdk-next-net-mrvl/master. Thanks.