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From: Jerin Jacob <jerinjacobk@gmail.com>
To: Rahul Bhansali <rbhansali@marvell.com>,
	Thomas Monjalon <thomas@monjalon.net>,
	 Ferruh Yigit <ferruh.yigit@xilinx.com>
Cc: dpdk-dev <dev@dpdk.org>,
	Nithin Dabilpuram <ndabilpuram@marvell.com>,
	 Kiran Kumar K <kirankumark@marvell.com>,
	Sunil Kumar Kori <skori@marvell.com>,
	 Satha Rao <skoteshwar@marvell.com>,
	Jerin Jacob <jerinj@marvell.com>
Subject: Re: [PATCH 1/4] common/cnxk: add CN103XX platform support
Date: Sun, 1 May 2022 19:15:01 +0530	[thread overview]
Message-ID: <CALBAE1N80osR-CQ1615wJ3=R2kqj5Yh1uYtDRiwVUcqqC0zmPg@mail.gmail.com> (raw)
In-Reply-To: <20220325130351.3207019-1-rbhansali@marvell.com>

On Fri, Mar 25, 2022 at 6:34 PM Rahul Bhansali <rbhansali@marvell.com> wrote:
>
> Added support for CN103XX (cn10kb) platform.

Since 2/4. 3/4, 4/4 patches do not have any special description.
Please squash all patches and send v2.
It can go through the main tree as it touches all driver's PCI ID values.


>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> ---
>  doc/guides/platform/cnxk.rst        |  1 +
>  drivers/common/cnxk/roc_constants.h |  1 +
>  drivers/common/cnxk/roc_model.c     |  4 ++++
>  drivers/common/cnxk/roc_model.h     | 11 ++++++++++-
>  4 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
> index 3dee725ac5..92aa702a78 100644
> --- a/doc/guides/platform/cnxk.rst
> +++ b/doc/guides/platform/cnxk.rst
> @@ -18,6 +18,7 @@ Supported OCTEON cnxk SoCs
>  - CN98xx
>  - CN106xx
>  - CNF105xx
> +- CN103XX
>
>  Resource Virtualization Unit architecture
>  -----------------------------------------
> diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
> index 38e2087a26..1daaabfe55 100644
> --- a/drivers/common/cnxk/roc_constants.h
> +++ b/drivers/common/cnxk/roc_constants.h
> @@ -52,6 +52,7 @@
>  #define PCI_SUBSYSTEM_DEVID_CN10KA  0xB900
>  #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
>  #define PCI_SUBSYSTEM_DEVID_CNF10KA 0xBA00
> +#define PCI_SUBSYSTEM_DEVID_CN10KB  0xB900
>
>  #define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000
>  #define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400
> diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
> index 4120029541..1dd374e0fd 100644
> --- a/drivers/common/cnxk/roc_model.c
> +++ b/drivers/common/cnxk/roc_model.c
> @@ -16,6 +16,7 @@ struct roc_model *roc_model;
>  #define PART_106xx  0xB9
>  #define PART_105xx  0xBA
>  #define PART_105xxN 0xBC
> +#define PART_103xx  0xBE
>  #define PART_98xx   0xB1
>  #define PART_96xx   0xB2
>  #define PART_95xx   0xB3
> @@ -46,6 +47,7 @@ static const struct model_db {
>  } model_db[] = {
>         {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"},
>         {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"},
> +       {VENDOR_ARM, PART_103xx, 0, 0, ROC_MODEL_CN103xx_A0, "cn10kb_a0"},
>         {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
>         {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
>         {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
> @@ -92,6 +94,8 @@ cn10k_part_get(void)
>                 soc = PART_105xx;
>         } else if (strcmp("cnf10kb", ptr) == 0) {
>                 soc = PART_105xxN;
> +       } else if (strcmp("cn10kb", ptr) == 0) {
> +               soc = PART_103xx;
>         } else {
>                 plt_err("Unidentified 'CPU compatible': <%s>", ptr);
>                 goto fclose;
> diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
> index 4567566169..885c3d668f 100644
> --- a/drivers/common/cnxk/roc_model.h
> +++ b/drivers/common/cnxk/roc_model.h
> @@ -24,6 +24,7 @@ struct roc_model {
>  #define ROC_MODEL_CN106xx_A0   BIT_ULL(20)
>  #define ROC_MODEL_CNF105xx_A0  BIT_ULL(21)
>  #define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)
> +#define ROC_MODEL_CN103xx_A0   BIT_ULL(23)
>  /* Following flags describe platform code is running on */
>  #define ROC_ENV_HW   BIT_ULL(61)
>  #define ROC_ENV_EMUL BIT_ULL(62)
> @@ -50,8 +51,10 @@ struct roc_model {
>  #define ROC_MODEL_CN106xx   (ROC_MODEL_CN106xx_A0)
>  #define ROC_MODEL_CNF105xx  (ROC_MODEL_CNF105xx_A0)
>  #define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0)
> +#define ROC_MODEL_CN103xx   (ROC_MODEL_CN103xx_A0)
>  #define ROC_MODEL_CN10K                                                        \
> -       (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
> +       (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN |        \
> +        ROC_MODEL_CN103xx)
>  #define ROC_MODEL_CNF10K (ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
>
>  /* Runtime variants */
> @@ -152,6 +155,12 @@ roc_model_is_cnf10kb(void)
>         return roc_model->flag & ROC_MODEL_CNF105xxN;
>  }
>
> +static inline uint64_t
> +roc_model_is_cn10kb_a0(void)
> +{
> +       return roc_model->flag & ROC_MODEL_CN103xx_A0;
> +}
> +
>  static inline uint64_t
>  roc_model_is_cn10ka_a0(void)
>  {
> --
> 2.25.1
>

  parent reply	other threads:[~2022-05-01 13:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-25 13:03 Rahul Bhansali
2022-03-25 13:03 ` [PATCH 2/4] net/cnxk: " Rahul Bhansali
2022-03-25 13:03 ` [PATCH 3/4] event/cnxk: " Rahul Bhansali
2022-03-25 13:03 ` [PATCH 4/4] mempool/cnxk: " Rahul Bhansali
2022-05-01 13:45 ` Jerin Jacob [this message]
2022-05-02 11:31 ` [PATCH v2] common/cnxk: " Rahul Bhansali
2022-05-02 16:24   ` Jerin Jacob
2022-05-24  5:02     ` [EXT] " Rahul Bhansali
2022-06-01 19:59     ` Thomas Monjalon

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