From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ACF11A0C41; Tue, 7 Sep 2021 10:26:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6A469410EC; Tue, 7 Sep 2021 10:26:01 +0200 (CEST) Received: from mail-io1-f46.google.com (mail-io1-f46.google.com [209.85.166.46]) by mails.dpdk.org (Postfix) with ESMTP id 9C091410EB for ; Tue, 7 Sep 2021 10:26:00 +0200 (CEST) Received: by mail-io1-f46.google.com with SMTP id a13so11632854iol.5 for ; Tue, 07 Sep 2021 01:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=WHnz0rGuGWw5V+9y5BsOoM1XgObyoJarAC0/r4xCY0s=; b=DkqNCYzMu0wEGo3tAAwIbXNi7OlAOKkKktlS+r4Ci5ifLq3K3n3TvGHDrb8FIcTatB t6UxX9DAd5EmBy+CDIg+MVPAJi70B4nSisnLHzP4Zuoqu7OLoE6bMTTSjmEzG8Yv8YN+ XFWnZ7JqdNbHwBx4xe7KHwQ7gthl7SuBo8Yl+50UkR1EJBpqcyzWWWwyiD/GDEXDEBBr v1beZbMp+4F/iF43wtj6H+sq/ReeUOdJ4BxDuj8fkm/W0Yws7k3LghimLX5F/8wBOtF4 9CUcemu5NIFaEjNtvrY72nUE142VqGfMP/MN8/HOCTOvQd+ckN46hlVNnruhGtNPCwAR kaNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WHnz0rGuGWw5V+9y5BsOoM1XgObyoJarAC0/r4xCY0s=; b=gmKtz/dbMQQ1yPNgddAsDi8mGoF5A/klDzhTKxmuYnX1JsfBtGTICO9otJdIpq6wxK EqYBSewbSkZI2VYrFbyKvTVbjCTYd5FyH9WQ5BPekX/aV+KEwji5dQ5cUKgFxezkL0SA nbfFOYBWV6XmNRT8TlHBiSKRN2XsI7dDnWeyUX4DXH+SUGyVcFbEnO75hApk02FxLDpQ xGfWARg2usDdk3/FhMirttFvAL0kJpEDavIgWs8CyIpKMiXI2Q0xQeQUKpbxlruk4DuL ggYLXD5JoyhqjHRMPH4bzwtayTNZuSg3dK/1D0FAfiRgwmWHl1nqJjcycThbC/aI4fQB 3c/g== X-Gm-Message-State: AOAM530dtn8SDgSXBhCeVJadO0NfzJcAwUXPhebx/EwzL+YTaNpmyGbr 12RbdJDv8b2y5bEfk/Zn1LSn8SH1e9lz28lkf34= X-Google-Smtp-Source: ABdhPJyKiGJp02huIS3ZhGRh9GQbCUWmodIGsNfOU2iGR6YpvUj4ndeEpp3+X8SkwlbhvRfL/F0zX1MMu/NYHMWIWN4= X-Received: by 2002:a05:6602:1543:: with SMTP id h3mr12800992iow.123.1631003159957; Tue, 07 Sep 2021 01:25:59 -0700 (PDT) MIME-Version: 1.0 References: <20210810072100.4233-1-hpothula@marvell.com> In-Reply-To: <20210810072100.4233-1-hpothula@marvell.com> From: Jerin Jacob Date: Tue, 7 Sep 2021 13:55:33 +0530 Message-ID: To: Hanumanth Reddy Pothula , Ferruh Yigit Cc: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K , dpdk-dev Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH] net/octeontx2: configure MTU value correctly X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Aug 10, 2021 at 12:52 PM Hanumanth Reddy Pothula wrote: > > Update MTU value based on PTP enable status and reserve eight > bytes in TX path to accommodate VLAN tags. > > If PTP is enabled maximum allowed MTU is 9200 otherwise it's 9208. > > Signed-off-by: Hanumanth Reddy Pothula Updated as [for-next-net]dell[dpdk-next-net-mrvl] $ git show commit b6b92bb4bf28c39e55a538741cf408041a28f412 (HEAD -> for-next-net) Author: Hanumanth Reddy Pothula Date: Tue Aug 10 12:51:00 2021 +0530 net/octeontx2: fix MTU value Update MTU value based on PTP enable status and reserve eight bytes in TX path to accommodate VLAN tags. If PTP is enabled maximum allowed MTU is 9200 otherwise it's 9208. Fixes: b5dc3140448e ("net/octeontx2: support base PTP") Cc: stable@dpdk.org Signed-off-by: Hanumanth Reddy Pothula Acked-by: Jerin Jacob Applied to dpdk-next-net-mrvl/for-next-net. Thanks > --- > drivers/net/octeontx2/otx2_ethdev_ops.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c > index 5a4501208e..552e6bd43d 100644 > --- a/drivers/net/octeontx2/otx2_ethdev_ops.c > +++ b/drivers/net/octeontx2/otx2_ethdev_ops.c > @@ -17,7 +17,8 @@ otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) > struct nix_frs_cfg *req; > int rc; > > - frame_size += NIX_TIMESYNC_RX_OFFSET * otx2_ethdev_is_ptp_en(dev); > + if (dev->configured && otx2_ethdev_is_ptp_en(dev)) > + frame_size += NIX_TIMESYNC_RX_OFFSET; > > /* Check if MTU is within the allowed range */ > if (frame_size < NIX_MIN_FRS || frame_size > NIX_MAX_FRS) > @@ -547,6 +548,11 @@ otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) > devinfo->max_vfs = pci_dev->max_vfs; > devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD; > devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD; > + if (dev->configured && otx2_ethdev_is_ptp_en(dev)) { > + devinfo->max_mtu -= NIX_TIMESYNC_RX_OFFSET; > + devinfo->min_mtu -= NIX_TIMESYNC_RX_OFFSET; > + devinfo->max_rx_pktlen -= NIX_TIMESYNC_RX_OFFSET; > + } > > devinfo->rx_offload_capa = dev->rx_offload_capa; > devinfo->tx_offload_capa = dev->tx_offload_capa; > -- > 2.25.1 >