From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1D324A0C43; Thu, 30 Sep 2021 17:53:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8C28D410E5; Thu, 30 Sep 2021 17:53:53 +0200 (CEST) Received: from mail-io1-f47.google.com (mail-io1-f47.google.com [209.85.166.47]) by mails.dpdk.org (Postfix) with ESMTP id DADED40DDA for ; Thu, 30 Sep 2021 17:53:52 +0200 (CEST) Received: by mail-io1-f47.google.com with SMTP id h129so8231670iof.1 for ; Thu, 30 Sep 2021 08:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OAZUybNXujmVn1FLIQ/VD9dPQd9NhwY61XTxAN/6na8=; b=A+G9UqVqWH7hQy3e/PsufgGLYBehn20i6+F/zNnW1Sk6v8XeAZ4wvVN/XRpwWX5Vgv 7UAEZGsDu38/ZYqBtUQUIrJxseWZvU5Dguqk+3x7w/+vhVPmyNVlz/LC6NSCE3u116fR UfRgC4M+14HXpDmR+RT81TdGxO3uflW8i0aFgAvNXoamBVrdLxPCPtvxTz7Om5H67d7q JUAZhtlH0bW+JvRBp6qndpGYluVG2bwYX0Kje3S9ZzY1Q3SQoxJFja2eNtA23tGH8owJ rv7ppWFlovORnW6nuI1n0Hivn6kBgsH8AcuAc5hY0hEAj31GNMjA0whi7QBxjabYPi5a ZOiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OAZUybNXujmVn1FLIQ/VD9dPQd9NhwY61XTxAN/6na8=; b=7887iBAmZUrb0Yp7LhCDDhM0oce+t46QTuYgxZ7fwRglzUuibMwhTSot2T/YWxKGiN Qgmeq9SNVPgNhAMWgjYAw+3uj6LG8G4tb3980it+Qn7nG9MLupJ6vWfaPq8j0D1RQAOK jxeSwtwvawEVu0fJxRkDQ31FHzvAJJ7vrdeFkMgfESxKWRF1P5YAGQm2rJOtszI0xH7x OpZ8XzGxNC0SKPzuU1W8tvdtyxJsavUnSPgJYJ8B+yP+AAAveT1tkbfhiYDA4YDsd3TD vdnymNYXhulLaf6CMg2Q/9uOg2OLKHAZFkcn8HvoWXCmQt+JKpTzvwvW1Rjz1ejl+lQO K87g== X-Gm-Message-State: AOAM530j+4N7vpm/Y99QEMK67La6XZ3m3LHa24z/zcyyBy/VSKDAwKxd MelP2oetOeRbWIAUn8fbZ2+phgiQUrNga6huOfPTz084VdI= X-Google-Smtp-Source: ABdhPJxJ9D1YjQ2F4mzppv0qUhnSKLNppvx8J+/QxpEWg1N9sApz7lxRSQbiW8Yu/bRfvuTFvcOTH9/yL3P3T7wLEEY= X-Received: by 2002:a05:6638:339e:: with SMTP id h30mr5489056jav.99.1633017232170; Thu, 30 Sep 2021 08:53:52 -0700 (PDT) MIME-Version: 1.0 References: <20210921110038.115560-1-hkalra@marvell.com> In-Reply-To: <20210921110038.115560-1-hkalra@marvell.com> From: Jerin Jacob Date: Thu, 30 Sep 2021 21:23:26 +0530 Message-ID: To: Harman Kalra , Ferruh Yigit Cc: dpdk-dev , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 1/2] common/cnxk: clear rvum interrupts X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Sep 21, 2021 at 4:30 PM Harman Kalra wrote: > > As per an known HW issue RVUM interrupts may get dropped, If an RVUM > interrupt event occurs when PCCPF_XXX_MSIX_CAP_HDR[MSIXEN]=0 then no > interrupt is triggered, which is expected. But after MSIXEN is set to > 1, subsequently if same interrupts event occurs again, still no > interrupt will be triggered. > > As a workaround, all RVUM interrupt lines should be cleared between > MSIXEN=0 and MSIXEN=1. > > Signed-off-by: Harman Kalra Series Acked-by: Jerin Jacob Series applied to dpdk-next-net-mrvl/for-next-net. Thanks. Changed the git log to: commit b17c509dccf4b05d1471a2dac9c6cfd6ee78c94f (HEAD -> for-next-net) Author: Harman Kalra Date: Tue Sep 21 16:30:38 2021 +0530 common/cnxk: enable CQ overflow errata An issue exists on some HW revisions whereby if a CQ overflows NIX may have undefined behavior, e.g. free incorrect buffers. Implementing a workaround for this known HW issue. Signed-off-by: Harman Kalra Acked-by: Jerin Jacob commit 416bf1eda5727a967de7b4c0475d350996e41720 Author: Harman Kalra Date: Tue Sep 21 16:30:37 2021 +0530 common/cnxk: enable RVUM interrupt errata As per an known HW issue RVUM interrupts may get dropped, If an RVUM interrupt event occurs when PCCPF_XXX_MSIX_CAP_HDR[MSIXEN]=0 then no interrupt is triggered, which is expected. But after MSIXEN is set to 1, subsequently if same interrupts event occurs again, still no interrupt will be triggered. As a workaround, all RVUM interrupt lines should be cleared between MSIXEN=0 and MSIXEN=1. Signed-off-by: Harman Kalra Acked-by: Jerin Jacob > --- > drivers/common/cnxk/roc_dev.c | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c > index 4e204373dc..ce6980cbe4 100644 > --- a/drivers/common/cnxk/roc_dev.c > +++ b/drivers/common/cnxk/roc_dev.c > @@ -884,6 +884,38 @@ vf_flr_register_irqs(struct plt_pci_device *pci_dev, struct dev *dev) > return 0; > } > > +static void > +clear_rvum_interrupts(struct dev *dev) > +{ > + uint64_t intr; > + int i; > + > + if (dev_is_vf(dev)) { > + /* Clear VF mbox interrupt */ > + intr = plt_read64(dev->bar2 + RVU_VF_INT); > + if (intr) > + plt_write64(intr, dev->bar2 + RVU_VF_INT); > + } else { > + /* Clear AF PF interrupt line */ > + intr = plt_read64(dev->bar2 + RVU_PF_INT); > + if (intr) > + plt_write64(intr, dev->bar2 + RVU_PF_INT); > + for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) { > + /* Clear MBOX interrupts */ > + intr = plt_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(i)); > + if (intr) > + plt_write64(intr, > + dev->bar2 + > + RVU_PF_VFPF_MBOX_INTX(i)); > + /* Clear VF FLR interrupts */ > + intr = plt_read64(dev->bar2 + RVU_PF_VFFLR_INTX(i)); > + if (intr) > + plt_write64(intr, > + dev->bar2 + RVU_PF_VFFLR_INTX(i)); > + } > + } > +} > + > int > dev_active_vfs(struct dev *dev) > { > @@ -1090,6 +1122,9 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev) > intr_offset = RVU_PF_INT; > } > > + /* Clear all RVUM interrupts */ > + clear_rvum_interrupts(dev); > + > /* Initialize the local mbox */ > rc = mbox_init(&dev->mbox_local, mbox, bar2, direction, 1, intr_offset); > if (rc) > -- > 2.18.0 >