From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 52002A0A02; Wed, 24 Mar 2021 13:55:05 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 30B004067B; Wed, 24 Mar 2021 13:55:05 +0100 (CET) Received: from mail-il1-f176.google.com (mail-il1-f176.google.com [209.85.166.176]) by mails.dpdk.org (Postfix) with ESMTP id 5CBA94014F for ; Wed, 24 Mar 2021 13:55:04 +0100 (CET) Received: by mail-il1-f176.google.com with SMTP id c17so21271796ilj.7 for ; Wed, 24 Mar 2021 05:55:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=lKrT3hBYZ37KvuxjNNSwkUFuhZCU1O+XJzw/7oxBddA=; b=Jh2+sc+cRjKVMTvbcTH2AWV3qn9XCn8TQZsRYNiQJ2ULCLajNHJBVR8QnrC8SwDXCy XwSI2cotTsiGLSrVKukNIVVlG8srANKJ2ZNVujpSZh8AMQkoMxQ/BAlhbho2kmZE95Vf UknrC5Ynem7+v/tMSaqJC6o7tdUVBguBQo+i4TMZgeetiKfxcruNbJji221EY5QXCNbv MZC2vzyjYj/JB8u2gfrp8ozxXCdrrEhJky1NLH6soRwEMqdsTWgO9T6K+R89YXgDX4r+ Bm5T8d7vzcD5d9FzMOhgiuqA6EYG+o+XMJr0Q3VmG4V/kp/E5/qEVU+ksxeAWYMSg78P 2URA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=lKrT3hBYZ37KvuxjNNSwkUFuhZCU1O+XJzw/7oxBddA=; b=UroL1+/nRlLFNEf1QdQRiu3cIjDv4495g+RKXvP60Tg2lg5AtsNIWWECgCEVDIivvr NvesQmikAOBUHDm1s3Yf1/OZOovwhkpoZ77EyW4repfeQ4+DZKen6JIYQQrVpZnCZWTY zRwD2IRzD2F/fQf+t2kBmmdo0DNlZYEIQUs/gub21t5doE0jKoIpQO11Mnlk7Fsa22GJ PtcsH2U2nfoguNAq39IJDfi06xADAongegcVD3L1JvjSrv0GOmqAdZNlOeDDNr53+Fp5 hDr8WM8hC+lrRwI9UnVUV8jpSKVQceIRUHw8mPn4OJz5wQiqhsD9YY8eFkEwnuI9dKp1 vy1Q== X-Gm-Message-State: AOAM530Skic2lDzODUHh/X/vUxJCI6xlql7SmIQb3K/GOKht3LG8PEyl WXuHPMsaONuObCimxTR0dW1wvHKkXyWJgeDEs3g= X-Google-Smtp-Source: ABdhPJzq4w3teWzok6ZfqZfG2EA23NBAA5i90yDA4CIhpi2VdgmsQTiUp7dKFTX9jXfd9erAj3YmwvGfD696bpw4V9w= X-Received: by 2002:a92:d28b:: with SMTP id p11mr2561445ilp.130.1616590503597; Wed, 24 Mar 2021 05:55:03 -0700 (PDT) MIME-Version: 1.0 References: <20210225190112.2073-1-pbhagavatula@marvell.com> In-Reply-To: From: Jerin Jacob Date: Wed, 24 Mar 2021 18:24:47 +0530 Message-ID: To: David Marchand , Ray Kinsella Cc: Pavan Nikhilesh , Harman Kalra , Thomas Monjalon , Jerin Jacob , Bruce Richardson , dpdk-dev Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 1/2] eal: make max interrupt vector id configurable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Mar 24, 2021 at 4:45 PM David Marchand wrote: > > On Wed, Mar 24, 2021 at 12:01 PM Jerin Jacob wrote: > > > > On Fri, Feb 26, 2021 at 12:31 AM wrote: > > > > > > From: Pavan Nikhilesh > > > > > > Make RTE_MAX_RXTX_INTR_VEC_ID configurable as MSI-X support a > > > maximum of 2048 vectors. > > > The default value is unchanged and set to 512. > > > > > > IMO, We dont need to make it configurable and each platform sets its > > value. That scheme won't work as generic distribution build will fail > > to run. > > Since PCIe specification defines this value and there is no > > performance impact on increasing this, > > IMO, We can change to 2048 as default. > > It probably breaks rte_intr_* ABI. Yes. Even though all APIs are used as a pointer (ie. "struct rte_intr_handle *"), the definition kept in the header file. > struct rte_intr_handle { > ... > int efds[RTE_MAX_RXTX_INTR_VEC_ID]; /**< intr vectors/efds mapping */ > struct rte_epoll_event elist[RTE_MAX_RXTX_INTR_VEC_ID]; > /**< intr vector epoll event */ > ... > > > I see you need this for octeontx2, so wondering if you could handle > this differently in octeontx2 drivers? This is an issue with any PCIe device that has more than 512 MSIX interrupts. The PCI spec the max is defined as 2K. CN10K drivers have 1K interrupt lines per PCIe device. I think, following are the options. 1) To avoid ABI breakage in default configuration use the existing patch 2) In 21.11 break ABI and Either change to a) RTE_MAX_RXTX_INTR_VEC_ID as 1024 or b) Make it full dynamic allocation based on PCI device MSIX size on probe time. That brings some kind of dependency rte_intr with PCI device. Need to understand, How it can clearly be abstracted out and Is it worth trouble for the amount of memory. Looks like the cost of one entry is 40B. So additional 512 is 40B * 512 = 21KB virtual memory. Thoughts? > > > -- > David Marchand >