From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C62ACA04BC; Thu, 8 Oct 2020 15:12:40 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BD5311BFD9; Thu, 8 Oct 2020 15:12:38 +0200 (CEST) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by dpdk.org (Postfix) with ESMTP id A8C581BF63 for ; Thu, 8 Oct 2020 15:12:36 +0200 (CEST) Received: by mail-io1-f67.google.com with SMTP id l8so6041894ioh.11 for ; Thu, 08 Oct 2020 06:12:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=PIfRem9BCS9Jwf1wLovqWSTe9D6lKubOz99PQAii9kE=; b=QMVY7XFqCR7GpyLzvwx44taAnRry2ZC2WUMVfsm3UF7IrBNJXoE0AwSk/ugbT8bXQW Ui5z+S6nGVVfMdq5SbcS4V9xfxdUtg+I2KQnM9OVw88ry8SK54URKR4PGGvZgSCeWtoh lA7Yrg99o7XidYUN4YW4gAlAbHTb8hQX6dnzeK7XTGrOzvKJATFo8/y80B+phRVdWwBk +kt1mhOOirzwmMnTrP14PgWCy2Xf5ItB+Eq+uvRoASLFabHdOxW4C1DcDLPUO4mRqqXf PDyyGyIteSNTKQzHKZtERJqMR8/J+t0WE7ld1nY9lSLvACUfA6aKHWzj6dmmHo6zCcRl 5wvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PIfRem9BCS9Jwf1wLovqWSTe9D6lKubOz99PQAii9kE=; b=YNLKMBrPXCoyHnsxHbes4EhG2+VundBDRi4svIFPYbftoeVY0/jap5A86g9JkzWgHL hzWBzgIFvonLXf0hvFqGEH+SnjlSDJ75aT7gwXPMtdnz3+yl52afTLg0naThPw0AZej5 jeMsJ4pxP1+DW/B2T9l4mvXGsmftbAY9fS//CGg27ouUHzqS5LslAqEWsZpdh5l3vPiS K14Wv1OVFdmCiwtPi/qds7kGpZE9tocy0EjKDrl0dilFtYWKsh/cdRKgaNfrB4+2mrz9 Sao8KI1j9G/xLCDyqhE93uP9++MRyJ1HCwrUhgBVXiCU5J0EZPMw5YNgR36HiqxYwpVt ehPg== X-Gm-Message-State: AOAM532SlmbzG58lIGmgR5lSlu7H/IXoxMtjg0sdkuW4VvUfFkudX/X8 hrlHuCuZTrAG3/cUPdRxB0HH87iNAmJ/oauWouw= X-Google-Smtp-Source: ABdhPJwtlDg0TJfBj3o6Y9AWV9iHyyB3yqXgoiUPQYjeKCglBd2OkhgoIP/x803JDxXf3641wBMqF+V+Em3uKEoglwE= X-Received: by 2002:a5d:9615:: with SMTP id w21mr5873190iol.59.1602162754863; Thu, 08 Oct 2020 06:12:34 -0700 (PDT) MIME-Version: 1.0 References: <1599700614-22809-1-git-send-email-omkar.maslekar@intel.com> <1601512112-12577-1-git-send-email-omkar.maslekar@intel.com> <1601512112-12577-2-git-send-email-omkar.maslekar@intel.com> In-Reply-To: <1601512112-12577-2-git-send-email-omkar.maslekar@intel.com> From: Jerin Jacob Date: Thu, 8 Oct 2020 18:42:18 +0530 Message-ID: To: Omkar Maslekar Cc: dpdk-dev , "Richardson, Bruce" , ciara.loftus@intel.com Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v5] eal: add cache-line demote support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Thu, Oct 1, 2020 at 6:00 AM Omkar Maslekar wrote: > > rte_cldemote is similar to a prefetch hint - in reverse. cldemote(addr) > enables software to hint to hardware that line is likely to be shared. > Useful in core-to-core communications where cache-line is likely to be > shared. ARM and PPC implementation is provided with NOP and can be added > if any equivalent instructions could be used for implementation on those > architectures. > > Signed-off-by: Omkar Maslekar > Acked-by: Bruce Richardson > > --- > v5: documentation updated > fixed formatting issue in release notes > added Acked-by: Bruce Richardson > * > v4: updated bold text for title and fixed margin in release notes > * > v3: fixed warning regarding whitespace > * > v2: documentation updated > --- > --- > doc/guides/rel_notes/release_20_11.rst | 7 +++++++ > lib/librte_eal/arm/include/rte_prefetch_32.h | 5 +++++ > lib/librte_eal/arm/include/rte_prefetch_64.h | 5 +++++ > lib/librte_eal/include/generic/rte_prefetch.h | 14 ++++++++++++++ > lib/librte_eal/ppc/include/rte_prefetch.h | 5 +++++ > lib/librte_eal/x86/include/rte_prefetch.h | 9 +++++++++ > 6 files changed, 45 insertions(+) > > diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst > index df227a1..dc402ab 100644 > --- a/doc/guides/rel_notes/release_20_11.rst > +++ b/doc/guides/rel_notes/release_20_11.rst > @@ -55,6 +55,13 @@ New Features > Also, make sure to start the actual text at the margin. > ======================================================= > > +* **Added new function rte_cldemote in rte_prefetch.h.** > + > + Added a hardware hint CLDEMOTE, which is similar to prefetch in reverse. > + CLDEMOTE moves the cache line to the more remote cache, where it expects > + sharing to be efficient. Moving the cache line to a level more distant from > + the processor helps to accelerate core-to-core communication. > + > > Removed Items > ------------- > diff --git a/lib/librte_eal/arm/include/rte_prefetch_32.h b/lib/librte_eal/arm/include/rte_prefetch_32.h > index e53420a..ad91edd 100644 > --- a/lib/librte_eal/arm/include/rte_prefetch_32.h > +++ b/lib/librte_eal/arm/include/rte_prefetch_32.h > @@ -33,6 +33,11 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) > rte_prefetch0(p); > } > > +static inline void rte_cldemote(const volatile void *p) > +{ > + RTE_SET_USED(p); > +} > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/arm/include/rte_prefetch_64.h b/lib/librte_eal/arm/include/rte_prefetch_64.h > index fc2b391..35d278a 100644 > --- a/lib/librte_eal/arm/include/rte_prefetch_64.h > +++ b/lib/librte_eal/arm/include/rte_prefetch_64.h > @@ -32,6 +32,11 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) > asm volatile ("PRFM PLDL1STRM, [%0]" : : "r" (p)); > } > > +static inline void rte_cldemote(const volatile void *p) > +{ > + RTE_SET_USED(p); > +} ARM64 does not have this support so NOP is fine for this. Acked-by: Jerin Jacob > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h > index 6e47bdf..5500cd5 100644 > --- a/lib/librte_eal/include/generic/rte_prefetch.h > +++ b/lib/librte_eal/include/generic/rte_prefetch.h > @@ -51,4 +51,18 @@ > */ > static inline void rte_prefetch_non_temporal(const volatile void *p); > > +/** > + * Demote a cache line to a more distant level of cache from the processor. > + * > + * CLDEMOTE hints to hardware to move (demote) a cache line from the closest to > + * the processor to a level more distant from the processor. It is a hint and > + * not guarantee. rte_cldemote is intended to move the cache line to the more > + * remote cache, where it expects sharing to be efficient and to indicate that a > + * line may be accessed by a different core in the future. > + * > + * @param p > + * Address to demote > + */ > +static inline void rte_cldemote(const volatile void *p); > + > #endif /* _RTE_PREFETCH_H_ */ > diff --git a/lib/librte_eal/ppc/include/rte_prefetch.h b/lib/librte_eal/ppc/include/rte_prefetch.h > index 9ba07c8..3fe9655 100644 > --- a/lib/librte_eal/ppc/include/rte_prefetch.h > +++ b/lib/librte_eal/ppc/include/rte_prefetch.h > @@ -34,6 +34,11 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) > rte_prefetch0(p); > } > > +static inline void rte_cldemote(const volatile void *p) > +{ > + RTE_SET_USED(p); > +} > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/x86/include/rte_prefetch.h b/lib/librte_eal/x86/include/rte_prefetch.h > index 384c6b3..029d06e 100644 > --- a/lib/librte_eal/x86/include/rte_prefetch.h > +++ b/lib/librte_eal/x86/include/rte_prefetch.h > @@ -32,6 +32,15 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) > asm volatile ("prefetchnta %[p]" : : [p] "m" (*(const volatile char *)p)); > } > > +/* > + * we're using raw byte codes for now as only the newest compiler > + * versions support this instruction natively. > + */ > +static inline void rte_cldemote(const volatile void *p) > +{ > + asm volatile(".byte 0x0f, 0x1c, 0x06" :: "S" (p)); > +} > + > #ifdef __cplusplus > } > #endif > -- > 1.8.3.1 >