From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7471DA00C3; Thu, 20 Jan 2022 09:46:17 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 271FA41C3C; Thu, 20 Jan 2022 09:46:17 +0100 (CET) Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) by mails.dpdk.org (Postfix) with ESMTP id 00FED40042 for ; Thu, 20 Jan 2022 09:46:15 +0100 (CET) Received: by mail-io1-f45.google.com with SMTP id f24so6158082ioc.0 for ; Thu, 20 Jan 2022 00:46:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3pIkqyRURC8EPDDCinuiTAVcTaNG1e/nxYBupk1ihWA=; b=GU+HD4MZujmdFmqdjaeGxpsqYntbvuT8wajZ5UYLCi9WobfHWwAOgSrqSEoxwUvVbU HBNyTTkNgxVfc8+X5zZ1TIUvf65sFVFl9y0k0vVMtz8WSdbmv3iMMfqCCijVRx+Q6uOp x/Yg0V7o4KwRCRUHnuYQvqsX4Xq6f+bdMyClMkXT7wpYRJbDD85zWt4L4euS/Y3oas9B hBlz4VbDHmlefSizRe2z9oICZ7rxOup1h3fv1k4UPRex17xOctt5eOnEdT6CrisYPKlq 6ddZXQbvJbyyf3Kuvip4FqTJLR7LqlhByKTIDQ9w8Y8K5d4E6/s/ae81+OFddLUxwPYr lDBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3pIkqyRURC8EPDDCinuiTAVcTaNG1e/nxYBupk1ihWA=; b=76Ytx6UfAbMfqcTyFJLu9wFuldzh6dgYpFHjtmyxK+kqaG0A3ywTIwwY5+lO8TTYY0 2hpWpDcJjQ8Qk1b4D5A7j2fOmDlQjiGezL5lHbGh6UTRzpEcVHpPaErXRz46VAW8jekd GEhTAATbgmnbCes0582ALIqa2Cgex4C9ns9RMkMXBwoUgTmSvPkLlQnQgd75B/i/GFBE p/2V0cy6MzQjD03dGlEIw89gWh0mz0uVgISpoCcBwzgWv7Qu3+EpQ5QHEJ20MIN1Y9/6 mQnwt6nkAQb1cLUYg2YWOwi/P1EoUbA5PnTKJLUN48nYpctKqs4Zv6TIU/d5jnUKQxRB 9z3A== X-Gm-Message-State: AOAM531FduwPWHAlobpqAhVU4Cpl5Gj30WjYcKo++tc4N3904GE5rwGk 2KvSQG686T1KS5pH9Od8sUrLgHUGkjNpLL2yWWs= X-Google-Smtp-Source: ABdhPJwMaf/YIYMFneftCYpE1LOTBudqExgnideOSv4Fp44VZi75ZMC1+8DI+mRPu5rv2aupeyTMT6t8VpqqJ6y0r+0= X-Received: by 2002:a05:6602:27d1:: with SMTP id l17mr18399969ios.160.1642668375284; Thu, 20 Jan 2022 00:46:15 -0800 (PST) MIME-Version: 1.0 References: <20220113121807.187105-1-hkalra@marvell.com> In-Reply-To: <20220113121807.187105-1-hkalra@marvell.com> From: Jerin Jacob Date: Thu, 20 Jan 2022 14:15:49 +0530 Message-ID: Subject: Re: [PATCH] common/cnxk: enable NIX Tx interrupts errata To: Harman Kalra Cc: dpdk-dev , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, Jan 13, 2022 at 5:48 PM Harman Kalra wrote: > > An errata exists whereby NIX may incorrectly overwrite the value in > NIX_SQ_CTX_S[SQ_INT]. This may cause set interrupts to get cleared or > causing an QINT when no error is outstanding. > As a workaround, software should always read all SQ debug registers > and not just rely on NIX_SQINT_E bits set in NIX_SQ_CTX_S[SQ_INT]. > Also for detecting SQB faults software must read SQ context and > check id next_sqb is NULL. > > Signed-off-by: Harman Kalra Please rebase to next-net-mrvl. Following conflict found in merging. [for-next-net]dell[dpdk-next-net-mrvl] $ git diff diff --cc drivers/common/cnxk/roc_nix_irq.c index 7dcd533ea9,71971ef261..0000000000 --- a/drivers/common/cnxk/roc_nix_irq.c +++ b/drivers/common/cnxk/roc_nix_irq.c @@@ -203,11 -226,12 +226,20 @@@ nix_lf_sq_debug_reg(struct nix *nix, ui reg = plt_read64(nix->base + off); if (reg & BIT_ULL(44)) { ++<<<<<<< HEAD + plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff), + (uint8_t)(reg & 0xff)); + /* Clear valid bit */ + plt_write64(BIT_ULL(44), nix->base + off); + } ++======= + err = reg & 0xff; + /* Clear valid bit */ + plt_write64(BIT_ULL(44), nix->base + off); + } + + return err; ++>>>>>>> common/cnxk: enable NIX Tx interrupts errata } > --- > drivers/common/cnxk/roc_nix_irq.c | 69 ++++++++++++++++++++++--------- > 1 file changed, 50 insertions(+), 19 deletions(-) > > diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c > index a5cd9d4b02..71971ef261 100644 > --- a/drivers/common/cnxk/roc_nix_irq.c > +++ b/drivers/common/cnxk/roc_nix_irq.c > @@ -196,15 +196,42 @@ nix_lf_sq_irq_get_and_clear(struct nix *nix, uint16_t sq) > return nix_lf_q_irq_get_and_clear(nix, sq, NIX_LF_SQ_OP_INT, ~0x1ff00); > } > > -static inline void > +static inline bool > +nix_lf_is_sqb_null(struct dev *dev, int q) > +{ > + bool is_sqb_null = false; > + volatile void *ctx; > + int rc; > + > + rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, &ctx); > + if (rc) { > + plt_err("Failed to get sq context"); > + } else { > + is_sqb_null = > + roc_model_is_cn9k() ? > + (((__io struct nix_sq_ctx_s *)ctx)->next_sqb == > + 0) : > + (((__io struct nix_cn10k_sq_ctx_s *)ctx) > + ->next_sqb == 0); > + } > + > + return is_sqb_null; > +} > + > +static inline uint8_t > nix_lf_sq_debug_reg(struct nix *nix, uint32_t off) > { > + uint8_t err = 0; > uint64_t reg; > > reg = plt_read64(nix->base + off); > - if (reg & BIT_ULL(44)) > - plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff), > - (uint8_t)(reg & 0xff)); > + if (reg & BIT_ULL(44)) { > + err = reg & 0xff; > + /* Clear valid bit */ > + plt_write64(BIT_ULL(44), nix->base + off); > + } > + > + return err; > } > > static void > @@ -226,6 +253,7 @@ nix_lf_q_irq(void *param) > struct dev *dev = &nix->dev; > int q, cq, rq, sq; > uint64_t intr; > + uint8_t rc; > > intr = plt_read64(nix->base + NIX_LF_QINTX_INT(qintx)); > if (intr == 0) > @@ -266,22 +294,25 @@ nix_lf_q_irq(void *param) > sq = q % nix->qints; > irq = nix_lf_sq_irq_get_and_clear(nix, sq); > > - if (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) { > - plt_err("SQ=%d NIX_SQINT_LMT_ERR", sq); > - nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG); > - } > - if (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) { > - plt_err("SQ=%d NIX_SQINT_MNQ_ERR", sq); > - nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG); > - } > - if (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) { > - plt_err("SQ=%d NIX_SQINT_SEND_ERR", sq); > - nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); > - } > - if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) { > + /* Detect LMT store error */ > + rc = nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG); > + if (rc) > + plt_err("SQ=%d NIX_SQINT_LMT_ERR, errcode %x", sq, rc); > + > + /* Detect Meta-descriptor enqueue error */ > + rc = nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG); > + if (rc) > + plt_err("SQ=%d NIX_SQINT_MNQ_ERR, errcode %x", sq, rc); > + > + /* Detect Send error */ > + rc = nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); > + if (rc) > + plt_err("SQ=%d NIX_SQINT_SEND_ERR, errcode %x", sq, rc); > + > + /* Detect SQB fault, read SQ context to check SQB NULL case */ > + if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL) || > + nix_lf_is_sqb_null(dev, q)) > plt_err("SQ=%d NIX_SQINT_SQB_ALLOC_FAIL", sq); > - nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); > - } > } > > /* Clear interrupt */ > -- > 2.18.0 >