Re: [dpdk-dev] [PATCH v2] eal: adjust barriers for IO on Armv8-a

[Jerin Jacob <jerinjacobk@gmail.com>]

On Sun, Jun 28, 2020 at 12:55 AM Honnappa Nagarahalli
<Honnappa.Nagarahalli@arm.com> wrote:
>
> Hi Jerin,
>         You had a comment earlier about deprecating rte_cio_[rw]mb. Let me know if you are ok with this patch and I can add those changes (replace references to rte_cio_[rw]mb with rte_io_[rw]mb and a deprecation notice).

Acked-by: Jerin Jacob <jerinj@marvell.com> for this patch
Please send the deprecation notice for overlapping rte_cio_* for 20.11


>
> Thanks,
> Honnappa
>
> > -----Original Message-----
> > From: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > Sent: Saturday, June 27, 2020 2:12 PM
> > To: dev@dpdk.org; Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>;
> > Ruifeng Wang <Ruifeng.Wang@arm.com>; jerinj@marvell.com;
> > hemant.agrawal@nxp.com; Ajit Khaparde (ajit.khaparde@broadcom.com)
> > <ajit.khaparde@broadcom.com>; igorch@amazon.com;
> > thomas@monjalon.net; viacheslavo@mellanox.com;
> > arybchenko@solarflare.com; bruce.richardson@intel.com
> > Cc: nd <nd@arm.com>
> > Subject: [PATCH v2] eal: adjust barriers for IO on Armv8-a
> >
> > Change the barrier APIs for IO to reflect that Armv8-a is other-multi-copy
> > atomicity memory model.
> >
> > Armv8-a memory model has been strengthened to require other-multi-copy
> > atomicity. This property requires memory accesses from an observer to
> > become visible to all other observers simultaneously [3]. This means
> >
> > a) A write arriving at an endpoint shared between multiple CPUs is
> >    visible to all CPUs
> > b) A write that is visible to all CPUs is also visible to all other
> >    observers in the shareability domain
> >
> > This allows for using cheaper DMB instructions in the place of DSB for devices
> > that are visible to all CPUs (i.e. devices that DPDK caters to).
> >
> > Please refer to [1], [2] and [3] for more information.
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id
> > =22ec71615d824f4f11d38d0e55a88d8956b7e45f
> > [2] https://www.youtube.com/watch?v=i6DayghhA8Q
> > [3] https://www.cl.cam.ac.uk/~pes20/armv8-mca/
> >
> > Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > Tested-by: Ruifeng Wang <ruifeng.wang@arm.com>
> > ---
> >  lib/librte_eal/arm/include/rte_atomic_64.h | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h
> > b/lib/librte_eal/arm/include/rte_atomic_64.h
> > index 7b7099cdc..e42f69edc 100644
> > --- a/lib/librte_eal/arm/include/rte_atomic_64.h
> > +++ b/lib/librte_eal/arm/include/rte_atomic_64.h
> > @@ -1,6 +1,6 @@
> >  /* SPDX-License-Identifier: BSD-3-Clause
> >   * Copyright(c) 2015 Cavium, Inc
> > - * Copyright(c) 2019 Arm Limited
> > + * Copyright(c) 2020 Arm Limited
> >   */
> >
> >  #ifndef _RTE_ATOMIC_ARM64_H_
> > @@ -19,11 +19,11 @@ extern "C" {
> >  #include <rte_compat.h>
> >  #include <rte_debug.h>
> >
> > -#define rte_mb() asm volatile("dsb sy" : : : "memory")
> > +#define rte_mb() asm volatile("dmb osh" : : : "memory")
> >
> > -#define rte_wmb() asm volatile("dsb st" : : : "memory")
> > +#define rte_wmb() asm volatile("dmb oshst" : : : "memory")
> >
> > -#define rte_rmb() asm volatile("dsb ld" : : : "memory")
> > +#define rte_rmb() asm volatile("dmb oshld" : : : "memory")
> >
> >  #define rte_smp_mb() asm volatile("dmb ish" : : : "memory")
> >
> > @@ -37,9 +37,9 @@ extern "C" {
> >
> >  #define rte_io_rmb() rte_rmb()
> >
> > -#define rte_cio_wmb() asm volatile("dmb oshst" : : : "memory")
> > +#define rte_cio_wmb() rte_wmb()
> >
> > -#define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory")
> > +#define rte_cio_rmb() rte_rmb()
> >
> >  /*------------------------ 128 bit atomic operations -------------------------*/
> >
> > --
> > 2.17.1
>