From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 44D5542C58; Thu, 8 Jun 2023 07:38:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 19FD340A84; Thu, 8 Jun 2023 07:38:53 +0200 (CEST) Received: from mail-ua1-f41.google.com (mail-ua1-f41.google.com [209.85.222.41]) by mails.dpdk.org (Postfix) with ESMTP id 2AC2A40042 for ; Thu, 8 Jun 2023 07:38:52 +0200 (CEST) Received: by mail-ua1-f41.google.com with SMTP id a1e0cc1a2514c-78400319b0eso74770241.2 for ; Wed, 07 Jun 2023 22:38:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686202731; x=1688794731; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=SQS8KfKYMFiHja1Ua0zXKxdoi5ORE5k+cVI4xhyDSFc=; b=RrPCu4hphc4Tlc+h6k5TgzX6ygK+d0CiXcS+MGv/TiVg6pZHn7tmJgT59PeLKg+MbU O+nMtK+SFrUL2CsXuP0FGlM+AbzaJ8l+D3pVy4aUSHv/f9Pv1Lm2k9fbUzuhS5dE48BY GdCKPViC3Sjjuoiuw8otnWmGOK+asySmO2NvcY7YHziTMi0F0rCkW1J4bkQVIUUHG3ie xlKfeXVx0ETAf6a2qbp2jv1M81jN4dRa2/Q9ekpSxMpX2pvpHn6O9Xwz/qtfmm+RrSxL niCU1yHIqpVEFKfMCRiCQaaAziGR0g/ZMYlKJeJEAUhFxCScbiOMDx3z19orrlHV9cmd v7wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686202731; x=1688794731; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SQS8KfKYMFiHja1Ua0zXKxdoi5ORE5k+cVI4xhyDSFc=; b=W5WMuWxUDCDy2uQioJZKWTZWOeGMPiikmetmMAJbZEhunYAsCjiOPua04EkBOrxUBl eW511JqR3h8jDIzMOxbC9uwV0P9QJsMr1qiaCrkh+7gCAcf3RHXFv7j047zAay5hYpvY M8ioCI+9/cZMdQPHE4gpOVvAYvifuJDQECHg1uFv+rp2ifu3lMy3QSZfiDGW5iWmlLUm MhnDoPu7fUGdO3dXbKp/Ca9tuAL6jj2aEHYF3eqbcaDl+D60/uFD6Y/BCRUe3Q77molU db29JBY33eSlH+THNTYnor/AqFuAyoQ6CILmyTw+jSfa54WEQ/UHJo596EeWjj9dVu4j HuAw== X-Gm-Message-State: AC+VfDxteN6l9f8ZmsMsi+S9HAxwLUz8hZ4omrIikSuZWxDbBTSWJ5Zn OEibdfGfuxNlBcy8E3mv/oE7xowKaxNdpiKzYWI= X-Google-Smtp-Source: ACHHUZ6lC8ADMYbLEi2ZLaF8Du/rqjlsTWm/uRYeUjUPD0DvEVFCrzEBADD0/XuNlGS7a6YW5OFJihXKdN54E9p3qQY= X-Received: by 2002:a1f:3dcd:0:b0:462:ca4d:2fa5 with SMTP id k196-20020a1f3dcd000000b00462ca4d2fa5mr2036937vka.12.1686202731346; Wed, 07 Jun 2023 22:38:51 -0700 (PDT) MIME-Version: 1.0 References: <20230607210050.107944-1-abdullah.sevincer@intel.com> In-Reply-To: <20230607210050.107944-1-abdullah.sevincer@intel.com> From: Jerin Jacob Date: Thu, 8 Jun 2023 11:08:25 +0530 Message-ID: Subject: Re: [PATCH v1] event/dlb2: add support for disabling PASID To: Abdullah Sevincer , Gaetan Rivet , David Marchand , Thomas Monjalon Cc: dev@dpdk.org, jerinj@marvell.com, mike.ximing.chen@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, Jun 8, 2023 at 2:31=E2=80=AFAM Abdullah Sevincer wrote: > > vfio-pci driver in Linux kernel 6.2 enables PASID by default. > In DLB hardware, enabling PASID puts DLB in SIOV mode. This > breaks DLB PF-PMD mode. For DLB PF-PMD mode to function properly > PASID needs to be disabled for kernel 6.2. > > In this commit this issue is addressed and PASID is disabled > by writing a zero to PASID control register. > > Signed-off-by: Abdullah Sevincer > + /* The current Linux kernel vfio driver does not expose PASID cap= ability to > + * users. It also enables PASID by default, which breaks DLB PF P= MD. We have > + * to use the hardcoded offset for now to disable PASID. > + */ > + pasid_cap_offset =3D DLB2_PCI_PASID_CAP_OFFSET; > + > + off =3D pasid_cap_offset + DLB2_PCI_PASID_CTRL; +++ additional folks. Is make sense to move this helper function to PCI common for disabling PASID for a PCI device so that other driver can use if needed as the implementation is not specific to DLB2. > + if (rte_pci_read_config(pdev, &pasid_ctrl, 2, off) !=3D 2) > + pasid_ctrl =3D 0; > + > + if (pasid_ctrl) { > + DLB2_INFO(dlb2_dev, "DLB2 disabling pasid...\n"); > + > + pasid_ctrl =3D 0; > + ret =3D rte_pci_write_config(pdev, &pasid_ctrl, 2, off); > + if (ret !=3D 2) { > + DLB2_LOG_ERR("[%s()] failed to write the pcie con= fig space at offset %d\n", > + __func__, (int)off); > + return ret; > + } > + } > + > return 0; > } > > -- > 2.25.1 >