From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C6924A0543; Mon, 13 Jun 2022 10:23:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9E34540150; Mon, 13 Jun 2022 10:23:44 +0200 (CEST) Received: from mail-qk1-f179.google.com (mail-qk1-f179.google.com [209.85.222.179]) by mails.dpdk.org (Postfix) with ESMTP id 0D962400EF for ; Mon, 13 Jun 2022 10:23:43 +0200 (CEST) Received: by mail-qk1-f179.google.com with SMTP id d128so3505841qkg.8 for ; Mon, 13 Jun 2022 01:23:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cHQ4Z/QnB8fDGvaFhVFV8/N+ImCaBdFPq44gFN69/Ds=; b=PYhDeKYtMxuACbS5r1H3W9SEoXhlBzM/QCU1eJczWZY0R7nAu7T8TvEIebpJtbSAHw 6fhKxEd164ZqgnW6R29pZmu1t99+eTWHaBUea0TvPsmXdQN1qoxXBKRymkJ2ZPjN4kLW HGSD3gVwmRhP0m6oIE10s+RaOICwvXIFPTwDh2C5HYaBmEloY0RouhD17Y7bnwHsy/8X rk+XwYdCmMX11qMiUwhogsAxoowUNWzuF9PfjuzMNS7yvaae0uKEYR/MLVFF2oEUo1Cg 1aEj0MFwITu/0p2GF7jufzfCZopJQNRuNSKX5oNuwFks65aW+xgbMFWbYCeKSHOYJFEb epRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cHQ4Z/QnB8fDGvaFhVFV8/N+ImCaBdFPq44gFN69/Ds=; b=fxEbV6RBKK/cbMkYHcwO/+S/7BmE81ZOtBnvauumBhNS+B6t+hBkdtGcbQM6xwNyd4 xyDNCuy/w9E6LxlvcnVmV0WCLDXEE/sYC2AtOqiTq/FgK57AUojCGzAtIcJtQXXifI2d jzqkaKhQrPDWLQOuaDV57vdMQU9PkXs04fPeO+GMzSphHQNkH2RWtQDKhwNPCNmkUg1t KUaL7MRIxRCnpIMJzEumANHBp1dPqX6dyzpxzfIBbAqTI3z0MDM7Kofv321g5P+koCa2 6PPLKRxpH4Lz3hsXf9DzEvmGjvWIQBrwpbwkKgoFMVrjY5Hfd8jN69wQIWf98UiT2Bpo g1pw== X-Gm-Message-State: AOAM533PUZp8HX90HM582dhGmAaNzZfPclMuqcUn7xQIjxfH5WNjdzhv c39Py8Swfaa/juhd6rQjCCS00o7Vt1HhasW/Mn9BEShWogk= X-Google-Smtp-Source: ABdhPJxLLriH4iS1qC0OkF5YOFRnEw4OPmYDdAMXR3MHqvCPJBb8EiUlsxOhxZYFXb4q8q2PsKWXDNNk5TcC4tBk3iM= X-Received: by 2002:a05:620a:84b:b0:6a7:903c:ce7a with SMTP id u11-20020a05620a084b00b006a7903cce7amr2455143qku.402.1655108622450; Mon, 13 Jun 2022 01:23:42 -0700 (PDT) MIME-Version: 1.0 References: <20220412174224.13143-1-syalavarthi@marvell.com> <20220516172656.22333-1-syalavarthi@marvell.com> In-Reply-To: <20220516172656.22333-1-syalavarthi@marvell.com> From: Jerin Jacob Date: Mon, 13 Jun 2022 13:53:16 +0530 Message-ID: Subject: Re: [PATCH v2 1/1] common/cnxk: added new macros to platform layer To: Srikanth Yalavarthi Cc: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , dpdk-dev , Jerin Jacob , sshankarnara@marvell.com Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Mon, May 16, 2022 at 10:57 PM Srikanth Yalavarthi wrote: > > Added new platform layer macros for pointer operations, > bitwise operations, spinlocks and 32 bit read and write. > > Signed-off-by: Srikanth Yalavarthi Acked-by: Jerin Jacob Applied to dpdk-next-net-mrvl/for-next-net. Thanks > --- > drivers/common/cnxk/roc_platform.h | 26 ++++++++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) > > diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h > index 86987aea3b..1ad3c16705 100644 > --- a/drivers/common/cnxk/roc_platform.h > +++ b/drivers/common/cnxk/roc_platform.h > @@ -41,6 +41,7 @@ > #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE > #define PLT_STD_C11 RTE_STD_C11 > #define PLT_PTR_ADD RTE_PTR_ADD > +#define PLT_PTR_SUB RTE_PTR_SUB > #define PLT_PTR_DIFF RTE_PTR_DIFF > #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID > #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET > @@ -70,6 +71,10 @@ > #define PLT_U32_CAST(val) ((uint32_t)(val)) > #define PLT_U16_CAST(val) ((uint16_t)(val)) > > +/* Add / Sub pointer with scalar and cast to uint64_t */ > +#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x)) > +#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x)) > + > /** Divide ceil */ > #define PLT_DIV_CEIL(x, y) \ > ({ \ > @@ -113,10 +118,11 @@ > #define plt_bitmap_scan rte_bitmap_scan > #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint > > -#define plt_spinlock_t rte_spinlock_t > -#define plt_spinlock_init rte_spinlock_init > -#define plt_spinlock_lock rte_spinlock_lock > -#define plt_spinlock_unlock rte_spinlock_unlock > +#define plt_spinlock_t rte_spinlock_t > +#define plt_spinlock_init rte_spinlock_init > +#define plt_spinlock_lock rte_spinlock_lock > +#define plt_spinlock_unlock rte_spinlock_unlock > +#define plt_spinlock_trylock rte_spinlock_trylock > > #define plt_intr_callback_register rte_intr_callback_register > #define plt_intr_callback_unregister rte_intr_callback_unregister > @@ -165,12 +171,24 @@ > #define plt_write64(val, addr) \ > rte_write64_relaxed((val), (volatile void *)(addr)) > > +#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr)) > +#define plt_write32(val, addr) \ > + rte_write32_relaxed((val), (volatile void *)(addr)) > + > #define plt_wmb() rte_wmb() > #define plt_rmb() rte_rmb() > #define plt_io_wmb() rte_io_wmb() > #define plt_io_rmb() rte_io_rmb() > #define plt_atomic_thread_fence rte_atomic_thread_fence > > +#define plt_bit_relaxed_get32 rte_bit_relaxed_get32 > +#define plt_bit_relaxed_set32 rte_bit_relaxed_set32 > +#define plt_bit_relaxed_clear32 rte_bit_relaxed_clear32 > + > +#define plt_bit_relaxed_get64 rte_bit_relaxed_get64 > +#define plt_bit_relaxed_set64 rte_bit_relaxed_set64 > +#define plt_bit_relaxed_clear64 rte_bit_relaxed_clear64 > + > #define plt_mmap mmap > #define PLT_PROT_READ PROT_READ > #define PLT_PROT_WRITE PROT_WRITE > -- > 2.17.1 >