From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53EDEA0563; Tue, 10 Mar 2020 10:03:35 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 564791C00E; Tue, 10 Mar 2020 10:03:34 +0100 (CET) Received: from mail-il1-f194.google.com (mail-il1-f194.google.com [209.85.166.194]) by dpdk.org (Postfix) with ESMTP id 48B211C000 for ; Tue, 10 Mar 2020 10:03:32 +0100 (CET) Received: by mail-il1-f194.google.com with SMTP id c8so10914953ilm.1 for ; Tue, 10 Mar 2020 02:03:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1O+idw79WvhwSWot32bm1+bG8+eyuc/3x+gKjJYIzio=; b=KoiNP/MtYPpeD1Zlq/YC7uiEwtQLSRZFNwrvigJl0vjLWJ0KhL5kRbui+6hFF8ULl1 i1DgK48U+4LapKHjIoi52u9aldlHD+oWQoTj3A0WBLvy8JSz8v+onPp/dksbwzwWYEuB Pkl+2T/OKja1iGxj23OSM02NSCdX+LPVXcfKGFzctIL65N8YV79ieW7WoirbAt58ELuW r+O6wUQke9OMXbHuRhU1IPuAOB1zZlXS9DeoozwKp21XTPPc7RGcKiR0lCgBS9Pt8pfj TxvuHF/Slm/VFFNbZUtIefQYdkHhDKSr8aw7c1rHLSiEsfPO6+pciQ485EG0K3vWVlgA ZcKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1O+idw79WvhwSWot32bm1+bG8+eyuc/3x+gKjJYIzio=; b=Yb3Bkf/nd6OVFIuEUtZt/TWuF3ak95nhPsj15lApaKEIXtBU7wLfcpOwladB1K7aW0 6nBYduqD6QhY/QKB4KfnYtfdX0AhfQIaBAiZiNxtfY5Q/uM6iRbMwsOWL5jhTKIRonRO /DnzGcNnYNMdTfmvro/UA0EF8x+vzY0XiB9pyUz2aI6kTRE4s2LZOTc+OMDrqqPXYopf azQL3O+d61fZ9LaTEeNZTwR7zfQb6puowE6Iz3yQ842XWTyBlvev4ziHlNlNugp/oxz/ 8/BRXQSF8+RCWGwHMRmqGaQkgLlHCjCfwsGSVfplVEYNcvIRdkQM7BdK9LXJF0SwJvyu RsuA== X-Gm-Message-State: ANhLgQ2fZYxR/dFST3lPv9Jz0+XnXTFefdrRid3xUUhwJQgDdM/G6kDI nWN7KE2NCYS75x7U15AMFjpGW3EpA5na4zeRMDY= X-Google-Smtp-Source: ADFU+vtb4/7ZWRJhdd/MAVlaZipyPdZDIwu+gT0CZqwWLHysVXGtxAFf7TjnZiZZshHKsINEpkmDwWODk1frLfwSyD8= X-Received: by 2002:a92:cd0e:: with SMTP id z14mr3587744iln.294.1583831011369; Tue, 10 Mar 2020 02:03:31 -0700 (PDT) MIME-Version: 1.0 References: <4099DE2E54AFAD489356C6C9161D53339729F575@DGGEML502-MBX.china.huawei.com> In-Reply-To: <4099DE2E54AFAD489356C6C9161D53339729F575@DGGEML502-MBX.china.huawei.com> From: Jerin Jacob Date: Tue, 10 Mar 2020 14:33:15 +0530 Message-ID: To: Linhaifeng Cc: Gavin Hu , "dev@dpdk.org" , "thomas@monjalon.net" , chenchanghu , xudingke , "Lilijun (Jerry)" , Honnappa Nagarahalli , Steve Capper , nd Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2] cycles: add isb before read cntvct_el0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Mar 10, 2020 at 1:39 PM Linhaifeng wrote: Please change the subject to more meaningful one: Something like, eal/arm64: fix rdtsc precise version > We should use isb rather than dsb to sync system counter to cntvct_el0. Please tell "why" in commit message, something like this In order to get more accurate the cntvct_el0 reading, SW must invoke ..... Add Fixes: as well. # Make sure it is passing ./devtools/checkpatches.sh and ./devtools/check-git-log.sh > > Reference of linux kernel: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/asm/arch_timer.h?h=v5.5#n220 > > Signed-off-by: Haifeng Lin > --- > .../common/include/arch/arm/rte_atomic_64.h | 3 +++ > .../common/include/arch/arm/rte_cycles_64.h | 20 +++++++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > index 859ae129d..2587f98a2 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > @@ -21,6 +21,7 @@ extern "C" { > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") > #define dmb(opt) asm volatile("dmb " #opt : : : "memory") > +#define isb() (asm volatile("isb" : : : "memory")) > > #define rte_mb() dsb(sy) > > @@ -44,6 +45,8 @@ extern "C" { > > #define rte_cio_rmb() dmb(oshld) > > +#define rte_isb() isb() As David said, Don't add rte_ public symbols from header files. > + > /*------------------------ 128 bit atomic operations -------------------------*/ > > #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS) > diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > index 68e7c7338..bc4e3f8e6 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > @@ -18,6 +18,7 @@ extern "C" { > * The time base for this lcore. > */ > #ifndef RTE_ARM_EAL_RDTSC_USE_PMU > + > /** > * This call is portable to any ARMv8 architecture, however, typically > * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks. > @@ -59,11 +60,26 @@ rte_rdtsc(void) > } > #endif > > +#define arch_counter_enforce_ordering(val) do { \ > + uint64_t tmp, _val = (val); \ > + \ > + asm volatile( \ > + " eor %0, %1, %1\n" \ > + " add %0, sp, %0\n" \ > + " ldr xzr, [%0]" \ > + : "=r" (tmp) : "r" (_val)); \ > +} while (0) Please use static inline function and change the name to __rte_arm64_cntvct_el0_enforce_ordering() or so > + > static inline uint64_t > rte_rdtsc_precise(void) > { > - rte_mb(); > - return rte_rdtsc(); > + uint64_t tsc; > + > + rte_isb(); No need for new marco, If you think, it is needed make it as __rte_arm64_isb() or so > + tsc = rte_rdtsc(); > + arch_counter_enforce_ordering(tsc); > + return tsc; > } > > static inline uint64_t > -- > 2.24.1.windows.2