From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7ACF7440E7; Mon, 27 May 2024 17:24:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 36992402D4; Mon, 27 May 2024 17:24:11 +0200 (CEST) Received: from mail-qt1-f172.google.com (mail-qt1-f172.google.com [209.85.160.172]) by mails.dpdk.org (Postfix) with ESMTP id 3ED31402C5 for ; Mon, 27 May 2024 17:24:10 +0200 (CEST) Received: by mail-qt1-f172.google.com with SMTP id d75a77b69052e-43fc7623afaso7260041cf.3 for ; Mon, 27 May 2024 08:24:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716823449; x=1717428249; darn=dpdk.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ydGI8NlgyBi2w5HWw5lKNix2dFnPM2cUltQU9SSbbMk=; b=KCyW3nAuiKuqFbHgBDjHkqytrTSJcxEdz71d9adPrA3cEiLxS6dSV6d4N/LmcG6Krr B8dRumqB6Tw/E6i10abB71XAk2V0glkoTC/M/Fyd86wGxmrtztof2xNgztThQ4aFGNyB 7+6nsZ2YqMJI4/uY/YVr1IuTm8UHTmLMiWzYoqHCZX7lQ8uqK3ONantYke27ohQAPaLl OH1Dhtm3Tn7ANhhOa16UWG2ApKNZXYkCMFuGegOBaiFkNdXst5TLf4Uwjfe7j9YdoLYn 8SXSWPORv5m7kFu64xwlzfutP5FBxB3vV8agM9ihn+ZwO1NDZa2vEfsGyjDzZLyt+kQ5 N8Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716823449; x=1717428249; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ydGI8NlgyBi2w5HWw5lKNix2dFnPM2cUltQU9SSbbMk=; b=B8fUt++XkcUeE61GbBpIQO0xWCW8scneC1en1vyHrxWZfuRauXZ42/yA0AEFrv3yVS ddGl7B43Kj3E4lI9TnSzErFj8+GuZ2fmHlYDIaLjkb+nYwQj3QBSldAnTUcqkb+VfuUg C4nXsvNDXRS7RGw6bkmUnd5dEme5PJzo1ujkClV4CX68hUrEMcwHhLbbnc58OxhpJ77W eFhqKbqq5xDXW54OQfavv4Xj5IqOEjTKLckRL6rOi02aT6yFJJhvmgvkxM7yXrGlUE87 s74gbsznS2MOkkDjy2aRUPb/uuyoy3NTt48ahtMv/g6ZDO1J7Jn486kAHKElTpl8ou06 Pgmg== X-Gm-Message-State: AOJu0YzXzxGvDpDXGkvTIqe7RmKWlG3s6UomWdB87Pr/XHdws7hU6moC zVd2W39KRSYsthqNhQIXTGsbt9nYRWh3LAqPqGUChBHJyxRvsxnYHcCDU/qZ7HQN/fNSlrf5+G/ 9j9sNyC+t10BZWW8O2C9TJDpE7cY= X-Google-Smtp-Source: AGHT+IG75RA9EAuZNxofq2fNY3YeZifdq8odMiwE/+Kby816zXM8SL+cM/a8ej00g8+1ZCBzHQiFAd+/FxEzswwqQbM= X-Received: by 2002:a05:622a:1306:b0:43a:b207:907 with SMTP id d75a77b69052e-43fb0e5480fmr113060851cf.16.1716823449247; Mon, 27 May 2024 08:24:09 -0700 (PDT) MIME-Version: 1.0 References: <20240501194620.1199357-1-abdullah.sevincer@intel.com> <20240501194620.1199357-3-abdullah.sevincer@intel.com> In-Reply-To: <20240501194620.1199357-3-abdullah.sevincer@intel.com> From: Jerin Jacob Date: Mon, 27 May 2024 20:53:42 +0530 Message-ID: Subject: Re: [PATCH v4 2/3] event/dlb2: add support for dynamic HL entries To: Abdullah Sevincer Cc: dev@dpdk.org, jerinj@marvell.com, mike.ximing.chen@intel.com, tirthendu.sarkar@intel.com, pravin.pathak@intel.com, shivani.doneria@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, May 2, 2024 at 1:16=E2=80=AFAM Abdullah Sevincer wrote: > > In DLB 2.5, hardware assist is available, complementing the Delayed > token POP software implementation. When it is enabled, the feature > works as follows: > > It stops CQ scheduling when the inflight limit associated with the CQ > is reached. So the feature is activated only if the core is > congested. If the core can handle multiple atomic flows, DLB will not > try to switch them. This is an improvement over SW implementation > which always switches the flows. > > The feature will resume CQ scheduling when the number of pending > completions fall below a configured threshold. > > DLB has 64 LDB ports and 2048 HL entries. If all LDB ports are used, > possible HL entries per LDB port equals 2048 / 64 =3D 32. So, the > maximum CQ depth possible is 16, if all 64 LB ports are needed in a > high-performance setting. > > In case all CQs are configured to have HL =3D 2* CQ Depth as a > performance option, then the calculation of HL at the time of domain > creation will be based on maximum possible dequeue depth. This could > result in allocating too many HL entries to the domain as DLB only > has limited number of HL entries to be allocated. Hence, it is best > to allow application to specify HL entries as a command line argument > and override default allocation. A summary of usage is listed below: > > When 'use_default_hl =3D 1', Per port HL is set to > DLB2_FIXED_CQ_HL_SIZE (32) and command line parameter > alloc_hl_entries is ignored. > > When 'use_default_hl =3D 0', Per LDB port HL =3D 2 * CQ depth and per > port HL is set to 2 * DLB2_FIXED_CQ_HL_SIZE. > > User should calculate needed HL entries based on CQ depths the > application will use and specify it as command line parameter > 'alloc_hl_entries'. This will be used to allocate HL entries. > Hence, alloc_hl_entries =3D (Sum of all LDB ports CQ depths * 2). > > If alloc_hl_entries is not specified, then Total HL entries for the > vdev =3D num_ldb_ports * 64. > > Signed-off-by: Abdullah Sevincer > } > diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_pri= v.h > index d6828aa482..dc9f98e142 100644 > --- a/drivers/event/dlb2/dlb2_priv.h > +++ b/drivers/event/dlb2/dlb2_priv.h > @@ -52,6 +52,8 @@ > #define DLB2_PRODUCER_COREMASK "producer_coremask" > #define DLB2_DEFAULT_LDB_PORT_ALLOCATION_ARG "default_port_allocation" > #define DLB2_ENABLE_CQ_WEIGHT_ARG "enable_cq_weight" > +#define DLB2_USE_DEFAULT_HL "use_default_hl" > +#define DLB2_ALLOC_HL_ENTRIES "alloc_hl_entries" 1)Update doc/guides/eventdevs/dlb2.rst for new devargs 2)Please release note PMD section for this feature.