From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A3345A00C4; Sun, 24 Apr 2022 05:54:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4918740042; Sun, 24 Apr 2022 05:54:53 +0200 (CEST) Received: from mail-io1-f51.google.com (mail-io1-f51.google.com [209.85.166.51]) by mails.dpdk.org (Postfix) with ESMTP id 112C24003F for ; Sun, 24 Apr 2022 05:54:52 +0200 (CEST) Received: by mail-io1-f51.google.com with SMTP id n134so12567599iod.5 for ; Sat, 23 Apr 2022 20:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=fAouNKF2wGibvMQLM0D+8MVMdtGGJ05Xo1AHvAJl7Ig=; b=LexSrEh/4x/SDp/0S7aI+dBDPBvWdsKYM5CdtZQpJvanz57THrgyCaWQI3bZBkv4rh 7ajQlHja+/ABooL1QS1xLpSSaAKXQ1huao31MPzuoz33aXJZeq6Ax0p4kRTsmUUL6yPI rzFIyidMtLv3dkojcqygab0jwfDJTzyc9IwMJV7oyuV1lk3SALS0t2C+vuEjot/uy1O1 uJwyWtdGbuKNDXY8s3J9O4N4yq930dZwJjux+Ahf+Vw0UUusMCMgLvTCzK6NvAJTNif1 +TY9/GzmYHKPEveibjLMRn5rSsx4TH6PNoMAPa/Yxt0oVdNl/7w9iJIVnBesScI5+68O WRCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fAouNKF2wGibvMQLM0D+8MVMdtGGJ05Xo1AHvAJl7Ig=; b=dsjDekyZTq4vFg/yBNz54arWCX3my0LXkSW4jctc+3lFjbdvUwZuEG5/LUDKQTAGZD ZreWDJ4217M43Raax7ycnm8Ix9Y85yHc2qa6+Hq/oJ0dD4XGevebqlRUJeBG3hcmHOzw iA6GU8AcPNjCH9HrP8ZjO4DytuWsxNofxX2LuabwofIrKoDvDbm9xsDeXOfkw5FzjtAj yXY0fJGjQFyqigXsTF/rw2YW7NCIDHPQYr5iKQYl62liihIakcQvpJR3MJdPwQWEg9Qi UVU2TURbKn0XXH/hzuChbZZYQ20VpP207BmB92uLh+H1HCfWJWqBMZVyz1VP8wTjLI5u fUqw== X-Gm-Message-State: AOAM532a9yAAfAaUmq/yqYl5X+auqfr/Wj+DLTLMA9IXCn6c+MSRzJpZ eYX8g8VVnO7hEgdxz08hQAp8KTFihpdYK3AJO2Q= X-Google-Smtp-Source: ABdhPJwtsObK/XB9LPwfz+dPEc004JR2mQdjYT5RVTB2j9b7q9/aJQSKcFHlwePxNKjlb920AnLxtYcGF7rLvxLieDw= X-Received: by 2002:a05:6638:8d:b0:32a:e5c0:54d5 with SMTP id v13-20020a056638008d00b0032ae5c054d5mr509231jao.158.1650772491251; Sat, 23 Apr 2022 20:54:51 -0700 (PDT) MIME-Version: 1.0 References: <20220228045322.1841812-1-psatheesh@marvell.com> In-Reply-To: <20220228045322.1841812-1-psatheesh@marvell.com> From: Jerin Jacob Date: Sun, 24 Apr 2022 09:24:25 +0530 Message-ID: Subject: Re: [dpdk-dev] [PATCH 1/2] common/cnxk: support for CPT second pass flow rules To: Satheesh Paul , ferruh.yigit@xilinx.com, Andrew Rybchenko Cc: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , dpdk-dev Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Mon, Feb 28, 2022 at 10:23 AM wrote: > > From: Satheesh Paul > > Added support to create flow rules to match packets > from CPT(second pass packets). With this change, ingress > rules will be created with bits 10 and 11 of channel field > in the MCAM ignored by default. For rules specific to > second pass packets, the CPT channel bits will be set > in the MCAM. > > Signed-off-by: Satheesh Paul Series Acked-by: Jerin Jacob Series applied to dpdk-next-net-mrvl/for-next-net. Thanks. > --- > drivers/common/cnxk/hw/nix.h | 7 +++- > drivers/common/cnxk/roc_npc.c | 9 +++-- > drivers/common/cnxk/roc_npc.h | 1 + > drivers/common/cnxk/roc_npc_mcam.c | 60 ++++++++++++++++++++--------- > drivers/common/cnxk/roc_npc_parse.c | 14 +++++++ > drivers/common/cnxk/roc_npc_priv.h | 2 + > 6 files changed, 69 insertions(+), 24 deletions(-) > > diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h > index 1cc0c8dfb8..5863e358e0 100644 > --- a/drivers/common/cnxk/hw/nix.h > +++ b/drivers/common/cnxk/hw/nix.h > @@ -830,7 +830,7 @@ > #define NIX_CHAN_LBKX_CHX(a, b) \ > (0x000ull | ((uint64_t)(a) << 8) | (uint64_t)(b)) > #define NIX_CHAN_CPT_CH_END (0x4ffull) /* [CN10K, .) */ > -#define NIX_CHAN_CPT_CH_START (0x400ull) /* [CN10K, .) */ > +#define NIX_CHAN_CPT_CH_START (0x800ull) /* [CN10K, .) */ > #define NIX_CHAN_R4 (0x400ull) /* [CN9K, CN10K) */ > #define NIX_CHAN_R5 (0x500ull) > #define NIX_CHAN_R6 (0x600ull) > @@ -843,6 +843,11 @@ > #define NIX_CHAN_RPMX_LMACX_CHX(a, b, c) \ > (0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | (uint64_t)(c)) > > +/* The mask is to extract lower 10-bits of channel number > + * which CPT will pass to X2P. > + */ > +#define NIX_CHAN_CPT_X2P_MASK (0x3ffull) > + > #define NIX_INTF_SDP (0x4ull) > #define NIX_INTF_CGX0 (0x0ull) /* [CN9K, CN10K) */ > #define NIX_INTF_CGX1 (0x1ull) /* [CN9K, CN10K) */ > diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c > index fc88fd58bc..51e36f141f 100644 > --- a/drivers/common/cnxk/roc_npc.c > +++ b/drivers/common/cnxk/roc_npc.c > @@ -570,10 +570,11 @@ npc_parse_pattern(struct npc *npc, const struct roc_npc_item_info pattern[], > struct roc_npc_flow *flow, struct npc_parse_state *pst) > { > npc_parse_stage_func_t parse_stage_funcs[] = { > - npc_parse_meta_items, npc_parse_pre_l2, npc_parse_cpt_hdr, > - npc_parse_higig2_hdr, npc_parse_la, npc_parse_lb, > - npc_parse_lc, npc_parse_ld, npc_parse_le, > - npc_parse_lf, npc_parse_lg, npc_parse_lh, > + npc_parse_meta_items, npc_parse_mark_item, npc_parse_pre_l2, > + npc_parse_cpt_hdr, npc_parse_higig2_hdr, npc_parse_la, > + npc_parse_lb, npc_parse_lc, npc_parse_ld, > + npc_parse_le, npc_parse_lf, npc_parse_lg, > + npc_parse_lh, > }; > uint8_t layer = 0; > int key_offset; > diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h > index 6204139396..aecea37b3d 100644 > --- a/drivers/common/cnxk/roc_npc.h > +++ b/drivers/common/cnxk/roc_npc.h > @@ -37,6 +37,7 @@ enum roc_npc_item_type { > ROC_NPC_ITEM_TYPE_L3_CUSTOM, > ROC_NPC_ITEM_TYPE_QINQ, > ROC_NPC_ITEM_TYPE_RAW, > + ROC_NPC_ITEM_TYPE_MARK, > ROC_NPC_ITEM_TYPE_END, > }; > > diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c > index 9c5ff5e60a..3447b59344 100644 > --- a/drivers/common/cnxk/roc_npc_mcam.c > +++ b/drivers/common/cnxk/roc_npc_mcam.c > @@ -497,6 +497,38 @@ npc_mcam_fetch_kex_cfg(struct npc *npc) > return rc; > } > > +static void > +npc_mcam_set_channel(struct roc_npc_flow *flow, > + struct npc_mcam_write_entry_req *req, uint16_t channel, > + uint16_t chan_mask, bool is_second_pass) > +{ > + uint16_t chan = 0, mask = 0; > + > + req->entry_data.kw[0] &= ~(GENMASK(11, 0)); > + req->entry_data.kw_mask[0] &= ~(GENMASK(11, 0)); > + flow->mcam_data[0] &= ~(GENMASK(11, 0)); > + flow->mcam_mask[0] &= ~(GENMASK(11, 0)); > + > + if (is_second_pass) { > + chan = (channel | NIX_CHAN_CPT_CH_START); > + mask = (chan_mask | NIX_CHAN_CPT_CH_START); > + } else { > + /* > + * Clear bits 10 & 11 corresponding to CPT > + * channel. By default, rules should match > + * both first pass packets and second pass > + * packets from CPT. > + */ > + chan = (channel & NIX_CHAN_CPT_X2P_MASK); > + mask = (chan_mask & NIX_CHAN_CPT_X2P_MASK); > + } > + > + req->entry_data.kw[0] |= (uint64_t)chan; > + req->entry_data.kw_mask[0] |= (uint64_t)mask; > + flow->mcam_data[0] |= (uint64_t)chan; > + flow->mcam_mask[0] |= (uint64_t)mask; > +} > + > int > npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, > struct npc_parse_state *pst) > @@ -564,32 +596,22 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, > if (flow->nix_intf == NIX_INTF_RX) { > if (inl_dev && inl_dev->is_multi_channel && > (flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) { > - req->entry_data.kw[0] |= (uint64_t)inl_dev->channel; > - req->entry_data.kw_mask[0] |= > - (uint64_t)inl_dev->chan_mask; > pf_func = nix_inl_dev_pffunc_get(); > req->entry_data.action &= ~(GENMASK(19, 4)); > req->entry_data.action |= (uint64_t)pf_func << 4; > - > flow->npc_action &= ~(GENMASK(19, 4)); > flow->npc_action |= (uint64_t)pf_func << 4; > - flow->mcam_data[0] |= (uint64_t)inl_dev->channel; > - flow->mcam_mask[0] |= (uint64_t)inl_dev->chan_mask; > + > + npc_mcam_set_channel(flow, req, inl_dev->channel, > + inl_dev->chan_mask, false); > } else if (npc->is_sdp_link) { > - req->entry_data.kw[0] &= ~(GENMASK(11, 0)); > - req->entry_data.kw_mask[0] &= ~(GENMASK(11, 0)); > - req->entry_data.kw[0] |= (uint64_t)npc->sdp_channel; > - req->entry_data.kw_mask[0] |= > - (uint64_t)npc->sdp_channel_mask; > - flow->mcam_data[0] &= ~(GENMASK(11, 0)); > - flow->mcam_mask[0] &= ~(GENMASK(11, 0)); > - flow->mcam_data[0] |= (uint64_t)npc->sdp_channel; > - flow->mcam_mask[0] |= (uint64_t)npc->sdp_channel_mask; > + npc_mcam_set_channel(flow, req, npc->sdp_channel, > + npc->sdp_channel_mask, > + pst->is_second_pass_rule); > } else { > - req->entry_data.kw[0] |= (uint64_t)npc->channel; > - req->entry_data.kw_mask[0] |= (BIT_ULL(12) - 1); > - flow->mcam_data[0] |= (uint64_t)npc->channel; > - flow->mcam_mask[0] |= (BIT_ULL(12) - 1); > + npc_mcam_set_channel(flow, req, npc->channel, > + (BIT_ULL(12) - 1), > + pst->is_second_pass_rule); > } > } else { > uint16_t pf_func = (flow->npc_action >> 4) & 0xffff; > diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c > index b849326a19..364a846963 100644 > --- a/drivers/common/cnxk/roc_npc_parse.c > +++ b/drivers/common/cnxk/roc_npc_parse.c > @@ -21,6 +21,20 @@ npc_parse_meta_items(struct npc_parse_state *pst) > return 0; > } > > +int > +npc_parse_mark_item(struct npc_parse_state *pst) > +{ > + if (pst->pattern->type == ROC_NPC_ITEM_TYPE_MARK) { > + if (pst->flow->nix_intf != NIX_INTF_RX) > + return -EINVAL; > + > + pst->is_second_pass_rule = true; > + pst->pattern++; > + } > + > + return 0; > +} > + > static int > npc_flow_raw_item_prepare(const struct roc_npc_flow_item_raw *raw_spec, > const struct roc_npc_flow_item_raw *raw_mask, > diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h > index e78d96e876..78d6ee844d 100644 > --- a/drivers/common/cnxk/roc_npc_priv.h > +++ b/drivers/common/cnxk/roc_npc_priv.h > @@ -189,6 +189,7 @@ struct npc_parse_state { > /* adjust ltype in MCAM to match at least one vlan */ > bool set_vlan_ltype_mask; > bool set_ipv6ext_ltype_mask; > + bool is_second_pass_rule; > }; > > enum npc_kpu_parser_flag { > @@ -421,6 +422,7 @@ void npc_get_hw_supp_mask(struct npc_parse_state *pst, > int npc_parse_item_basic(const struct roc_npc_item_info *item, > struct npc_parse_item_info *info); > int npc_parse_meta_items(struct npc_parse_state *pst); > +int npc_parse_mark_item(struct npc_parse_state *pst); > int npc_parse_pre_l2(struct npc_parse_state *pst); > int npc_parse_higig2_hdr(struct npc_parse_state *pst); > int npc_parse_cpt_hdr(struct npc_parse_state *pst); > -- > 2.25.4 >