From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7C4AA0350; Thu, 25 Jun 2020 17:33:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 803904F9C; Thu, 25 Jun 2020 17:33:44 +0200 (CEST) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by dpdk.org (Postfix) with ESMTP id CE281F04 for ; Thu, 25 Jun 2020 17:33:43 +0200 (CEST) Received: by mail-io1-f65.google.com with SMTP id i4so6470666iov.11 for ; Thu, 25 Jun 2020 08:33:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CWu8R92IkSi+xmhEXxL3D1J4YCsbUoX2//ne51V4bvk=; b=hNSq+Vsl6Paj0D9Dzt/O4PnCw4ulRXlw0BuIX8D0038NvbXFG4puX0MVclvEyEp9px 3bEYNb+oDgHIpJeTYckE5vXzAO35RqQwNpYzUbI7Ypwm9SrmBWY6bvRgIyyexE0kAuEI OhB2kkW8ZVD5Cs1hc1A0Hu9hTeO32ihlgDiYNqDyubS6vZerbcq8s0LqR90q/9+3brNx pE3TgsJOOLP7QHYb/x4jgXMNmNyS6qyTEbruyvimXN6S4iHagIKbn09EDM1I0b/+zX4A ucILkcv3erPUEwdm+Q9pcGETjdJw3Pcl67iG9XOG3Myu4mdDvZpWs3MlQrjueSmaqWGB ktlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CWu8R92IkSi+xmhEXxL3D1J4YCsbUoX2//ne51V4bvk=; b=Sqs45IUCRNiHpS2Q71b0u1ZUGLph6Z5u8VUxwBQXT7flGm/AHxO00I41Zqpd6bmwHg 6+XWNEuNoMVeqv7nVwCwNSu7tqgmDpbbUo2l151Qy7QffKHouuz2LdBfi5B4Eh6ZWYST YJI5vSKmIASBfmvRFuAUDyzlEdCNZEqXhimzQTPUawZu1OhPlEMmT2Vb5iZyQg8x5LRn ixLLUq5LXO3AT9bpBrFmpp2C/sRZzmr7tO+MtlXLBxZj7lYT1da8CGHCAvNyMPNxkxd1 b8YVepkrgwUth5GWYkjQTC2SIRGW0cjAq416pN/Nb8KPX4XgtWftE43ED5jby+m6ePk5 mHrw== X-Gm-Message-State: AOAM533slORjzC36czS0fudRB85SbXmpnWVfibZHJG0raMOJk+FkzSvf BRNou1kFcL5d2NAuYqm0xNS5PjqOmS49U32x5Qg= X-Google-Smtp-Source: ABdhPJw4QcLhb6DzBvc1MAbFE4zL/j0wMGbBsjMWIArzFemsBpKlnw8e6MhiVZPTox5T0yiVh9brALRromR9zB4QwjY= X-Received: by 2002:a02:942e:: with SMTP id a43mr35742506jai.113.1593099222820; Thu, 25 Jun 2020 08:33:42 -0700 (PDT) MIME-Version: 1.0 References: <1593002808-29161-1-git-send-email-hkalra@marvell.com> In-Reply-To: <1593002808-29161-1-git-send-email-hkalra@marvell.com> From: Jerin Jacob Date: Thu, 25 Jun 2020 21:03:26 +0530 Message-ID: To: Harman Kalra , Ferruh Yigit Cc: Thomas Monjalon , Jerin Jacob , Nithin Dabilpuram , John McNamara , Marko Kovacevic , Kiran Kumar K , dpdk-dev Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2] net/octeontx2: add cn98xx support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Jun 24, 2020 at 6:17 PM Harman Kalra wrote: > > New cn98xx SOC comes up with two NIX blocks wrt > cn96xx, cn93xx, to achieve higher performance. > Also the no of cores increased to 36 from 24. > > Adding support for cn98xx where need a logic to > detect if the LF is attached to NIX0 or NIX1 and > then accordingly use the respective NIX block. > > Signed-off-by: Harman Kalra Acked-by: Jerin Jacob Applied to dpdk-next-net-mrvl/master. Thanks > --- > *V2: updated make/meson configs with the increased no of > cores. > > config/arm/meson.build | 2 +- > config/defconfig_arm64-octeontx2-linuxapp-gcc | 2 +- > doc/guides/platform/octeontx2.rst | 1 + > drivers/common/octeontx2/hw/otx2_rvu.h | 3 ++- > drivers/net/octeontx2/otx2_ethdev.c | 17 ++++++++++++++++- > 5 files changed, 21 insertions(+), 4 deletions(-) > > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 6e75e6d97..8728051d5 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -82,7 +82,7 @@ flags_thunderx2_extra = [ > flags_octeontx2_extra = [ > ['RTE_MACHINE', '"octeontx2"'], > ['RTE_MAX_NUMA_NODES', 1], > - ['RTE_MAX_LCORE', 24], > + ['RTE_MAX_LCORE', 36], > ['RTE_ARM_FEATURE_ATOMICS', true], > ['RTE_EAL_IGB_UIO', false], > ['RTE_USE_C11_MEM_MODEL', true]] > diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc > index 7cfb81872..0d83becf5 100644 > --- a/config/defconfig_arm64-octeontx2-linuxapp-gcc > +++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc > @@ -7,7 +7,7 @@ > CONFIG_RTE_MACHINE="octeontx2" > > CONFIG_RTE_MAX_NUMA_NODES=1 > -CONFIG_RTE_MAX_LCORE=24 > +CONFIG_RTE_MAX_LCORE=36 > CONFIG_RTE_ARM_FEATURE_ATOMICS=y > > # Doesn't support NUMA > diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst > index d38a4c1ed..7dd695175 100644 > --- a/doc/guides/platform/octeontx2.rst > +++ b/doc/guides/platform/octeontx2.rst > @@ -13,6 +13,7 @@ More information about OCTEON TX2 SoC can be found at `Marvell Official Website > Supported OCTEON TX2 SoCs > ------------------------- > > +- CN98xx > - CN96xx > - CN93xx > > diff --git a/drivers/common/octeontx2/hw/otx2_rvu.h b/drivers/common/octeontx2/hw/otx2_rvu.h > index f2037ec57..330bfb37f 100644 > --- a/drivers/common/octeontx2/hw/otx2_rvu.h > +++ b/drivers/common/octeontx2/hw/otx2_rvu.h > @@ -134,11 +134,12 @@ > #define RVU_BLOCK_ADDR_RVUM (0x0ull) > #define RVU_BLOCK_ADDR_LMT (0x1ull) > #define RVU_BLOCK_ADDR_NPA (0x3ull) > +#define RVU_BLOCK_ADDR_NIX0 (0x4ull) > +#define RVU_BLOCK_ADDR_NIX1 (0x5ull) > #define RVU_BLOCK_ADDR_NPC (0x6ull) > #define RVU_BLOCK_ADDR_SSO (0x7ull) > #define RVU_BLOCK_ADDR_SSOW (0x8ull) > #define RVU_BLOCK_ADDR_TIM (0x9ull) > -#define RVU_BLOCK_ADDR_NIX0 (0x4ull) > #define RVU_BLOCK_ADDR_CPT0 (0xaull) > #define RVU_BLOCK_ADDR_NDC0 (0xcull) > #define RVU_BLOCK_ADDR_NDC1 (0xdull) > diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c > index 3f3f0a693..095506034 100644 > --- a/drivers/net/octeontx2/otx2_ethdev.c > +++ b/drivers/net/octeontx2/otx2_ethdev.c > @@ -2177,6 +2177,20 @@ otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev) > return false; > } > > +static inline uint64_t > +nix_get_blkaddr(struct otx2_eth_dev *dev) > +{ > + uint64_t reg; > + > + /* Reading the discovery register to know which NIX is the LF > + * attached to. > + */ > + reg = otx2_read64(dev->bar2 + > + RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0)); > + > + return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1; > +} > + > static int > otx2_eth_dev_init(struct rte_eth_dev *eth_dev) > { > @@ -2236,7 +2250,6 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev) > dev->configured = 0; > dev->drv_inited = true; > dev->ptype_disable = 0; > - dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20); > dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20); > > /* Attach NIX LF */ > @@ -2244,6 +2257,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev) > if (rc) > goto otx2_npa_uninit; > > + dev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20); > + > /* Get NIX MSIX offset */ > rc = nix_lf_get_msix_offset(dev); > if (rc) > -- > 2.18.0 >