Re: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants

[Jerin Jacob <jerinjacobk@gmail.com>]

On Mon, Sep 14, 2020 at 8:39 PM Harry van Haaren
<harry.van.haaren@intel.com> wrote:
>
> This commit adds a new rte_prefetch0_write() variants, suggesting to the
> compiler to use a prefetch instruction with intention to write. As a
> compiler builtin, the compiler can choose based on compilation target
> what the best implementation for this instruction is.
>
> Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
>
> ---
>
> v2:
> - Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan)
>
> The integer constants passed to the builtin are not available as
> a #define value, and doing #defines just for this write variant
> does not seems a nice solution to me... particularly for those using
> IDEs where any #define value is auto-hinted for code-completion.
> ---
>  lib/librte_eal/include/generic/rte_prefetch.h | 49 +++++++++++++++++++
>  1 file changed, 49 insertions(+)
>
> diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h
> index 6e47bdfbad..3dfca77a74 100644
> --- a/lib/librte_eal/include/generic/rte_prefetch.h
> +++ b/lib/librte_eal/include/generic/rte_prefetch.h
> @@ -51,4 +51,53 @@ static inline void rte_prefetch2(const volatile void *p);
>   */
>  static inline void rte_prefetch_non_temporal(const volatile void *p);
>
> +/**
> + * Prefetch a cache line into all cache levels, with intention to write. This
> + * prefetch variant hints to the CPU that the program is expecting to write to
> + * the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch0_write(const void *p)

Typically DPDK coding standards is to have

static inline void
rte_prefetch0_write(const void *p)

vs
static inline void rte_prefetch0_write(const void *p)

Either way:

Reviewed-by: Jerin Jacob <jerinj@marvell.com>


> +{
> +       /* 1 indicates intention to write, 3 sets target cache level to L1. See
> +        * GCC docs where these integer constants are described in more detail:
> +        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +        */
> +       __builtin_prefetch(p, 1, 3);
> +}
> +
> +/**
> + * Prefetch a cache line into all cache levels, except the 0th, with intention
> + * to write. This prefetch variant hints to the CPU that the program is
> + * expecting to write to the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch1_write(const void *p)
> +{
> +       /* 1 indicates intention to write, 2 sets target cache level to L2. See
> +        * GCC docs where these integer constants are described in more detail:
> +        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +        */
> +       __builtin_prefetch(p, 1, 2);
> +}
> +
> +/**
> + * Prefetch a cache line into all cache levels, except the 0th and 1st, with
> + * intention to write. This prefetch variant hints to the CPU that the program
> + * is expecting to write to the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch2_write(const void *p)
> +{
> +       /* 1 indicates intention to write, 1 sets target cache level to L3. See
> +        * GCC docs where these integer constants are described in more detail:
> +        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +        */
> +       __builtin_prefetch(p, 1, 1);
> +}
> +
> +
>  #endif /* _RTE_PREFETCH_H_ */
> --
> 2.17.1
>